...
380.3 RESERVED 0003 ( RESERVED 0003 -- 0x3 )
Address: 0x9C00BE0C
Reset: 0x0000
| Field Name | Bit | Access | Description |
| Reserved | 15:0 | RW | RESERVEDReserved |
380.4 RESERVED 0004 ( RESERVED 0004 -- 0x4 )
Address: 0x9C00BE10
Reset: 0x0000
...
| Field Name | Bit | Access | Description |
| Reserved | 15:0 | RW | RESERVEDReserved |
380.5 PWR CTRL ( PWR CTRL -- 0x5 )
Address: 0x9C00BE14
Reset: 0x140f
...
| Field Name | Bit | Access | Description |
| Reserved | 15:14 | RW | RESERVEDReserved |
| aclk sel | 13:12 | RW | Audio clock freq. select (ACLK from TMDSTX) Faclk = 4*Ftclk/N. |
| oclk src sel | 11:10 | RW | Audio Sample Clock Source select (mainly for SPDIF sampling) |
| tclk edge | 9 | RW | Adjust tclk edge, 0 = : Non-inverted 1 = : Inverted |
| pclk edge | 8 | RW | Adjust pclk edge, 0 = : Non-inverted 1 = : Inverted |
| Reserved | 7:5 | RW | RESERVEDReserved |
| pd tmds n | 4 | RW | Power down TMDSTX PHY, 0 = : pwr down, 1 = : normal |
| pd tclk | 3 | RW | Power down tclk domain, 0 = : pwr down 1 = : normal |
| pd fclk n | 2 | RW | Power down fclk domain, 0 = : pwr down 1 = : normal |
| pd pclk n | 1 | RW | Power down pclk domain, 0 = : pwr down 1 = : normal |
| pd total n | 0 | RW | Power down all, 0 = : pwr down, 1 = : normal |
380.6 SW RESET ( SW RESET -- 0x6 )
Address: 0x9C00BE18
Reset: 0x00e9
| Field Name | Bit | Access | Description |
| Reserved | 15:8 | RW | RESERVEDReserved |
| TMDS_rst_b | 7 | RW | TMDS reset 0 = : reset, 1 = : normal |
| Audio_rst_b | 6 | RW | Audio reset 0 = : reset, 1 = : normal |
| Video_rst_b | 5 | RW | Video reset 0 = : reset, 1 = : normal |
| RW afifo_lp_en | 4 | RW | Audio FIFO Low Power Enable 0 = : disable, 1 = : enable |
| CEC_rst_b | 3 | RW | CEC reset 0 = : reset, 1 = : normal |
| HDCP_rst_b | 2 | RW | HDCP Engine reset 0 = : reset, 1 = : normal |
| FIFO_rst_b | 1 | RW | Audio FIFO reset 0 = : reset, 1 = : normal |
| SW_ rst_b | 0 | RW | Software reset 0 = : reset, 1 = : normal |
380.7 SYSTEM STATUS ( SYSTEM STATUS 0x7 )
Address: 0x9C00BE1C
...
| Field Name | Bit | Access | Description |
| Reserved | 15:4 | RW | RESERVEDReserved |
| tmds clkdetect | 3 | RU | TMDS clock detect. (Clock sources from TMDS PHY) 0 = : No TMDS clock. 1 = : TMDS clock exist |
| pll_ready | 2 | RU | Internal PLL ready. (for reference only) 0 = : Not ready. 1 = : Ready |
| hpd_in | 1 | RU | Hot Plug Detect status 0 = : No Hot Plug. 1 = : Hot Plug In (Usually means HDMI RX is connected) |
| rsen in | 0 | RU | HDMI RX sense 0 = : No Rx. 1 = : Rx active (HDMI RX is powered) |
...
| Field Name | Bit | Access | Description | ||||
| ctl defaultReserved | 15:12 | RW | CTL[3:0] Debug use. Do not alternate it. debug 的可以變成 Reserve 嗎 ? | Reserved | |||
| Reserved | 11:3 | RW | RESERVEDReserved | ||||
| null packet en | 2 | RW | Auto null packet enable 0: Disable NULL packet 1: Enable NULL packet | ||||
| tmds dbus selReserved | 1 | RW | 30/60bits TMDS bus select. (Only for RD use) For RD use 的可以變成 Reserve 嗎 ? | hdmi mode | 0 | Reserved | |
| hdmi mode | 0 | RW | HDMI mode or DVI mode. 0 = : DVI mode. 1 = : HDMI mode |
380.9 RESERVED 0009 ( RESERVED 0009 -- 0x9 )
Address: 0x9C00BE24
Reset: 0x0000
| Field Name | Bit | Access | Description |
| Reserved | 15:0 | RW | RESERVEDReserved |
380.10 SYSTEM CTRL2 ( SYSTEM CTRL2 -- 0xa )
Address: 0x9C00BE28
Reset: 0x0000
For RD use 的可以變成 Reserve 嗎 ?
| Field Name | Bit | Access | Description | |
| Reserved | 15:3 | RW | RESERVEDReserved | |
| tclkd2 edgeReserved | 2 | RW | tclkd2 edge select. (Only for RD use) For RD use 的可以變成 Reserve 嗎 ? | |
| tst tclkd2 | 1 | RW | tclkd2 test. (Only for RD use) 0 = From TMDS. 1 = From pclkd2 | |
| tst tclk Reserved | ||||
| Reserved | 1 | RW | Reserved | |
| Reserved | 0 | RW | tclk test. (Only for RD use) 0 = From TMDS. 1 = From pclk | Reserved |
380.11 SYSTEM CTRL3 ( SYSTEM CTRL3 -- 0xb )
Address: 0x9C00BE2C
...
| Field Name | Bit | Access | Description |
| Reserved | 15:0 | RW | RESERVEDReserved |
380.14 RESERVED 000E ( RESERVED 000E -- 0xe )
Address: 0x9C00BE38
Reset: 0x0000
...
| Field Name | Bit | Access | Description |
| Reserved | 15:0 | RW | RESERVEDReserved |
380.15 SYSTEM CTRL5 ( SYSTEM CTRL5 -- 0xf )
Address: 0x9C00BE3C
Reset: 0x8000 0x8000
這些應該可以改成 RESERVE
| Field Name | Bit | Access | Description | VIDEO
| Reserved | 15:0 | RW | Useless, please do not modify it |
| CARBON ONLY MODE | 14 | RW | Useless, please do not modify it |
| Reserved | 13:11 | RW | Reserved |
| PCLK SRC SEL | 10 | RW | Useless, please do not modify it |
| PLLTV EN MODE | 9 | RW | Useless, please do not modify it |
| TMDSTX ONLY MODE | 8 | RW | Useless, please do not modify it |
| Reserved | 7:5 | RW | Reserved |
| DUMMY GPIO MODE | 4 | RW | Useless, please do not modify it |
| SW SCAN MODE | 3 | RW | Useless, please do not modify it |
| SW BIST MODE | 2 | RW | Useless, please do not modify it |
| CEC PROBE MODE | 1 | RW | Useless, please do not modify it |
| OTP PGM MODE | 0 | RW | Useless, please do not modify it |
...
| Field Name | Bit | Access | Description |
| Reserved | 15:12 | RW | Reserved |
| HDf_BKSV_error | 11 | RO | 全名 ? 1'b1: the BKSV value of HDMI receiver is error |
| RO HDf_AKSV_error | 10 | RO | 全名 ? 1 = the AKSV value of HDMI transmitter is error |
| HDf AKSV ready | 9 | RO | 全名 ? 1 = AKSV is ready in HDMI transmitter |
| HDt_R0_ready | 8 | RO | 全名 ? 1 = Ri is ready in HDMI transmitter |
| Reserved | 7:4 | RW | Reserved |
| FreeAn_gen | 3 | RO | 全名 ? 1 = The cipher engine is free running to generate AN |
| Repeater | 2 | RW | 全名 ? 1 = HDMI receiver is a Repeater |
| HDCP 1p1 Feature | 1 | RW | 全名 ? 1 = enable Bcaps bit 1.1 FEATURES |
| HDCP Encryption | 0 | RW | 全名 ? 1= enable HDCP encryption0 = disable HDCP encryptionReserved |
380.16 HDCP CTRL1 ( HDCP CTRL1 -- 0x10 )
Address: 0x9C00BE40
Reset: 0x0008
| Field Name | Bit | Access | Description |
| Reserved | 15:0 | RW | Reserved |
380.17 BKSV12 ( BKSV12 -- 0x11 )
Address: 0x9C00BE44
Reset: 0x0000
...
| Field Name | Bit | Access | Description |
| BKSV[15:0]Reserved | 15:0 | RW | the LSB BKSV value of HDMI receiver (BKSV 是什麼的縮寫?)Reserved |
380.18 BKSV34 ( BKSV34 -- 0x12 )
Address: 0x9C00BE48
Reset: 0x0000
...
| Field Name | Bit | Access | Description |
| BKSV[31:16]Reserved | 15:0 | RW | the BKSV[31:16] value of HDMI receiverReserved |
380.19 BKSV5 ( BKSV5 -- 0x13 )
Address: 0x9C00BE4C
Reset: 0x0000
| Field Name | Bit | Access | Description |
| Reserved | 15:80 | RW | Reserved |
| BKSV[39:32] | 7:0 | RW | the BKSV[39:32] value of HDMI receiver |
380.20 Mi12 ( Mi12 -- 0x14 )
Address: 0x9C00BE50
Reset: 0x0000
...
| Field Name | Bit | Access | Description | |
| HDt Mi[15:0]Reserved | 15:0 | RO | the AN/Mi[15:0] value of HDMI transmitterRW | Reserved |
380.21 Mi23 ( Mi23 -- 0x15 )
Address: 0x9C00BE54
Reset: 0x0000
...
| Field Name | Bit | Access | Description | |
| HDt Mi[31:16]Reserved | 15:0 | RO | the AN/Mi[31:16] value of HDMI transmitterRW | Reserved |
380.22 Mi56 ( Mi56 -- 0x16 )
Address: 0x9C00BE58
Reset: 0x0000
...
| Field Name | Bit | Access | Description | |
| HDt Mi[47:32]Reserved | 15:0 | RO | the AN/Mi[47:32] value of HDMI transmitterRW | Reserved |
380.23 Mi78 ( Mi78 -- 0x17 )
Address: 0x9C00BE5C
Reset: 0x0000
| Field Name | Bit | Access | Description | |
| HDt Mi[63:48]Reserved | 15:0 | RO | the AN/Mi[63:48] value of HDMI transmitterRW | Reserved |
380.24 AKSV12 ( AKSV12 -- 0x18 )
Address: 0x9C00BE60
Reset: 0x0000
...
| Field Name | Bit | Access | Description | |
| HDf AKSV[15:0]Reserved | 15:0 | RO | the AKSV[15:0] value of HDMI transmitterRW | Reserved |
380.25 AKSV23 ( AKSV23 -- 0x19 )
Address: 0x9C00BE64
Reset: 0x0000
...
| Field Name | Bit | Access | Description | |
| HDf AKSV[31:16]Reserved | 15:0 | RO | the AKSV[31:16] value of HDMI transmitterRW | Reserved |
380.26 AKSV5 ( AKSV5 -- 0x1a )
Address: 0x9C00BE68
Reset: 0x0000
...
| Field Name | Bit | Access | Description |
| Reserved | 15:80 | RW | Reserved |
| HDf AKSV[39:32] | 7:0 | RO | the AKSV[39:32] value of HDMI transmitter |
380.27 Ri CMP ( Ri CMP -- 0x1b )
Address: 0x9C00BE6C
...
| Field Name | Bit | Access | Description | |
| HDt Ri compareReserved | 15:0 | RO | the Ri value of HDMI transmitterRW | Reserved |
380.28 Rj CMP ( Rj CMP -- 0x1c )
Address: 0x9C00BE70
Reset: 0x0000
...
| Field Name | Bit | Access | Description | |||
| Reserved | 15:80 | RW | ReservedHDt Pj compare | 7:0 | RO | the Pj value of HDMI transmitter |
380.29 Ri CMP SET ( Ri CMP SET -- 0x1d )
Address: 0x9C00BE74
Reset: 0x0000
...
0x9C00BE74
Reset: 0x0000
| Field Name | Bit | Access | Description |
| Reserved | 15:0 | RW | Indicates at what frame to do Auto-Ri compareReserved |
380.30 FrameCnt ( FrameCnt -- 0x1e )
Address: 0x9C00BE78
Reset: 0x0000
...
| Field Name | Bit | Access | Description | |
| DBf RXRIReserved | 15:0 | RO | the Ri value of HDMI receiverRW | Reserved |
381.3 RXPj ( RXPj -- 0x23 )
Address: 0x9C00BE8C
...
| Field Name | Bit | Access | Description | ||||
| Reserved | 15:80 | RW | Reserved | DBf RXPJ | 7:0 | RO | the Pj value of HDMI receiver |
381.4 HDCP TEST ( HDCP TEST -- 0x24 )
Address: 0x9C00BE90
Reset: 0x0000
...
| Field Name | Bit | Access | Description | |
| Reserved | 15: | 30 | RW | Reserved |
| reload AKSV | 2 | WO | 1 = Reload AKSV of HDMI transmitter. (Enable this when AKSV is error or after SW reset) | |
| HDCP Bist2 En | 1 | WO | 1 = Enable HDMI Self-Test#2 | |
| HDCP Bist1 En | 0 | WO | 1 = Enable HDMI Self-Test#1 |
381.5 HDCP TEST RESULT ( HDCP TEST RESULT -- 0x25 )
Address: 0x9C00BE94
Reset: 0x0000
| Field Name | Bit | Access | Description | |||||
| Reserved | 15:4 | RW | Reserved | |||||
| HDf HDCP Bist2 err | 3 | RO | 1 = HDMI Self-Test#2 Fail flag 0: HDMI Self-Test#2 Pass | |||||
| HDf HDCP Bist2 done | 2 | RO | HDMI Self-Test#2 Done flag 0 | = : HDMI Self-Test#2 | PassHDf HDCP Bist2 done | 2 | RO | 1 = not Done 1: HDMI Self-Test#2 Done |
| HDf HDCP Bist1 err | 1 | RO | 1 = HDMI Self-Test#1 Fail flag 0 =: HDMI Self-Test#1 Pass | |||||
| HDf HDCP Bist1 done | 0 | RO | HDMI Self-Test#1 Done flag 0: HDMI Self-Test#1 not Done 1 = : HDMI Self-Test#1 DoneWhen this bit is 1, then check the following result. |
...
381.7 APO SPDIF CHNL STS1 ( APO SPDIF CHNL STS1 -- 0x27 )
Address: 0x9C00BE9C
Reset: 0x0000
| Field Name | Bit | Access | Description |
| APo spdif chnl sts[31:16] | 15:0 | RO | Channel status[31:16] of SPDIF |
...
| Field Name | Bit | Access | Description |
| Reserved | 15:3 | RW | vReserved |
| asp urgent en | 2 | RW | Audio Sample Packet Urgent Enable (left it default) 0: Disable ASP urgent 1: Enable ASP urgent |
| bw ctrl en | 1 | RW | Audio bandwidth control register. 0: Disable 1: Enable |
| spdif adaptive ui en | 0 | RW | Adaptive ui control register. 0: Disable 1: Enable |
...
| Field Name | Bit | Access | Description |
| Reserved | 15:3 | RW | Reserved |
| csc man dst c | 2 | RW | CSC man mode for RL2RF/RF2RL/YL2YF/YF2YL 0 = : keep hw definition of destination side color space 1 = : change hw definition of destination side color space |
| csc man src c | 1 | RW | CSC man mode for RL2RF/RF2RL/YL2YF/YF2YL 0 = : keep hw definition of source side color space 1 = : change hw definition of source side color space |
| blvipa en | 0 | RW | Internal blank video switch 0 = : Disable 1 = : Enable |
381.13 BLVPA0 ( BLVPA0 -- 0x2d )
Address: 0x9C00BEB4
Reset: 0x0000
...
| Field Name | Bit | Access | Description |
| vs_pol_reg | 15 | RW | vsync polarity 0: negative sync 1 = : positive sync0 = negative sync |
| hs_pol_reg | 14 | RW | hsync polarity 1 = positive sync 0 = : negative sync 1: positive syncc |
| sync_pol_set | 13 | RW | video sync polarity settings: 0 = : auto 1 = : controlled by registers (0x10[15:14]) |
| downsample | 12 | RW | 1 = down-sample enable 1: 444 to 422 enable (down-sample) Only valid in YC mode. |
| upsample | 11 | RW | up-sample enable 0: disable (up-sample) 1: 422 to 444 enable (up-sample) Only valid in YC mode. |
| Reserved | 10 | RW | Reserved |
| csc_man | 9 | RW | 1 = color space coversion coefficients overrided with registerscoefficient control 0 =: color space coversion coefficient is predefined. |
| csc_en | 8 | RW | color space coversion enable 1 =0: color space coversion disable 1: color space coversion enable |
| csc_mode | 7:4 | RW | color space conversion mode: bit [0] 0=limit range ycc, 1=full range ycc bit [1] 0=limit range rgb, 1=full range rgb bit [2] 0=r2y, 1=y2r bit [3] 0=601 (SSD), 1=709 (HD) |
| pix rep | 3:0 | RW | pixel repitition: 0 = no repeat 1 = sent 2 times 2 = sent 3 times 3 = sent 4 times 4 = sent 5 times 5 = sent 6 times 6 = sent 7 times 7 = sent 8 times 8 = sent 9 times 9 = sent 10 times |
...
| Field Name | Bit | Access | Description |
| Reserved | 15:5 | RW | Reserved |
| tdither en | 4 | RW | enable time domain dithering 0: disable time domain dithering 1 =: enable time domain dithering ,
|
| dither mode | 3:1 | RW | dithering mode 0 = 0x0: dither off 1 = 0x1: dither on, 16bits to 12bits 2 = 0x2: dither on, 16bits to 10bits 3 = 0x3: dither on, 16bits to 8bits 4 = 0x4: dither on, 12bits to 10bits 5 = 0x5: dither on, 12bits to 8bits 6 = 0x6: dither on, 10bits to 8bits |
| dither en | 0 | RW | 1 = dithering enable 0: dithering disable 1: dithering enable |
381.20 VIDEO PAT GEN1 ( VIDEO PAT GEN1 -- 0x34 )
Address: 0x9C00BED0
Reset: 0x0000
| Field Name | Bit | Access | Description |
| Reserved | 15:13 | RW | Reserved |
| vg inter mode | 12:11 | RW | interlaced internal pattern resolution selection: 0 = : disable 1 = : 480i 2 = : 576i 3 = : 1080i |
| pat res | 10:8 | RW | internal pattern resolution selection: 0 = : 480p 1 = : 720p 2 = : 1080p 3 = : 4k x 2k @ 24Hz 7 = : registers define (reg: 0x15 0x1C) (other setting are un-defined) |
| gray step | 7:6 | RW | gray level steps: 0 = : 1 step 1 = : 4 steps 2 = : 16 steps 3 = : 64 steps |
| yc_HD_SD | 5 | RW | ycc color bar pattern with HD or SD: 0 = : SD (601) 1 = : HD (709) |
| yc444_yc422 | 4 | RW | YC sample selection, ycc444 or ycc422: 0 = : ycc422 1 = : ycc444 |
| rgb_yc | 3 | RW | Color space selection, rgb or ycc: 0 = : ycc 1 = : rgb |
| vs_inv | 2 | RW | Invert vsync 1 =0: not Invert vsync |
| hs_inv | 1 | RW | 1 = Invert hsync 0: not Invert hsync |
| pattern en | 0 | RW | enable internal pattern generation 1 = enable0: disable internal pattern generation |
381.21 VIDEO PAT GEN2 ( VIDEO PAT GEN2 -- 0x35 )
Address: 0x9C00BED4
Reset: 0x0000
...
| Field Name | Bit | Access | Description |
| Reserved | 15:8 | RW | Reserved |
| ColorDepth | 7:4 | RW | color depth (deep color): 4'b0100 = : 24 bits per pixel (8 bits per channel) 4'b0101 = 5: 30 bits per pixel (10 bits per channel) 4'b0110 = 6: 36 bits per pixel (12 bits per channel) 4'b0111 = 7: 48 bits per pixel (16 bits per channel) |
| Reserved | 3:2 | RW | Reserved |
| hsync out neg | 1 | RW | Output Hsync polarity 0: positive output 1 = : negative output0 = positive output |
| vsync out neg | 0 | RW | Output Vsync polarity 1 = negative output 0 = : positive output 1: negative output |
382.13 RESERVED 020D ( RESERVED 020D -- 0x4d )
Address: 0x9C00BF34
Reset: 0x0000
...
| Field Name | Bit | Access | Description |
| i2s ch3 map | 15:14 | RW | I2S audio channel map. SD3 mapped to ch[n], 0=0 3 |
| i2s ch2 map | 13:12 | RW | I2S audio channel map. SD2 mapped to ch[n], 0=0 3 |
| i2s ch1 map | 11:10 | RW | I2S audio channel map. SD1 mapped to ch[n], 0=0 3 |
| i2s ch0 map | 9:8 | RW | I2S audio channel map. SD0 mapped to ch[n], 0=0 3 |
| i2s_ch3_en | 7 | RW | I2S ch3 enable. 1: enable, 0: disable |
| i2s_ch2_en | 6 | RW | I2S ch2 enable. 1: enable, 0: disable |
| i2s_ch1_en | 5 | RW | I2S ch1 enable. 1 = enable, 0 = : disable 1: enable |
| i2s_ch0_en | 4 | RW | I2S ch0 enable. 0: disable 1 = : enable, 0 = disable |
| i2s_hbr_mode | 3 | RW | I2S input in HBR mode 1 = 0: Non-HBR mode 0 = Non-1: HBR mode |
| audio_mute | 2 | RW | Audio mute. 0 = normal 1 = mute, 0 = normal |
| audio layout | 1 | RW | Audio Packet layout. Check HDMI spec. 7.6 |
| audio en | 0 | RW | Audio Enable. 0: disable 1 = Enable, 0 = Disable: enable |
382.17 AUDIO CTRL2 ( AUDIO CTRL2 -- 0x51 )
Address: 0x9C00BF44
Reset: 0x01b4
| Field Name | Bit | Access | Description |
| Reserved | 15:10 | RW | Reserved |
| i2s v bit | 9 | RW | I2S V bits in channel status |
| i2s max length | 8 | RW | I2S sample maximum length. 0: 20bits 1 = : 24bits, 0 = 20bits |
| i2s sample length | 7:5 | RW | I2S sample length. 101 = 24 (20) bits (max length=1 (max length=0)) 100 = 23 (19) bits (max length=1 (max length=0)) 010 = 22 (18) bits (max length=1 (max length=0)) 110 = 21 (17) bits (max length=1 (max length=0)) 001 = 20 (16) bits (max length=1 (max length=0)) |
| i2s_philips_shift | 4 | RW | I2S shift. 0 = : no shift, 1 = : delay one bit of sd to ws |
| i2s_data_dir | 3 | RW | I2S data direction. 0 = : MSb first, 1 = : LSb first |
| i2s_left_justify | 2 | RW | I2S data left justify. 0 = : right justify, 1 = : left justify |
| i2s ws polarity | 1 | RW | I2S WS polarity. 0 = : when WS=1 -> Left ch., 1 = : when WS=0 -> Left ch. |
| sck edge | 0 | RW | I2C SCK edge select 0 = Non: Non-inverted |
382.18 AUDIO SPDIF CTRL ( AUDIO SPDIF CTRL -- 0x52 )
Address: 0x9C00BF48
Reset: 0x0020
| Field Name | Bit | Access | Description |
| APo spdif sample error | 15 | RO | SPDIF Sample Error. 1 = 0: not found, 0 = not 1: found |
| APo spdif parity error | 14 | RO | SPDIF Parity Error. 1 = 0: not found, 0 = not 1: found |
| APo spdif bi phase error | 13 | RO | SPDIF Phase Error. 1 = 0: not found, 0 = not 1: found |
| APo spdif ui min found | 12 | RO | SPDIF min UI found. 1 = 0: not found, 0 = not 1: found. Max and min UI found means the SPDIF is locked |
| APo spdif ui max found | 11 | RO | SPDIF max UI found. 1 = 0: not found, 0 = not 1: found |
| spdif_sw_ui_en | 10 | RW | SPDIF SW UI interval enable. (Only for RD debug use) 0: disable 1 = : enable, 0 = disable |
| spdif_v_bit | 9 | RW | SPDIF V bit in channel status |
| spdif sw chnl sts en | 8 | RW | SPDIF SW channel status. 1 = Overwrite the original 0: Use the channel status in from SPDIF stream 0 = Use the 1: Overwrite the original channel status from in SPDIF stream |
| spdif hbr mode | 7 | RW | SPDIF HBR mode. Useless |
| spdif phase | 6:5 | RW | SPDIF input phase. (Only for RD adjustment) Adust this value for optimal SPDIF sampling |
| spdif sp en | 4:1 | RW | SPDIF sample packet enable setting when layout = 0. Check HDMI spec. 7.6 |
| spdif en | 0 | RW | SPDIF input enable. 0: disable 1 = : enable, 0 = disable |
382.19 AUDIO SPDIF SW UI ( AUDIO SPDIF SW UI -- 0x53 )
Address: 0x9C00BF4C
...
| Field Name | Bit | Access | Description | |
| Reserved | 15:8 | RW | Reserved | |
| APm acr CTS error | 7 | RU | ACR CTS value is too small (CTS <1024) When this bit = 1, check the audio configuration. | |
| APm acr CTS valid | 6 | RU | ACR CTS valid flag. 0: error 1 = : valid.0 = error | |
| fs over 192k | 5 | RW | When input audio Fs is larger than 192KHz. | |
| acr MCLK over Fs | 4:2 | RW | MCLK/Fs ratio selection. 000 0: MCLK = 128Fs 001 1: MCLK = 256Fs 010 2: MCLK = 384Fs 011 3: MCLK = 512Fs 100 4: MCLK = 768Fs 101 5: MCLK = 1024Fs 110 6: MCLK = 1152Fs 111 7: MCLK = 192Fs | |
| acr sw CTS enReserved | 1 | RW | ACR SW CTS enable. (Only for RD debug use) 1 = enable, 0 = disable | Reserved |
| acr pkt en | 0 | RW | HDMI ACR packet enable. 0: disable 1 = : enable,0 = disable |
382.27 ACR N VALUE1 ( ACR N VALUE1 -- 0x5b )
Address: 0x9C00BF6C
...
| Field Name | Bit | Access | Description |
| Reserved | 15:2 | RW | Reserved |
| IRs intr state | 1 | RO | Interrupt status. 0: disassert 1 = assert, 0 = disassert.: assert One of intr[n] status asserted, this bit will be set to 1. (n=0 2) |
| intr polarity | 0 | RW | Interrupt Output polarity. 0: positive 1 = : negative,0 = positive |
383.1 INTR0 UNMASK ( INTR0 UNMASK -- 0x61 )
Address: 0x9C00BF84
Reset: 0x0000
...
| Field Name | Bit | Access | Description |
| intr0 status | 15:0 | RO | Interrupt status. 0: disassert 1 = : asserted. 0 = disassert. Write "0" to individual bit to clear. Mapping [0] Hot Plug change detect [1] HDMI RX sense change detect [2] tclk frequency change detect [3] every Vsync occurs [4] CEC ingterrupt, reference to "CEC STS2" [9] CTS value changed detect [10] Audio FIFO empty [11] Audio FIFO full [12] SPDIF preamble error (reserved) [13] SPDIF sample drop (reserved) [14] SPDIF bi-phase error (reserved) [15] SPDIF parity error (reserved) |
...
| Field Name | Bit | Access | Description |
| intr1 status | 15:0 | RU | Interrupt status. 0: disassert 1 = : asserted. 0 = disassert. Write "0" to individual bit to clear Mapping [0] every 128 HDCP frames [1] every 16 HDCP frames [2] DDC FIFO full [3] DDC FIFO empty [4] Auto Ri check fail @ frame0 [5] Auto Ri check fail @ frame127 [6] Tx Ri does not change between frame 0 and frame 127 [7] Ri/Pj is not read within one frame or DDC bus error [8] Auto Pj check fail @ frame 15 [9] Tx Pj does not change between frame 0 and frame 15 |
...
| Field Name | Bit | Access | Description |
| intr2 status | 15:0 | RO | Interrupt status. (Reserved) 0: disassert 1 = : asserted. 0 = disassert. Write "0" to individual bit to clear |
...
| Field Name | Bit | Access | Description |
| 2C DLY CNT | 15:6 | RW | DDC cycle count. Fine tune the DDC bus operation freq. |
| Reserved | 5 | RW | Reserved |
| DBf SW DDC I2C SDA IN | 4 | RU | DDC SDA input state in Software DDC Mode 1 = 0: Detect DDC SCL SDA line is highlow 0 = 1: Detect DDC SCL SDA line is lowhigh |
| DBf SW DDC I2C SCL IN | 3 | RU | DDC SCL input state in Software DDC Mode 1 = 0: Detect DDC SCL line is highlow 0 = 1: Detect DDC SCL line is lowhigh |
| SW DDC I2C SDA OUT | 2 | RW | DDC SDA output value in Software DDC Mode 1 = 0: Drive DDC SCL SDA line highlow 0 = 1: Drive DDC SCL SDA line lowhigh |
| SW DDC I2C SCL OUT | 1 | RW | DDC SCL output value in Software DDC Mode 1 = 0: Drive DDC SCL line highlow 0 = 1: Drive DDC SCL line lowhigh |
| SW DDC I2C En | 0 | RW | Enable Software DDC Mode 1 = Enable0: Disable Software DDC Mode |
383.8 DDC SLV DEVICE ADDR ( DDC SLV DEVICE ADDR -- 0x68 )
Address: 0x9C00BFA0
Reset: 0x0074
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| Field Name | Bit | Access | Description |
| Reserved | 15:4 | RW | Reserved |
| DDC cmd | 3:0 | RW | DDC command 0= : Fast Read 1= : Sequential Read 2= : Sequential Write with last byte ACK 3= : Sequential Write without last byte ACK 4= : Segment Read 5= : Clear FIFO 6= : Clock SCL 7= : Abort Command |
383.13 DDC STS ( DDC STS 0x6d )
Address: 0x9C00BFB4
Reset: 0x0000
| Field Name | Bit | Access | Description |
| Reserved | 15:7 | RW | Reserved |
| DBf DDCFIFO empty | 6 | RU | 1 = DDC DDC FIFO is empty flag 0: DDC FIFO is not empty |
| DBf DDCFIFO full | 5 | RU | 1 = DDC DDC FIFO is full flag 0: DDC FIFO is not full |
| DBf DDCFIFO in read | 4 | RU | 1 = DDC FIFO is in read progress flag 0: DDC FIFO is not in read progress |
| DBf DDCFIFO in write | 3 | RU | 1 = DDC FIFO is in write progress flag 0: DDC FIFO is not in write progress |
| DBf DDC I2C no ack | 2 | RU | 1 = DDC bus did not receive an ACK flag 0: DDC bus receive an ACK |
| DBf DDC I2C bus low | 1 | RU | 1 = DDC bus low flag 0: DDC bus high |
| DBf DDC cmd done | 0 | RU | 1 = DDC command done flag 0: DDC command does not done |
383.14 DDC DATA ( DDC DATA -- 0x6e )
Address: 0x9C00BFB8
Reset: 0x0000
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| Field Name | Bit | Access | Description |
| Reserved | 15:2 | RW | Reserved |
| gpio mode | 1 | RW | CEC gpio mode 0 = : HW mode— hardware mode 1 = : GPIO mode — gpio mode |
| gpio drv | 0 | RW | CEC gpo mode drive 0 = : ON — drive CEC line low 1 = : OFF — don't drive CEC line |
...
| Field Name | Bit | Access | Description |
| Reserved | 15:11 | RW | Reserved |
| CECf in filtered | 10 | RO | Cec line status (filtered) 0 = : low 1 = : high |
| IO cec i | 9 | RO | Cec line status 0 = : low 1 = : high |
| CECf ack sts | 8 | RO | Received ack status (as a initiator) |
| Reserved | 7:6 | RW | Reserved |
| auto stp dis | 5:2 | RW | CEC send auto-stop (initiator) disable auto stp dis[0]: arbitration fails auto stp dis[1]: cec frame set auto stp dis[2]: noack dectected (when cec set) |
| cec eom sed | 1 | RW | CEC RESERVED |
| cec out en | 0 | RW | CEC send (initiator) enable 0: disable 1 = : enable0 = disable |
383.20 CEC CONGIF3 ( CEC CONGIF3 -- 0x74 )
Address: 0x9C00BFD0
Reset: 0x0000
| Field Name | Bit | Access | Description |
| Reserved | 15:14 | RW | Reserved |
| cec frm rcv en | 13 | RW | CEC frame (blocks) received (as a follower) interrupt en- able 0: disable 1 = : enable 0 = disable |
| cec blk rcv en | 12 | RW | CEC data or header blocks received (as a follower) inter- rupt enable 0: disable 1 = : enable0 = disable |
| cec eom rcv en | 11 | RW | CEC EOM bit (as a follower) interrupt enable 0: disable 1 = : enable0 = disable |
| cec_err_rcv_en | 10 | RW | CEC line error notification received (as a follower) inter- rupt 0: disable 1 = : enable0 = disable |
| cec fall edge en | 9 | RW | CEC GPIO falling edge interrupt enable 0: disable 1 = : enable0 = disable |
| cec rise edge en | 8 | RW | CEC GPIO rising edge interrupt enable 0: disable 1 = : enable0 = disable |
| Reserved | 7:5 | RW | Reserved |
| cec noack sed en | 4 | RW | CEC noack detected (as a initiator) interrupt enable 0: disable 1 = : enable 0 = disable |
| cec frm sed en | 3 | RW | CEC frame (blocks) sent(as a initiator) interrupt enable 0: disable 1 = : enable0 = disable |
| cec blk sed en | 2 | RW | CEC RESERVED |
| cec line error sed en | 1 | RW | CEC line error notification received (as a initiator) inter- rupt enable 0: disable 1 = : enable 0 = disable |
| cec free timeup en | 0 | RW | CEC free line timed up (as a initiator) interrupt enable 0: disable 1 = : enable 0 = disable |
383.21 CEC CMD ( CEC CMD -- 0x75 )
Address: 0x9C00BFD4
Reset: 0x0000
| Field Name | Bit | Access | Description |
| Reserved | 15:14 | RW | Reserved |
| cec sed frm en | 13 | RW | CEC send frame (initiator) enable 0: disable 1 = : enable 0 = disable |
| cec sed bc | 12:8 | CEC send frame byte count (>=1) | |
| Reserved | 7:3 | RW | Reserved |
| cec free timer str | 2 | WO | CEC free timer start ( Write 1 to start) 0: disable 1 = : enable0 = disable |
| cec start sed | 1 | WO | Start bit and frame block trigger ( Write 1 to trigger) 0: disable 1 = : enable 0 = disable |
| cec blk sed | 0 | WO | Frame or data block trigger (Write 1 to trigger, content refers to Cec DATA SED) 0: disable 1 = : enable 0 = disable |
383.22 CEC TIMER ( CEC TIMER -- 0x76 )
Address: 0x9C00BFD8
Reset: 0x0000
| Field Name | Bit | Access | Description |
| cec free timer up en | 15 | RW | CEC free timer counting up enable 0 = : disable 1 = enable ( Reading cec free timer value will get the cor- rect cec free time directly .): enable |
| Reserved | 14:9 | RW | Reserved |
| cec free timer | 8:0 | RW | CEC timer setting for CEC signal free time (0.05ms ticks, 24ms max) Writing CEC FREE TIMER STR will start the down counting. |
...
| Field Name | Bit | Access | Description |
| Reserved | 15:11 | RW | Reserved |
| cec in en | 10 | RW | CEC receive (follower) enable 0: disable 1 = : enable 0 = disable |
| cec header ack | 9 | RW | follower cec header block ack 1 = 0: no ack — ( cec line is low high for normal message, and high low for broadcast message) 0 = no 1: ack — ( cec line is high low for normal message, and low high for broadcast message) |
| cec data ack | 8 | RW | follower cec data block ack 1 = 0: no ack — ( cec line is low high for normal message, and high low for broadcast message) 0 = no 1: ack — ( cec line is high low for normal message, and low high for broadcast message) |
| CECf data rcv | 7:0 | RO | CEC data received (Read it to get content of the received block.) cec data ack8 RW |
...
| Field Name | Bit | Access | Description | |
| Reserved | 15:11 | RW | Reserved | |
| sram bc en | 10 | RW | CEC command byte count queue enable 0: disable 1 = : enable 0 = disable | |
| sram en | 9 | RW | CEC command queue enable 0: disable 1 = : enable0 = disable | |
| cec rcv frm en | 8 | RW | CEC frame (follower) enable 0: disable 1 = : enable0 = disable | |
| Reserved | 7:2 | RW | Reserved | |
| CECf eom sts | 1 | RO | Received eom status (as a follower) Reserved | Received |
| CECf blk sts | 0 | RO | Received block status (as a follower) 0: data 1 = : header0 = data |
383.27 CEC STS2 ( CEC STS2 0x7b )
Address: 0x9C00BFEC
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| Field Name | Bit | Access | Description |
| auinfo pkt rpt spa | 15:12 | RW | every "pkt rpt spa" VSYNC to transmit Audio InfoFrame packet |
| Reserved | 11 | RUW | Reserved |
| auinfo pkt tx | 10 | RW | Transmit Audio InfoFrame immediately. pkt rpt = 0 |
| auinfo pkt rpt | 9 | RW | Transmit Audio InfoFrame repeatly. 0: Once 1 = : repeated. 0 = Once |
| auinfo pkt en | 8 | RUW | Audio InfoFrame Enable. 1 = Enable, 0 = Disable0: disable 1: enable |
| aviinfo pkt rpt spa | 7:4 | RW | every "pkt rpt spa" VSYNC to transmit AVI InfoFrame packet |
| Reserved | 3 | RUW | Reserved |
| aviinfo pkt tx | 2 | RW | Transmit AVI InfoFrame immediately. pkt rpt = 0 |
| aviinfo pkt rpt | 1 | RW | Transmit AVI InfoFrame repeatly. 0: Once 1 = : repeated.0 = Once |
| aviinfo pkt en | 0 | RUW | AVI InfoFram Enable. 0: disable 1 = Enable, 0 = Disable: enable |
385.1 InfoFrame CTRL2 ( InfoFrame CTRL2 0xa1 )
Address: 0x9C00C084
Reset: 0x1010
| Field Name | Bit | Access | Description |
| acp pkt rpt spa | 15:12 | RW | every "pkt rpt spa" VSYNC to transmit ACP packet. |
| Reserved | 11 | RUW | Reserved |
| acp_pkt_tx | 10 | RW | Transmit ACP packet immediately. pkt rpt = 0 |
| acp_pkt_rpt | 9 | RW | Transmit ACP packet repeatly. 1: repeated. 0: Once |
| acp_pkt_en | 8 | RUW | ACP packet Enable. 1 = Enable, 0 = Disable0: disable 1: enable |
| gc pkt rpt spa | 7:4 | RW | every "pkt rpt spa" VSYNC to transmit GC packet |
| Reserved | 3 | RW | Reserved |
| gc pkt tx | 2 | RW | Transmit GC packet immediately. pkt rpt = 0 |
| gc pkt rpt | 1 | RW | Transmit GC packet repeatly. 0: Once 1 = : repeated.0 = Once |
| gc pkt en | 0 | RW | Gernal Control Packet Enable. 1 = Enable, 0 = Disable0: disable 1: enable |
385.2 InfoFrame CTRL3 ( InfoFrame CTRL3 0xa2 )
Address: 0x9C00C088
Reset: 0x1010
| Field Name | Bit | Access | Description |
| spdinfo pkt rpt spa | 15:12 | RW | every "pkt rpt spa" VSYNC to transmit SPD InfoFrame packet. |
| Reserved | 11 | RUW | Reserved |
| spdinfo pkt tx | 10 | RW | Transmit SPD InfoFrame packet immediately. pkt rpt = 0 |
| spdinfo pkt rpt | 9 | RW | Transmit SPD InfoFrame packet repeatly. 0: Once 1 = : repeated.0 = Once |
| spdinfo pkt en | 8 | RUW | SPD InfoFrame packet Enable. 0: disable 1 = Enable, 0 = Disable: enable |
| vsinfo pkt rpt spa | 7:4 | RW | Please don't modify this ctrl. (Reserved) |
| Reserved | 3 | RUW | Reserved |
| vsinfo pkt tx | 2 | RW | Transmit VS packet immediately. pkt rpt = 0 |
| vsinfo pkt rpt | 1 | RW | Transmit VS packet repeatly. 0: Once 1 = : repeated.0 = Once |
| vsinfo pkt en | 0 | RUW | Vendor Specific Packet Enable. 0: disable 1 = Enable, 0 = Disable: enable |
385.3 InfoFrame CTRL4 ( InfoFrame CTRL4 0xa3 )
Address: 0x9C00C08C
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| Field Name | Bit | Access | Description |
| isrc2 pkt rpt spa | 15:12 | RW | every "pkt rpt spa" VSYNC to transmit ISRC2 packet. |
| Reserved | 11 | RUW | Reserved |
| isrc2 pkt tx | 10 | RW | Transmit ISRC2 packet immediately. pkt rpt = 0 |
| isrc2 pkt rpt | 9 | RW | Transmit ISRC2 packet repeatly. 0: Once 1 = : repeated. 0 = Once |
| isrc2 pkt en | 8 | RW | ISRC2 packet enable. 1 = Enable, 0 = Disable0: disable 1: enable |
| isrc1 pkt rpt spa | 7:4 | RW | Please don't modify this ctrl. (Reserved) |
| Reserved | 3 | RUW | Reserved |
| isrc1 pkt tx | 2 | RW | Transmit ISRC1 packet immediately. pkt rpt = 0 |
| isrc1 pkt rpt | 1 | RW | Transmit ISRC1 packet repeatly. 0: Once 1 = : repeated.0 = Once |
| isrc1 pkt en | 0 | RUW | ISRC1 packet enable. 1 = Enable, 0 = Disable0: disable 1: enable |
385.4 InfoFrame CTRL5 ( InfoFrame CTRL5 0xa4 )
Address: 0x9C00C090
Reset: 0x10
| Field Name | Bit | Access | Description |
| Reserved | 15:12 | RW | Reserved |
| gm pkt rpt cnt | 11:4 | RW | Trasmit "pkt rpt cnt" times within a Vsync |
| gm pkt tx | 3 | RUW | Transmit GM packet immediately. pkt rpt = 0 |
| Reserved | 2 | RW | Reserved |
| gm pkt rpt | 1 | RW | Transmit GM packet repeatly. 1 = repeated. 0 = : Once 1: repeated |
| gm pkt en | 0 | RUW | Gamut Metadata packet enable. 1 = Enable, 0 = Disable0: disable 1: enable |
385.5 InfoFrame CTRL6 ( InfoFrame CTRL6 0xa5 )
Address: 0x9C00C094
Reset: 0x1010
Field Name | Bit | Access | Description |
| uni pkt rpt spa | 15:12 | RW | every "pkt rpt spa" VSYNC to transmit Universal packet. |
| Reserved | 11 | RUW | Reserved |
| uni pkt tx | 10 | RW | Transmit Universal packet immediately. pkt rpt = 0 |
| uni pkt rpt | 9 | RW | Transmit Universal packet repeatly. 0: Once 1 = : repeated.0 = Once |
| uni pkt en | 8 | RUWUniversal | packet Enable. 1 = Enable, 0 = Disable0: disable 1: enable |
| mpeginfo pkt rpt spa | 7:4 | RW | every "pkt rpt spa" VSYNC to transmit MS InfoFrame packet |
| Reserved | 3 | RUW | Reserved |
| mpeginfo pkt tx | 2 | RW | Transmit MS InfoFrame packet immediately. pkt rpt = 0 |
| mpeginfo pkt rpt | 1 | RW | Transmit MS InfoFrame packet repeatly. 0: Once 1 = : repeated.0 = Once |
mpeginfo pkt en | 0 | RUW | Mpeg Source InfoFrame Packet Enable. 0: disable 1 = Enable, 0 = Disable: enable |
385.6 AVI InfoFrame01 ( AVI InfoFrame01 -- 0xa6 )
Address: 0x9C00C098
Reset: 0x0
...
387.3 Gamut Metadata Packet Header ( Gamut Metadata Packet Header --
0xe3 )
Address: 0x9C00C18C
Reset: 0x0
...
387.4 Gamut Metatata Packet PB01( Gamut Metatata Packet PB01 --
0xe4 )
Address: 0x9C00C190
Reset: 0x0
...
387.5 Gamut Metatata Packet PB23( Gamut Metatata Packet PB23 --
0xe5 )
Address: 0x9C00C194
Reset: 0x0
...
387.6 Gamut Metatata Packet PB45( Gamut Metatata Packet PB45 --
0xe6 )
Address: 0x9C00C198
Reset: 0x0
...
387.7 Gamut Metatata Packet PB67( Gamut Metatata Packet PB67 --
0xe7 )
Address: 0x9C00C19C
Reset: 0x0
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387.8 Gamut Metatata Packet PB89( Gamut Metatata Packet PB89 --
0xe8 )
Address: 0x9C00C1A0
Reset: 0x0
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387.9 Gamut Metatata Packet PB1011 ( Gamut Metatata Packet PB1011 --
0xe9 )
Address: 0x9C00C1A4
Reset: 0x0
...
387.18 MPEG Source InfoFrame PB01 ( MPEG Source InfoFrame PB01 --
0xf2 )
Address: 0x9C00C1C8
Reset:0x0
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| Field Name | Bit | Access | Description |
| MPEGInfo PB1 | 15:8 | RW | MPEG Source InfoFrame Packet Body Byte 1 |
| MPEGInfo PB0 | 7:0 | RW | MPEG Source InfoFrame Packet Body Byte 0, see CEA- 861D 6.7 |
387.19 MPEG Source InfoFrame PB23 ( MPEG Source InfoFrame PB23 --
0xf3 )
Address: 0x9C00C1CC
Reset: 0x0
...
387.20 MPEG Source InfoFrame PB45 ( MPEG Source InfoFrame PB45 --
0xf4 )
Address: 0x9C00C1D0
Reset: 0x0
...
387.21 MPEG Source InfoFrame PB67 ( MPEG Source InfoFrame PB67 --
0xf5 )
Address: 0x9C00C1D4
Reset: 0x0
...
387.22 MPEG Source InfoFrame PB89 ( MPEG Source InfoFrame PB89 --
0xf6 )
Address: 0x9C00C1D8
Reset: 0x0
...
387.23 MPEG Source InfoFrame PB10 ( MPEG Source InfoFrame PB10 --
0xf7 )
Address: 0x9C00C1DC
Reset: 0x0
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| Field Name | Bit | Access | Description |
| tmds ectr | 15:12 | RW | Pre-emphasis strength control. |
| tmds emp | 11 | RW | Pre-emphasis enable, 1 = Enable, 0 = Disable0: disable 1: enable |
| tmds clkdet en | 10 | RW | clock detector enable. 1 = Enable, 0 = Disable0: disable 1: enable |
| tmds fckdv | 9:8 | RW | Free run clock freq. Selection. 0= : 27MHz 1= : 54MHz 2= : 108MHz 3= : 216MHz |
| tmds ckinv | 7:4 | RW | Output clock inversion option ckinv[3] = 1 invert BCK20 ckinv[2] = 1 invert BCK10 ckinv[1] = 1 invert PCKO |
| Reserved | 3:2 | RW | Reserved |
| tmds sel20 | 1 | RW | TX MUX data mode selection. (Only for RD use) 0 = : 10bits data mode, data from ODD 1 = : 20bits data mode, data from EVN & ODD (This control should operated with "tmds dbus sel") |
| tmds inv ck | 0 | RW | TX MUX sample clock inversion |
...
| Field Name | Bit | Access | Description |
| tmds icp mod | 15:12 | RW | ICP MOD[3:2] CPP current control 0= : 1x 1= : 1.25x 2= : 1.5x 3= : 2x ICP MOD[1:0] CPI current control 0= : 1x 1= : 1.25x 2= : 1.5x 3= : 2x |
| tmds pd emp | 11 | RW | Turn off pre-emphasis sterilizer and driver 1: turn off |
| tmds pd d | 10:8 | RW | Power Down Data Channel. pd d[1] = 1, power down data chnl 1 pd d[2] = 1, power down data chnl 2 |
| tmds cpst | 7:4 | RW | PLL Charge Pump Current Trimming. Check the TMDSTX datasheet |
| Reserved | 3:2 | RW | Reserved |
| tmds icp sel | 1 | RW | Charge pump bias current from 0: IBIAS 1= : VCO0= IBIAS |
| tmds fbst | 0 | RW | PLL freq. Tracking boost. |
...
| Field Name | Bit | Access | Description |
| Reserved | 15:5 | RW | Reserved |
| tmds term en | 4:2 | RW | Driver termination enable bit. Check the TMDSTX datasheet. |
| tmds sel bgr | 1 | RW | Reference voltage selection bit 1= select BDGAP for bias 0= : select 2*VDD/3 for bias 1: select BDGAP for bias |
| tst pclk en | 0 | RW | Pixel clock source test enable 0: Use default pixel clock source, eq. PLLTV 1: Use test pixel clock source. |
...
387.31 RESERVED 071F ( RESERVED 071F -- 0xff )
Address: 0x9C00C1FC
Reset: 0x0
| Field Name | Bit | Access | Description |
| Reserved | 15:0 | RW | Reserved |
...