20. HDMI TX

20.1 Introduction

The HDMI TX module is stand for "High Definition Multimedia Interface" to transmit high quality video and audio in a single cable. This HDMI TX IP is composed of video, audio and HDCP cipher engine and intends to be integrated to a SoC to deliver high quality video and audio over a single cable. SP7021 totally supports HDMI1.4 specification, the main features list as below.
About Video

• Video Timing Support List: From 480I to 720P@60fps.

• Color Depth Support List: Support 24/30/36/48 bits and dithering function (16/12/10bits -> 8bits).

• Color Encoding Support List: RGB/YCbCr444/YCbCr422.

• Color Space Support List: AdobeRGB/AdobeYCC601/sYCC601.

• Pixel Repetition Support List: x2/x4.

• Support xvYCC with Gamun Metadata.

• RGB/AdobeRGB ↔ YCbCr (ITU 601/709/AdobeYCC601/sYCC601) conversion support and YCbCr 4:2:2 ↔ YCbCr 4:4:4 support.

About Audio

• Support max. 192kHz sample rate and max. 8 channels for LPCM.

• Support HBR (High Bit Rate) audio, such as DTS-HD Master Audio.

• Support SPDIF*1 and I2S*4 input.

About HDCP

• HDCP 1.4 compatible.

The HDMI TX control registers locate at RGST Table Group 380~387 which memory map address are 0x9C00BE00~0x9C00C1FF.

20.2 Function Diagram

A generalized function diagram of HDMI is shown in Figure 20-1.

Figure 20-1 Generic HDMI Functional Blocks
Each blocks description are as below:

• HDMI Transmitter/Receiver: High Definition Multimedia Interface Transmitter/Receiver

• TMDS: Transition Minimized Differential Signal

• EDID: Extended Display Identification Data

• CEC: Consumer Electronics Control

• HPD: Hot Plug Detect

A HDMI TX function diagram shows in Figure 20-2.

Figure 20-2 HDMI TX Functional Blocks
There are 8 digital sub-blocks in the HDMI TX module of SP7021.

• Video Capture & Processing: Used to capture video data and process video conversion, such as color space conversion.

• Audio Capture & Processing: Used to capture audio data and process audio packetization.

• HDCP: Used to process HDCP authentication between source and sink.

• HDMI packetization: Used to generate TMDS timing protocol and transmit HDMI packets.

• General Control: This block will generate interrupts and resets; the clocks generator also resides here.

• DDC BUS: The hardware DDC (I2C) master to deal with the DDC channel transaction between source and sink.

• CEC: The hardware CEC processor can be a CEC channel transceiver.

• Register File: The register file is to be an interface between host and this module to control HDMI TX.

20.3 Video Path

This HDMI TX module incorporates various video processing modules to perform video conversion such as color space and range as required, and packs into 3 TMDS channels with 8-bits bus each. The detail blocks are drawn as figure 20-3.

Figure 20-3 Video Path
Three channel YCbCr 4:4:4 <-> two channel YCbCr4:2:2 converters dealing with at most 16-bits video data per channel and a universal color space converter are implemented. For universal CSC composed of one 3x3 matrix, standard ITU-R BT601 and ITU-R BT709 with F(full)/L(limit), F/F, L/F, L/L ranges conversion are supported, and coefficients are configurable according to parameters input as well.
This video processing also has dithering engine to convert 16bits/per channel to 12/10/8bits/per channel. The dithering process is a noise diffusion process for high-intensity-resolution images, which is used to reduce false contouring when the intensity-resolution is decreased.
The video capture receives video data from MPEG side. Because of specific application, this video capture only supports RGB/YCbCr444/YCbCr422 parallel bus input.
For debug purpose, there is an internal video pattern generator in video capture, which provides two patterns, one is gray levels for RGB; the other is color bar for YCbCr.

20.4 Audio Path

This IP supports 2 types of digital audio input channel. One is I2S, the other is SPDIF. I2S can convey L-PCM and HBR (compressed and bit rate > 6.144Mbps, like DTS-HD Master Audio, Dolby MAT), while SPDIF can convey L-PCM and compressed (IEC61937) digital audio.
Digital audio is captured by I2S or SPDIF , then passed them to AUDIO FIFO and packaged into Audio Sample Packet as described in HDMI specification.
Another auxiliary module is ACR module for "Audio Clock Regeneration". This module calculates the "Cycle Time Stamp (CTS)" according to input N value, and packages them into "ACR" packet
.

Figure 20-4 Audio Path

20.5 HDCP

Figure 20-5 shows the HDCP function block.

Figure 20-5 HDCP Block
HDMI incorporates HDCP as content protection mechanism during transmitting copyright video and audio data. The SP7021 HDMI TX module embedded a HDCP engine to deal with this task.
The HDCP engine will generate security keys and uses them to encrypt the content. Before transmitting encrypted data, HDMI TX needs to do HDCP authentication with HDMI RX by exchanging HDCP public keys with each other. The detail process can be referred in HDCP specification 1.4.
The HDCP keys should be stored in non-violated memory in a safe place. The SP7021 HDMI TX module incorporates a predefined OTP interface protocol to access HDCP key. By this interface, HDMI TX can get the HDCP key from OTP then does HDCP encryption flow.

20.6 DDC Bus

The DDC bus exchange configuration and status between Source and Sink through I2C. The Sink's configuration and capabilities description is stored in the Extended Display Identification Data (EDID) ROM. The Source shall use I2C commands to read information from a Sink's EDID with a slave address.

20.7 Hot Plug Detect (HPD)

An HDMI Sink shall not assert high voltage level on its Hot Plug Detect pin when the EDID is not available for reading. The Hot Plug Detect pin may be asserted only when the +5V Power line from the Source is detected.
A Source may use a high voltage level Hot Plug Detect signal to initiate the reading of EDID data. A Source shall assume that any voltage within the range specified for High voltage level indicates that a Sink is connected and that EDID is readable.
An HDMI Sink shall indicate any change to the contents of the EDID by driving a low voltage level pulse at (least 100 msec) on the Hot Plug Detect pin.

20.8 Digital Visual Interface (DVI)

SP7021 can also support DVI 1.0 specification. The Group 380.8 SYSTEM CTRL1 register bit0 can select the supported mode. Set bit0=0 for DVI mode, set bit0=1 for HDMI mode.

20.9 System State Control

The firmware will control in the 4 states, they are INIT, HPD, RSEN and HDCP state. The operation flow is shown in figure 20-6. Each state operation describe in table 20-1.

Table 20-1 System State Description

Figure 20-6 HDMI TX main flow state control

20.10 HDMI Interrupts

There are many interrupt events can trigger HDMI TX interrupt. Read Group 383.4 INTR0_STS/383.5 INTR1_STS/383.6 INTR2_STS registers can get the interrupt status. Set corresponding bit to 1 in Group 383.1 INTR0_UNMASK/383.2 INTR1_UNMASK/383.3 INTR2_UNMASK registers can enable the interrupt. Table 20-2 list each interrupt event.

Table 20-1 HDMI TX Interrupt Event

20.11 Registers Map

20.11.1 Registers Memory Map