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- PIO_DONE_INTR: When PIO mode transfer finished, spi_intr_sts[2] will be high. Software write 1 to clean this bit.
- DMA_DONE_INTR: spi_intr_sts[1] indicate the current dma operation is done. Software can write 1 to clear this bit
- BUF_DATA_ENOU_INTR: spi_intr_sts[0] indicate the number of data received from flash has reached the setting amount. Software can write 1 to clear this bit. The amount is set in spi_cfg0[21] which is bit 21 of Group 22.6 register. Set spi_cfg0[21]=1, the buffer size is 32byte. Set spi_cfg0[21]=0, the buffer size is 64byte.
16.5 Registers Map
16.5.1 Registers Memory Map
Address | Group No. | Register Name | Register Description |
---|---|---|---|
0x9C000B00 | G22.0 | Spi_Ctrl | SPI control Register |
0x9C000B04 | G22.1 | Spi_timing | SPI timing Register |
0x9C000B08 | G22.2 | Spi_page_addr | SPI Page Address Register |
0x9C000B0C | G22.3 | Spi_data | SPI Data Register |
0x9C000B10 | G22.4 | Spi_status | SPI Status Register |
0x9C000B14 | G22.5 | Spi_auto_cfg | SPI Auto Mode Configuration Register |
0x9C000B18 | G22.6 | Spi_cfg0 | SPI Configuration0 Register |
0x9C000B1C | G22.7 | Spi_cfg1 | SPI Configuration1 Register |
0x9C000B20 | G22.8 | Spi_cfg2 | SPI Configuration2 Register |
0x9C000B24 | G22.9 | Spi_data_64 | SPI Data Buffer Register |
0x9C000B28 | G22.10 | Spi_buf_addr | SPI Buffer Address Register |
0x9C000B2C | G22.11 | Spi_status_2 | SPI Status2 Register |
0x9C000B30 | G22.12 | Spi_err_status | SPI Error Status |
0x9C000B34 | G22.13 | Mem_data_addr | Memory Data Address |
0x9C000B38 | G22.14 | Mem_parity_addr | Memory Parity Address For SPI_NOR is reserved. |
0x9C000B3C | G22.15 | Spi_col_addr | SPI Column Page Address For SPI_NOR is reserved. |
0x9C000B40 | G22.16 | Spi_bch | SPI BCH Configuration Register For SPI_NOR is reserved. |
0x9C000B44 | G22.17 | Spi_intr_msk | SPI Interrupt Mask Register |
0x9C000B48 | G22.18 | Spi_intr_sts | SPI Interrupt Status Register |
0x9C000B4C | G22.19 | Spi_page_size | SPI Device Page Size |
Address | Group No. | Register Name | Register Description |
---|---|---|---|
0x9C000B80 | G23.0 | Spi_protect_cfg | Protect Configuration Register |
0x9C000B84 | G23.1 | Spi_region0_start_addr | Protection Region0 Start Address |
0x9C000B88 | G23.2 | Spi_region0_size | Size of Protection Region0 |
0x9C000B8C | G23.3 | Spi_region1_start_addr | Protect Region1 Start Address |
0x9C000B90 | G23.4 | Spi_region1_size | Size of Protection Region1 |
0x9C000B94 | G23.5 | Spi_region2_start_addr | Protect Region2 Start Address |
0x9C000B98 | G23.6 | Spi_region2_size | Size of Protection Region2 |
0x9C000B9C | G23.7 | Spi_scramble1 | SPI Scramble1 Register |
0x9C000BA0 | G23.8 | Spi_scramble2 | SPI Scramble2 Register |
0x9C000BA4 | G23.9 | Spi_scramble3 | SPI Scramble3 Register |
16.5.2 Registers Description
RGST Table Group 22SPI Controller Registers
22.0 SPI Control Register (spi ctrl)
Address: 0x9C000B00
Reset: 0x0117 0003
...
Field Name | Bit | Access | Description |
Reserved | 31:23 | RO | Default to be zero |
DMA SUB ST | 22:20 | RO | DMA sub state 0x0: AXI IDLE 0x1: AXI WR INFO 0x2: AXI WR DATA 0x3: AXI RD INFO 0x4: AXI RD DATA |
DMA MAIN ST | 19:18 | RO | DMA main state 0x0: DMA IDLE 0x1: DMA DATA 0x2: DMA PARITY |
BCH ST | 17:16 | RO | DMA main state 0x0: IDLE 0x1: ENCODE 0x2: DECODE |
SPI SRAM ST | 15:13 | RO | Status of SRAM [0]: SRAM conflict, both OCP and customzied read/write at the same time [1]: SRAM empty [2]: SRAM full |
SPI CON ST | 12:8 | RU | Status of block SPI CON |
SPI OUT ST | 7:4 | RU | Status of block SPI OUT |
SPI AXIS ST | 3:0 | RO | Status of block SPI AXIS |
22.12 SPI Controller Error Status Register (spi err status)
Address: 0x9C000B30
Reset: 0x0000
Field NameBitAccessDescription
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Field Name | Bit | Access | Description |
Reserved | 15:3 | RO | Default to be zero |
DATA POR | 2:0 | RW | Data scramble position rotation |
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