Page Comparison

0x30

IOP_IM_Base[7:0]

RO

0x0

IOP IM base address; always set to 0x0 for UVM test

0x31

IOP_IM_Base[15:8]

RO

0x0

IOP IM base address; always set to 0x0 for UVM test

0x32

IOP_IM_Base[23:16]

RO

0x0

IOP IM base address

0x33

IOP_IM_Base[31:24]

RO

0x0

IOP IM base address

0x34

reserved

0x35

IOP_DM_Base[23:16]

RW

0x0

IOP DM base address; XDM bank address when D-cache is enabled

0x36

IOP_DM_Base[31:24]

RW

0x0

IOP DM base address; XDM bank address when D-cache is enabled

0x37

reserved

0x38[5:0]

IOP_INT_MASK_B

RW

0x0

refer to Interrupts_to_IOP

0x39[5:0]

IOP_INT_FLAG

R/W1C

0x0

refer to Interrupts_to_IOP

0x3A[0]

IOP_INT0

RW

0x0

refer to Interrupts_from_IOP

0x3A[1]

IOP_INT1

RW

0x0

refer to Interrupts_from_IOP

0x3B[6:0]

XDM Cache_Flush_LINE_NO

RW

0x7F

number of cache lines(32B) to be checked and then be flushed if dirty 0x0: none0x1: 2 lines are checked 0x7F(default): all lines of 4KB are checkedthis number has to be set before starting flush and not be modified until the end of flush

0x3C[0]

XDM Cache Disable

RW

0x0

0: cache is enabled (default) 1: cache is disabled

0x3C[1]

XDM Cache Flush

RW

0x0

0: normal mode write 1: flush read 1: flushing in progress (this bit is functionless when XDM cache is disabled)

0x3C[2]

XDM Cache_DIS_CLR_V_EN

RW

0x1

0: valid bits are not cleared 1: all valid bits are cleared when cache is disabled (0x3C[0]=1) (default)

0x3C[3]

XDM Cache_DIS_CLR_D_EN

RW

0x1

0: dirty bits are not cleared 1: all dirty bits are cleared when cache is disabled (0x3C[0]=1) (default)

0x3C[4]

XDM Cache_Flush_CLR_V_EN

RW

0x1

0: valid bits are not cleared 1: all valid bits are cleared when cache is flushed (0x3C[1]=1) (default)

0x3C[5]

XDM Cache_Flush_CLR_D_EN

RW

0x1

0: dirty bits are not cleared 1: all dirty bits are cleared when cache is flushed (0x3C[1]=1) (default)

0x3C[6]

XDM Cache_all_V_set

RW

0x0

0: normal function (default) 1: all valid bits are set
when it is set to "1", it will be cleared to "0" by HW automatically after 1T

0x3C[7]

XDM Cache_all_D_set

RW

0x0

0: normal function (default) 1: all dirty bits are set
when it is set to "1", it will be cleared to "0" by HW automatically after 1T

0x3D[0]

IR_O

RO

0x0

this bit equals IR_IN ^ IR_IN_polarity

0x3D[1]

IR_IN_polarity

RW

0x0

0: IR_O = IR_IN 1: IR_O = polarity-inverted IR_IN

0x3D[2]

PMC_IR_LATCH

RO

0x0

IR_LATCH flag from PMC 1: IR wakeup

0x3D[3]

PMC_SYS_RTC_LATCH

RO

0x0

SYS_RTC_LATCH flag from PMC 1: RTC wakeup

0x3D[4]

reserved

0x3D[5]

reserved

0x3D[6]

CLR_PMC_IR_LATCH

W1C

0x0

Clear PMC_IR_LATCH in PMC

0x3D[7]

CLR_PMC_SYS_RTC_LATCH

W1C

0x0

Clear PMC_SYS_RTC_LATCH in PMC

0x3E

TIMER1[7:0]

RW

0xFF

timer1 low byte

0x3F

TIMER1[15:8]

RW

0xFF

timer1 high byte

0x40

TIMER2[7:0]

RW

0xFF

timer2 low byte

0x41

TIMER2[15:8]

RW

0xFF

timer2 high byte

0x42[0]

TIMER2_EN

RW

0x0

1: enable 0: disable

0x42[1]

TIMER1_EN

RW

0x0

1: enable 0: disable

0x43

reserved

0x44[1]

DIS_SYS_RST_IOP

RW

0x0

disable system reset IOP; CLKISO_IOP_RST_B is blocked and can't reset IOP

0x45

CPU_RESUME_PCL[7:0]

RW

0x0

address for CPU to resume

0x46

CPU_RESUME_PCL[15:8]

RW

0x0

address for CPU to resume

0x47

CPU_RESUME_PCH[7:0]

RW

0x0

address for CPU to resume

0x48

CPU_RESUME_PCH[15:8]

RW

0x0

address for CPU to resume

0x49

IOP_INT_MASK1_B

RW

0x0

Mask for INT_FLAG1

0x4A

IOP_INT_FLAG1

RO

0x0

bit 0 : SPI_IOP_INT1_0bit 1 : SPI_IOP_INT1_1bit 2 : SPI_IOP_INT1_2bit 3 : SPI_IOP_INT1_3bit 4 : SPI_IOP_INT2_0bit 5 : SPI_IOP_INT2_1bit 6 : SPI_IOP_INT2_2bit 7 : SPI_IOP_INT2_3

0x4B

IOP_INT_MASK2_B

RW

0x0

Mask for INT_FLAG2

0x4C

IOP_INT_FLAG2

RO

0x0

• these interrupt sources are not used, all are tied to "0"

0x4D

IOP_INT_MASK3_B

RW

0x0

Mask for INT_FLAG3

0x4E[2:0]

IOP_INT_FLAG3[2:0]

RO

0x0

• these interrupt sources are not used, all are tied to "0"

0x4E[7:3]

IOP_INT_FLAG3[7:3]

RO

0x0

bit 3 : UART_IOP_INT(UA3_INT from UART3) bit 4 : SPI_IOP_INT0_0 bit 5 : SPI_IOP_INT0_1 bit 6 : SPI_IOP_INT0_2 bit 7 : SPI_IOP_INT0_3

0x4F

reserved

0x50 ~ 0x67

Mailbox 0 ~ 11

RW

0x0000

0x50: Mailbox0[7:0]; 0x51: Mailbox0[15:8] 0x52: Mailbox1[7:0]; 0x53: Mailbox1[15:8] ... 0x64: Mailbox10[7:0]; 0x65: Mailbox10[15:8] 0x66: Mailbox11[7:0]; 0x67: Mailbox11[15:8]

0x68 - 0x6F (RTC Timer)

Address

Signal Name

Attribute

Reset Value

Description

0x68

SYS_RTC_TIMER[31:24]

RO

0x0

System RTC timer bits 31~24

0x69

SYS_RTC_TIMER[23:16]

RO

0x0

System RTC timer bits 23~16

0x6A

SYS_RTC_TIMER[15:8]

RO

0x0

System RTC timer bits 15~8

0x6B

SYS_RTC_TIMER[7:0]

RO

0x0

System RTC timer bits 7~0; the values(32bits) of system RTC timer (inputs of IOP) are loaded into (0x68 ~ 0x6B) only when any one address of these four registers (0x68 ~ 0x6B) is written by IOP.

0x6C

SYS_RTC_ONTIME_SET[31:24]

RW

0x0

System RTC alarm setting bit 31~24

0x6D

SYS_RTC_ONTIME_SET[23:16]

RW

0x0

System RTC alarm setting bit 23~16

0x6E

SYS_RTC_ONTIME_SET[15:8]

RW

0x0

System RTC alarm setting bit 15~8

0x6F

SYS_RTC_ONTIME_SET[7:0]

RW

0x0

System RTC alarm setting bit 7~0;

• all 32 bits of SYS_RTC_ONTIME_SET are written into RTC upon the writing of this register.
• the SYS_RTC_ONTIME 32b register resides in the RTC module, which can also be set by CPU. Note that IDM initialization process by SW (which may clear all IDM) may accidentally change the value of SYS_RTC_ONTIME formerly set by CPU.
• IDM is initialized by HW, SW initialization is not necessary.

0x70

XDMDATA_OUT[31:24]

RW

0x0

XDM is originally an 8-bit data I/F, to cooperate with a 32-bit system, IOP writes out 32b data when D-cache is disabled When IOP writes XDM, the 32b data stored in these 4 registers (0x73 ~ 0x70) is written out to the 4 bytes with address[15:2] assigned by the instruction, the 8b data assigned by the instruction is dismissed.

0x71

XDMDATA_OUT[23:16]

RW

0x0

0x72

XDMDATA_OUT[15:8]

RW

0x0

0x73

XDMDATA_OUT[7:0]

RW

0x0

0x74

XDMDATA_IN[31:24]

RO

0x0

XDM is originally an 8-bit data I/F, to cooperate with a 32-bit system, IOP reads in 32b data when D-cache is disabled When IOP reads XDM, besides the original byte designated by the address of the command is read, all the 4 bytes nearby with the same address[15:2] are also recorded in these 4 IDM registers (0x77 ~ 0x74) at the same time.

0x75

XDMDATA_IN[23:16]

RO

0x0

0x76

XDMDATA_IN[15:8]

RO

0x0

0x77

XDMDATA_IN[7:0]

RO

0x0

0x78

XDM_Bank_ADR[31:24]

RW

0x0

XDM bank address when D-cache is disabled

0x79

XDM_Bank_ADR[23:16]

RW

0x0

XDM bank address when D-cache is disabled

0x7A~0x7F

reserved