This manual serves as a comprehensive guide for utilizing the C3V-W (LPDDR4) Core Board, a cutting-edge hardware solution tailored for diverse applications. The C3V-W (LPDDR4) Core Board comprises a integrates a robust set of components, including the C3V-W chip, an 8 GiB eMMC deviceflash, a 4 GiB LPDDR4 SDRAM, powers regulators many switching-mode and linear power regulators, and two 120-pin fine0.4mm-pitch connectors which connect necessary to essential for interfacing with an IO board. This board is designed by suing the state of the art 6 Crafted with precision using state-of-the-art 6-layer, HDI PCB which guarantees LPDDR4 to operate technology, this board ensures optimal performance, with LPDDR4 capable of operating at speeds up to 3200 MT/s and eMMC to operates reaching speeds of up to HS200. Customers can have the flexibility to design their own IO boards for specified application. The IO boards can simply use 4 layer PCB to reduce total cost. Refer to figure below for IO boards tailored to specific applications, leveraging cost-effective 4-layer PCBs. Refer to functional block diagram of C3V-W (LPDDR4) Core Board .below:
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Contents
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Pictures of C3V-W (LPDDR4) Core Board
Refer to pictures of The C3V-W (LPDDR4) Core Board : top-view picture, bottom-view picture and top view with heat-sink picture. The size is 40 mm x 55 mm.
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is compact, measuring 40mm x 55mm, ensuring efficient integration into various systems. Refer to pictures of C3V-W (LPDDR4) Core Board
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below: Top-view, Bottom-view
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Picture of Top view of C3V-W (LPDDR4) Core Board with Heat-sink
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and Top-view with heat-sink:
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IO Connectors
All IO pins, except for the eMMC device, are connected to conveniently accessible through the 120-pin fine0.4mm-pitch connectorconnectors. Refer Please refer to the pin-assignment of the two connectors:diagrams for Connector CN1 and Connector CN2 for detailed pinout information.
Pin-assignment of Connector CN1
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The C3V-W (LPDDR4) Core Board is powered by a +5V power . Sourcing from +5V power, Core Board has built in DC2DC and linear power regulaotrs to generate 12 power supplies. They are source. To guarantee stable power distribution and facilitate optimal performance and energy efficiency, the board incorporates advanced internal power regulation circuitry.
Integrated with both DC2DC and linear power regulators, the Core Board efficiently generates 12 distinct power supplies. These supplies are intelligently divided into 5 power domains, each catering to specific functional requirements of the board.
AO Power Domain:
AO means Always ON. When power of The Always-On (AO) Power Domain ensures CM4 remain operational even when other power domains are turned off, it still remain ON to keep minimum system operating in minimum power. Image of Linux kernel is kept in DRAM. It can restore to normal operation in a few second when requested by users.deactivated. Key power supplies include:
AO_0V8: 0.8V
AO_1V8: 1.8V
AO_3V3: 3.3V
DRAM_VDDQ
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: 1.1V
When other power domains are turned off, the AO Power Domain persists, ensuring that CM4 system functionalities are sustained. During this state, the image of the Linux kernel is suspend to (stored in) DRAM, allowing for rapid restoration to normal operation within a few seconds upon user request.
Video Codec Power Domain:
Video power domain is for This domain powers the video codec . It and can be turned off when selectively disabled to conserve energy when the video codec is not being used to save power consumptionin use.
VDD_VV: 0.8V
NPU Power Domain:
NPU power domain is for NPU. It can be turned off when NPU is not being used to save power consumption.The NPU Power Domain powers the Neural Processing Unit (NPU) and can be toggled off when not required, minimizing power consumption..
VDD_NPU: 0.85V
CPU Power Domain:
The CPU power domain Power Domain is responsible for CPU. It can be turned off when CPU is not being used to save power consumption. Besides, C3V-W supports DVFS. Voltage of CPU can be adjusted according to frequency scaling.supplying power to the CPU and is equipped with features to optimize power usage. Notably, it supports Dynamic Voltage and Frequency Scaling (DVFS), allowing for dynamic adjustments in voltage and frequency based on workload demands, thereby enhancing power efficiency.
When the CPU is not actively engaged, the CPU Power Domain can be deactivated to conserve power consumption, contributing to overall energy savings. Key voltage specifications for the CPU Power Domain:
VDD_CA55: Adjustable within the range of 0.7V
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to 1.0V
Voltage is controlled in I2C interfacecontrol within this domain is facilitated through the I2C interface, providing a convenient means to manage and regulate power settings according to system requirements.
Main Power domain:
The Main Power Domain serves as the backbone of the system, encompassing various components and peripherals essential for system operation. It provides crucial voltages necessary for the operation of peripherals, ensuring seamless functionality across the system.
SYS_0V8 = DPHY_0V8 = MIPI_0V8: 0.8V
SYS_1V8: 1.8V
SYS_3V: 3.0V
SYS_3V3: 3.3V
SYS_5V:
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5.0V