This manual serves as a guide for utilizing the C3V-W (LPDDR4) Core Board. The C3V-W (LPDDR4) Core Board comprises a C3V-W chip, an 8 GiB eMMC device, 4 GiB LPDDR4 SDRAM, powers regulators and two 120-pin fine-pitch connectors which connect necessary to IO board. This board is designed by suing the state of the art 6 layer, HDI PCB which guarantees LPDDR4 to operate up to 3200 MT/s and eMMC to operates up to HS200. Customers can design their own IO boards for specified application. The IO boards can simply use 4 layer PCB to reduce total cost. Refer to figure below for functional block diagram of C3V-W (LPDDR4) Core Board.
Contents
Pictures of C3V-W (LPDDR4) Core Board
Refer to pictures of C3V-W Core Board: top-view picture, bottom-view picture and top view with heat-sink picture. The size is 40 mm x 55 mm.
Picture of Top-view of C3V-W (LPDDR4) Core Board
Picture of Bottom-view of C3V-W (LPDDR4) Core Board
Picture of Top view of C3V-W (LPDDR4) Core Board with Heat-sink
GPIO
All IO pins except eMMC device are connected to the 120-pin fine-pitch connector. Refer to pin-assignment of the two connectors:
Pin-assignment of Connector CN1
Pin-assignment of Connector CN2
Powers
The C3V-W (LPDDR4) Core Board is powered by +5V power. Sourcing from +5V power, Core Board has built in DC2DC and linear power regulaotrs to generate 12 power supplies. They are divided into 5 power domains.
AO Power Domain:
AO means Always ON. When power of other power domains are turned off, it still remain ON to keep minimum system operating in minimum power. Image of Linux kernel is kept in DRAM. It can restore to normal operation in a few second when requested by users.
AO_0V8: 0.8V
AO_1V8: 1.8V
AO_3V3: 3.3V
DRAM_VDDQ (1.1V)
Video Power Domain:
Video power domain is for video codec. It can be turned off when video codec is not being used to save power consumption.
VDD_VV: 0.8V
NPU Power Domain:
NPU power domain is for NPU. It can be turned off when NPU is not being used to save power consumption.
VDD_NPU: 0.85V
CPU Power Domain:
CPU power domain is for CPU. It can be turned off when CPU is not being used to save power consumption. Besides, C3V-W supports DVFS. Voltage of CPU can be adjusted according to frequency scaling.
VDD_CA55: 0.7V ~ 1.0V
Voltage is controlled in I2C interface.
Main Power domain:
SYS_0V8 = DPHY_0V8 = MIPI_0V8: 0.8V
SYS_1V8: 1.8V
SYS_3V: 3.0V
SYS_3V3: 3.3V
SYS_5V: 5V