Case download:
fbio_selftest.zip
1 Design Brief
The SP7021 SOC platform LOOPBACK self-test experiment is mainly used to test the reliability of the SOC platform connection. The design of the FBIO Bus Bridge is placed on the FPGA daughter board. The Plus1 chip reads and writes the FBIO Bus Bridge to realize the reliability test of the connection between the Plus1 chip and the FPGA daughter board pin .
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The SP7021 SOC platform self-test experiment only needs to connect the axi_m and axi_s 64bit axim and axis bus interfaces of the FBIO Wrapper Bus Bridge together, and do the corresponding address mapping. That is, the access to the FBIO Bus Bridge start address 0x70000000 is mapped to the access to the DRAM start address 0x00000000 in the Plus1 SP7021 chip ;As shown below:
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This This experiment uses the FPGA daughter board supporting the Plus1 7021 SP7021 practice platform to complete the relevant experiments. The development tool of the FPGA daughter board uses Xilinx's Vivado integrated development environment (version number 2018.3); in order to facilitate the connection of the user's own verification IP to the SOC system Verification, this experiment provides the corresponding design reference basic files, as follows
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