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For a single-end signal with 50Ω 50 Ω impedance on Layer 1, set the trace width to 5 mils and clearance to 10 mils.
For a differential-pair signal with 90Ω 90 Ω differential impedance on Layer 1, set the trace width to 4.5 mils and clearance to 6 mils.
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2.3.1.2 DQ to DQ Mismatch Within a Byte
Skew limit: < 200ps200 pS
Recommended skew: < 20ps20 pS
2.3.1.3 DQ to DQS Skew
Skew limit: DQS ±100ps±100 pS
Recommended skew: DQS ±10ps±10 pS
2.3.1.4 CS, CKE, ODT, CA to CK Skew
Recommended skew: CK ±10ps±10 pS
Skew limit can be relaxed if the timing budget and simulation results indicate that there is adequate margin.
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Skew limit: -0.5 to +5.47 clock cycles
Recommended skew: CK ±60ps±60 pS
2.3.1.6 DQS/DQS# and CK/CK# Intra-pair Skew
Maximum intra-pair skew: 3ps3 pS
2.3.1.7 Trace Impedance
DQ: 50Ω 50 Ω ±10%
DQS (diff.): 100Ω 100 Ω ±10%
DM: 50Ω 50 Ω ±10%
CS, CKE, ODT and CA: 50Ω 50 Ω ±10%
CK (diff.): 100Ω 100 Ω ±10%
2.3.1.8 SI Criteria
The corresponding threshold levels are defined in JEDEC standard. Timing budgets should include both SDRAM contributions and PHY contributions, which are listed below.
Data write (rectangular mask):
Eye height: 140mV140 mV
Setup time: 67.1ps 1 pS (SDRAM contributions* and PHY contributions**)
Hold time: 69.8ps 8 pS (SDRAM contributions* and PHY contributions**)
Data read (diamond mask):
Eye height: 140mV140 mV
Setup time: 73.8ps 8 pS (SDRAM contributions* and PHY contributions**)
Hold time: 76.2ps 2 pS (SDRAM contributions* and PHY contributions**)
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Clock jitter: < 61.2ps 2 pS (SDRAM contributions* and PHY contributions**)
CS, ODT and CA (rectangular mask):
Eye height: 155mV155 mV
Setup time: 159.7ps 7 pS (SDRAM contributions* and PHY contributions**)
Hold time: 159.7ps 7 pS (SDRAM contributions* and PHY contributions**)
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Referring to reference layout of Layer 1 (Top) below, it is imperative to maintain a controlled impedance of 100Ω 100 Ω for the four specified differential pairs, while single-end signals should adhere to a 50Ω 50 Ω impedance standard. The sequence of the four differential pairs, from left to right, is as follows: (DRAM_SDQS1_T_A, DRAM_SDQS1_C_A), (DRAM_CK_C_A, DRAM_CK_T_A), (DRAM_CK_T_B, DRAM_CK_C_B), and (DRAM_SDQS1_T_B, DRAM_SDQS1_C_B).
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Refer to reference layout of Layer 3 (L3_S) below, similarly, the impedance of the two specified differential pairs should be maintained at 100Ω100 Ω, while other single-end signals should adhere to a 50Ω 50 Ω impedance standard. These two differential pairs, arranged from left to right, are: (DRAM_SDQS0_T_A, DRAM_SDQS0_C_A), and (DRAM_SDQS0_C_B, DRAM_SDQS0_T_B).
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Referring to reference layout of Layer 6 (Bottom) below, the prescribed impedance for all single-end signals is 50Ω50 Ω, ensuring consistency and optimal signal integrity throughout the design. Note that bypass capacitors for PHY and SDRAM are all placed at this layer.
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2.3.2.2 DQ to DQ Mismatch
Skew limit: < 200ps200 pS
Recommended skew: < 20ps20 pS
2.3.2.3 DQ to DQS Skew
Skew limit: DQS ±100ps±100 pS
Recommended skew: DQS ±10ps±10 pS
2.3.2.4 CS, CKE, ODT, Command and Address to CK Skew
Skew limit: 0 to 1UI*
Recommended skew: CK ±25ps±25 pS
*Programmable delay can be added to 4-bit groups of AC signals (ACX4-0 ~ ACX4-9).
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Skew limit: -1.0 to +5.97 clock cycles
Recommended skew: CK ±85ps±85 pS
2.3.2.6 DQS/DQS# and CK/CK# Intra-pair Skew
Maximum intra-pair skew: 3ps3 pS
2.3.2.7 Trace Impedance
DQ: 50Ω 50 Ω ±10%
DQS (diff.): 100Ω 100 Ω ±10%
DM: 50Ω 50 Ω ±10%
CS, CKE, ODT, command and address: 50Ω 50 Ω ±10%
CK (diff.): 100Ω 100 Ω ±10%
2.3.2.8 SI Criteria
The corresponding threshold levels are defined in JEDEC standard. Timing budgets should include both SDRAM contributions and PHY contributions, which are listed below.
Data write (rectangular mask):
Eye height: 120mV120 mV
Setup time: 62.7ps 7 pS (SDRAM contributions* and PHY contributions**)
Hold time: 66ps 66 pS (SDRAM contributions* and PHY contributions**)
Data read (diamond mask):
Eye height: 140mV140 mV
Setup time: 77.6ps 6 pS (SDRAM contributions* and PHY contributions**)
Hold time: 81ps 81 pS (SDRAM contributions* and PHY contributions**)
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Clock jitter: < 39.8ps 8 pS (SDRAM contributions* and PHY contributions**)
CS, CKE, ODT, command and address (rectangular mask):
Setup levels:
510mV 510 mV (AC input logic low)
690mV 690 mV (AC input logic high)
Setup time: 176.8ps 8 pS (SDRAM contributions* and PHY contributions**)
Hold levels:
535mV 535 mV (DC input logic low)
665mV 665 mV (DC input logic high)
Hold time: 180.8ps 8 pS (SDRAM contributions* and PHY contributions**)
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2.3.3.2 DQ to DQ Mismatch
Skew limit: < 200ps200 pS
Recommended skew: < 20ps20 pS
2.3.3.3 DQ to DQS Skew
Skew limit: DQS ±100ps±100 pS
Recommended skew: DQS ±10ps±10 pS
2.3.3.4 CS, CKE, ODT, Command and Address to CK Skew
Skew limit: 0 to 1UI*
Recommended skew: CK ±25ps±25 pS
*Programmable delay can be added to 4-bit groups of AC signals (ACX4-0 ~ ACX4-9).
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Skew limit: -1.0 to +5.97 clock cycles
Recommended skew: CK ±85ps±85 pS
2.3.3.6 DQS/DQS# and CK/CK# Intra-pair Skew
Maximum intra-pair skew: 3ps3 pS
2.3.3.7 Trace impedance
DQ: 50Ω 50 Ω ±10%
DQS (diff.): 100Ω 100 Ω ±10%
DM: 50Ω 50 Ω ±10%
CS, CKE, ODT, command and address: 50Ω 50 Ω ±10%
CK (diff.): 100Ω 100 Ω ±10%
2.3.3.8 SI Criteria
The corresponding threshold levels are defined in JEDEC standard. Timing budgets should include both SDRAM contributions and PHY contributions, which are listed below.
Data write (rectangular mask):
Setup levels:
615mV 615 mV (AC input logic low)
885mV 885 mV (AC input logic high)
Setup time: 136.5ps 5 pS (SDRAM contributions* and PHY contributions**)
Hold levels:
650mV 650 mV (DC input logic low)
850mV 850 mV (DC input logic high)
Hold time: 124.3ps 3 pS (SDRAM contributions* and PHY contributions**)
Data read (diamond mask):
Eye height: 140mV140 mV
Setup time: 123.5ps 5 pS (SDRAM contributions* and PHY contributions**)
Hold time: 166.5ps 5 pS (SDRAM contributions* and PHY contributions**)
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Clock jitter: < 43ps 43 pS (SDRAM contributions* and PHY contributions**)
CS, CKE, ODT, command and address (rectangular mask):
Setup levels: 625mV 625 mV (AC input logic low)
875mV 875 mV (AC input logic high)
Setup time: 270.1ps 1 pS (SDRAM contributions* and PHY contributions**)
Hold levels: 650mV 650 mV (DC input logic low)
850mV 850 mV (DC input logic high)
Hold time: 217.2ps 2 pS (SDRAM contributions* and PHY contributions**)
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2.3.4.2 DQ to DQ Mismatch
Skew limit: < 200ps200 pS
Recommended skew: < 20ps20 pS
2.3.4.3 DQ to DQS Skew
Skew limit: DQS ±100ps±100 pS
Recommended skew: DQS ±10ps±10 pS
2.3.4.4 CS, CKE, ODT, Command and Address to CK Skew
Skew limit: 0 to 1UI*
Recommended skew: CK ±25ps±25 pS
*Programmable delay can be added to 4-bit groups of AC signals (ACX4-0 ~ ACX4-9).
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Skew limit: -1.0 to +5.97 clock cycles
Recommended skew: CK ±85ps±85 pS
2.3.4.6 DQS/DQS# and CK/CK# Intra-pair Skew
Maximum intra-pair skew: 3ps3 pS
2.3.4.7 Trace Impedance
DQ: 50Ω 50 Ω ±10%
DQS (diff.): 100Ω 100 Ω ±10%
DM: 50Ω 50 Ω ±10%
CS, CKE, ODT, command and address: 50Ω 50 Ω ±10%
CK (diff.): 100Ω 100 Ω ±10%
2.3.4.8 SI Criteria
The corresponding threshold levels are defined in JEDEC standard. Timing budgets should include both SDRAM contributions and PHY contributions, which are listed below.
Data write (rectangular mask):
Setup levels:
540mV 540 mV (AC input logic low)
810mV 810 mV (AC input logic high)
Setup time: 136.5ps 5 pS (SDRAM contributions* and PHY contributions**)
Hold levels:
575mV 575 mV (DC input logic low)
775mV 775 mV (DC input logic high)
Hold time: 124.3ps 3 pS (SDRAM contributions* and PHY contributions**)
Data read (diamond mask):
Eye height: 140mV140 mV
Setup time: 123.5ps 5 pS (SDRAM contributions* and PHY contributions**)
Hold time: 166.5ps 5 pS (SDRAM contributions* and PHY contributions**)
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Clock jitter: < 43ps 43 pS (SDRAM contributions* and PHY contributions**)
CS, CKE, ODT, command and address (rectangular mask):
Setup levels:
550mV 550 mV (AC input logic low)
800mV 800 mV (AC input logic high)
Setup time: 270.1ps 1 pS (SDRAM contributions* and PHY contributions**)
Hold levels:
575mV 575 mV (DC input logic low)
775mV 775 mV (DC input logic high)
Hold time: 217.2ps 2 pS (SDRAM contributions* and PHY contributions**)
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2.4.1.3 Trace Impedance
D[3:0], CSN, CLK: 50Ω 50 Ω ±10%
2.4.2 SPI-NAND Flash
2.4.2.1 General Rules
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2.4.2.3 Trace Impedance
D[3:0], CSN, CLK: 50Ω 50 Ω ±10%
2.4.3 8-bit NAND Flash
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2.4.3.3 Trace Impedance
Trace Impedance: 50Ω 50 Ω ±10%
2.4.4 eMMC Device
2.4.4.1 General Rules
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CLK, CMD, DQ and DS signals : 50Ω 50 Ω ±10%
2.4.4.4 Reference Layout
Referring to reference layout of Layer 1 (Top) below, all eMMC nets initially originate from SP7350 and traverse Layer 1. It is important to maintain a controlled impedance of 50Ω 50 Ω for all eMMC nets whenever possible.
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2.4.5.2 DP/DM Differential-pair Mismatch
Maximum intra-pair skew: 1ps1 pS (~6mil)
2.4.5.3 Trace Impedance
DP/DM differential-pair: 90Ω 90 Ω ±10%
2.4.5.4 Reference Layout
In the reference layout below, the data differential pair of USB 2.0 is initially routed at Layer 3, and subsequently transition to Layer 6 towards a connector. It is crucial to maintain a controlled differential impedance of 90Ω 90 Ω for this pair.
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2.4.6 USB3.0
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2.4.6.2 TX or RX Differential-pairs Mismatch
Maximum intra-pair skew: 1ps1 pS (~6mil)
2.4.6.3 DP/DM Differential-pair Mismatch
Maximum intra-pair skew: 1ps1 pS (~6mil)
2.4.6.4 Trace Impedance
TX or RX differential-pairs: 90Ω 90 Ω ±10%
DP/DM differential-pair: 90Ω 90 Ω ±10%
2.4.6.5 Power loop inductance
USB3_AVDD08: < 2.4nH4 nH
USB3_DVDD08: < 2.4nH4 nH
USB3_VDD33: < 2.8nH8 nH
2.4.6.6 Reference Layout
In the reference layout below, the six differential pairs of USB 3.0 are initially routed at Layer 1, and subsequently transition to Layer 6 towards a connector. It is crucial to maintain a controlled differential impedance of 90Ω 90 Ω for all pairs. From top to bottom, the differential pairs are: (USB30_TX1_DP_0, USB30_TX1_DM_0), (USB30_RX1_DP_0, USB30_RX1_DM_0), (USB30_TX0_DM_0, USB30_TX0_DP_0), (USB30_RX0_DM_0, USB30_RX0_DP_0), and (USB30_DM, USB30_DP).
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CLK, CMD, D[3:0] signals : 50Ω 50 Ω ±10%
2.4.7.4 Reference Layout of SD Card
In the reference layout below, the six nets of the SD card are initially routed at Layer 1, and subsequently transition to Layer 6 towards a connector. Please maintain a controlled impedance of 50Ω 50 Ω for all SD card signals throughout.
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In the reference layout below, the six nets of the SDIO are initially routed at Layer 1, and subsequently transition to Layer 6 towards a connector. Please maintain a controlled impedance of 50Ω 50 Ω for all SDIO signals throughout.
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2.4.8.2 Data Differential-pairs Mismatch
Maximum intra-pair skew: 1ps1 pS (~6mil)
2.4.8.3 Clock Differential-pair Mismatch
Maximum intra-pair skew: 1ps1 pS (~6mil)
2.4.8.4 Data to Clock Skew
Channel skew limit: clock ±66ps±66 pS
2.4.8.5 Trace Impedance
Data and clock differential-pairs: 100Ω 100 Ω ±10%
2.4.8.6 Reference Layout of MIPI-RX2
In the reference layout below, the nets of the MIPI-RX2 are routed at Layer 1 and Layer 3, and subsequently transition to Layer 6 near the connector. It is crucial to maintain a controlled differential impedance of 100Ω 100 Ω for all pairs. From top to bottom, the differential pairs are: (MIPIRX2_DP2, MIPIRX2_DN2), (MIPIRX2_DN0, MIPIRX2_DP0), and (MIPIRX2_DP3, MIPIRX2_DN3).
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In the reference layout below, the nets of the MIPI-RX3 are routed at Layer 1 and Layer 3, and subsequently transition to Layer 6 near the connector. It is crucial to maintain a controlled differential impedance of 100Ω 100 Ω for all pairs. From top to bottom, the differential pairs are: (MIPIRX3_DP0, MIPIRX3_DN0), and (MIPIRX3_CN, MIPIRX3_CP).
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In the reference layout below, the three differential pairs of MIPI-RX4 are initially routed at Layer 1, and subsequently transition to Layer 6 near the connector. It is crucial to maintain a controlled differential impedance of 100Ω 100 Ω for all pairs. From top to bottom, the differential pairs are: (MIPI4_DP0, MIPI4_DN0), (MIPI4_SP, MIPI4_SN), and (MIPI4_DP1, MIPI4_DN1).
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In the reference layout below, the five differential pairs of MIPI-RX5 are initially routed at Layer 3, and subsequently transition to Layer 6 near the connector. It is crucial to maintain a controlled differential impedance of 100Ω 100 Ω for all pairs. From top to bottom, the differential pairs are: (MIPI5_DN2, MIPI5_DP2), (MIPI5_DN0, MIPI5_DP0), (MIPI5_SP, MIPI5_SN), (MIPI5_DN1, MIPI5_DP1), and (MIPI5_DP3, MIPI5_DN3).
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In the reference layout below, the five differential pairs of MIPI-TX are initially routed at Layer 1, and subsequently transition to Layer 6 near the connector. It is crucial to maintain a controlled differential impedance of 100Ω 100 Ω for all pairs. From top to bottom, the differential pairs are: (MIPITX_DP3, MIPITX_DN3), (MIPITX_DP2, MIPITX_DN2), (MIPITX_SP, MIPITX_SN), (MIPITX_DP1, MIPITX_DN1), and (MIPITX_DP0, MIPITX_DN0).
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TXD[3:0], TXEN, TXC, RXD[3:0], RXDV and RXC signals: 50Ω 50 Ω ±10%
2.4.9.5 Reference Layout
In the reference layout below, the nets of the RGMII are routed at Layer 1 and Layer 3, and subsequently transition to Layer 6 near the connector. Please maintain a controlled impedance of 50Ω 50 Ω for all RGMII signals throughout.
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2.4.10 Ethernet Interface (RMII)
2.4.10.1 General Rules
For single-ended signals, ensure that trace lengths run parallel to each other smoothly to maintain signal integrity. Avoid sharp corners, stubs in routing, as these can introduce impedance mismatches and signal reflections.
2.4.10.2 Trace Impedance
TXD[1:0], TXEN, REF_CLK, RXD[1:0] and CRS_DV signals : 50 Ω ±10%