This document elucidates the application circuits associated with the SP7350. It serves as a supplementary resource to the specification of the SP7350.
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All power sources should be managed using the CM4_PWR_EN signal. Specifically, when CM4_PWR_EN is set to LOW, all power supplies, including those for the CM4 and Main power domain, should be deactivated.
Please refer to the provided power scheme for details on power control.
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These pins serve as 1.8V general-purpose IO (GPIO) pins and are prefixed with "AO_" indicating their association with the Always On (CM4) power domain. For ease of reference, consult the table below to determine the corresponding GPIO number for manipulation of IO registers.
Pin Name | GPIO # | Power -supply Supply Pins |
AO_MX30 - AO_M48 | 80 - 98 | VDDPST18_GPIO_AO |
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Following the de-assertion of the RESET pin, these pins can be repurposed as GPIOs. Refer to the table below for the corresponding GPIO numbers for IO registers manipulation.
Pin Name | GPIO # | Power -supply Supply Pins |
IV_MX0 - IV_M6 | 99 - 105 | VDDPST18_GPIO_AO |
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Refer to the power scheme illustrated below. All powers in the main power domain should be controlled by both CM4_PWR_EN and MAIN_PWR_EN signals. Specifically, all powers in the main power domain are only turned on when both CM4_PWR_EN and MAIN_PWR_EN are set to HIGH.
It's important to note that during cold booting, CM4_PWR_EN goest to HIGH to initiate the booting process. Therefore, the default state ofMAIN_PWR_EN (when the GPIO is not yet programmed) should be HIGH to allow the CA55 to start booting.
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Typically, MAIN_PWR_EN is controlled by a GPIO in the CM4 domain. CM4 can directly set the power of the main power domain to either on or off.
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Refer to the table below for the target impedance for each power domain, ensuring optimal performance:
Power PinPins | Maximum current (A) | Ripple Spec. | Target impedance Impedance (mΩ) |
VDD | 2.1 | 5% | 19.0 |
VDD_VV | 1.7 | 5% | 23.9 |
VDD_CA55 | 1.0 | 5% | 40.0 |
VDD_NPU | 5.4 | 5% | 7.4 |
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For ease of reference, consult the table below to determine the corresponding GPIO number for manipulation of IO registers:
Pin Name | GPIO # | Power -supply Supply Pins |
G_MX0 - G_M19 | 0 - 19 | VDDPST18_GPIO_0 VDDPST18_GPIO_1 |
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The DVIO pins are divided into two groups, each with its own power supply and bias power pins. Refer to the table provided for pin grouping details:
Pin Name | GPIO # | Power -supply Supply Pins | Bias Power Pins |
G_MX21 - G_MX27 | 21 - 27 | VDDPST3018_DVIO_1 | VDDPST18_DVIO_1 |
G_MX20, G_M28 - G_MX37 | 20, 28 - 37 | VDDPST3018_DVIO_2 | VDDPST18_DVIO_2 |
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DDR Type | Max. Clock | Max. Data Rate | Max. BW (1 ch16 bits) | Max. BW (2 ch32 bits) |
|---|---|---|---|---|
LPDDR4 | 1.600 GHz | 3200 MT/s | 6.4 GB/s | 12.8 GB/s |
DDR4 | 1.333 GHz | 2666 MT/s | 5.3 GB/s | 10.7 GB/s |
LPDDR3 / DDR3 / DDR3L | 0.933 MHz | 1866 MT/s | 3.7 GB/s | 7.5 GB/s |
Please note that only LPDDR4, DDR4, DDR3L and DDR3 are verified.
5.1 Data Bus and Data Strobe Signals Wiring
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The DRAM_VDD power pins are designated for the digital core of the DDR PHY. It is essential to connect these pins to a 0.8V power source and include bypass capacitors for stable operation.
The DRAM_VDDQ power pins cater to the IO buffers of the DDR PHY. These pins must be connected to a 1.1V power source and equipped with bypass capacitors to ensure optimal performance.
The BP_VAA power pin serves the PLL of the DDR PHY. It is crucial to connect this pin to a 1.8V power source and include bypass capacitors to maintain stable PLL operation.
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For on-die terminator calibration, the BP_ZN pin should be linked to 240Ω resistors with 1% accuracy.
Refer to the table below for the operational range of each power source:
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Please refer to the schematics for the connection of power, control, address bus, and data bus of LPDDR4 SDRAM.
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For on-die terminator calibration, the ZQ0 and ZQ1 pins should be connected to 240Ω resistors with 1% accuracy, respectively.
5.3.3 Power and Ground of LPDDR4 SDRAM
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The DRAM_VDD power pins are designated for the digital core of the DDR PHY. It is essential to connect these pins to a 0.8V power source and include bypass capacitors for stable operation.
The DRAM_VDDQ power pins cater to the IO buffers of the DDR PHY. These pins must be connected to a 1.2V power source and equipped with bypass capacitors to ensure optimal performance.
The BP_VAA power pin serves the PLL of the DDR PHY. It is crucial to connect this pin to a 1.8V power source and include bypass capacitors to maintain stable PLL operation.
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For on-die terminator calibration, the BP_ZN pin should be linked to 240Ω resistors with 1% accuracy.
Refer to the table below for the operational range of each power source:
Power PinPins | Min. | Typ. | Max. | Remarks |
DRAM_VDD (V) | 0.75 | 0.80 | 0.88 | -7% ~ +10% |
BP_VAA (V) | 1.68 | 1.80 | 1.98 | -7% ~ +10% |
DRAM_VDDQ (V) | 1.14 | 1.20 | 1.26 | -5% ~ +5% |
It is crucial to design the PCB to meet target impedance values for the DRAM_VDD, DRAM_VDDQ, and BP_VAA power pins. Refer to the table below for the target impedance values for each power source:
Power PinPins | Maximum current (A) | Ripple Spec. | Target impedance Impedance (mΩ) |
DRAM_VDD | 0.394 | 2.5% | 50.8 |
DRAM_VDDQ | 0.429 | 5.0% | 139.8 |
BP_VAA | 0.00429 | 2.5% | 10479 |
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The DRAM_VDD power pins are designated for the digital core of the DDR PHY. It is essential to connect these pins to a 0.8V power source and include bypass capacitors for stable operation.
The DRAM_VDDQ power pins cater to the IO buffers of the DDR PHY. These pins must be connected to a 1.35V power source for DDR3L (or a 1.5V power source for DDR3) and equipped with bypass capacitors to ensure optimal performance.
The BP_VAA power pin serves the PLL of the DDR PHY. It is crucial to connect this pin to a 1.8V power source and include bypass capacitors to maintain stable PLL operation.
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bypass capacitors to maintain stable PLL operation.
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For on-die terminator calibration, the BP_ZN pin should be linked to 240Ω resistors with 1% accuracy.
Refer to the table below for the operational range of each power source:
Power PinPins | Min. | Typ. | Max. | Remarks |
DRAM_VDD (V) | 0.75 | 0.80 | 0.88 | -7% ~ +10% |
BP_VAA (V) | 1.68 | 1.80 | 1.98 | -7% ~ +10% |
DRAM_VDDQ (V) | 1.29 | 1.35 | 1.45 | -5% ~ +7.4% for DDRL3 |
1.43 | 1.50 | 1.57 | -5% ~ +5% for DDR3 |
It is crucial to design the PCB to meet target impedance values for the DRAM_VDD, DRAM_VDDQ, and BP_VAA power pins. Refer to the table below for the target impedance values for each power source:
Power PinPins | Maximum current (A) | Ripple Spec. | Target impedance Impedance (mΩ) |
DRAM_VDD | 0.344 | 2.5% | 58.2 |
DRAM_VDDQ | 0.638 | 5.0% | 117.6 |
BP_VAA | 0.00429 | 2.5% | 10479 |
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The SP7350 supports SPI-NAND flash for booting. To boot from an SPI-NAND flash, set the bootstrap pins IV_MX[6:2] to [1 1 1 0 1]. The SP7350 supports either 2k-sector with 1 or 2 planes or 4k-sector with 1 plane. When using a 1.8V flash chip, the maximum clock frequency is 153 MHz. It's advisable to use a 1.8V flash chip for optimal high-speed operation.
Special Note:
NAND flash memory in the market is categorized into SLC (Single-Level Cell) and MLC (Multi-Level Cell) types. It's advisable to use a 1.8V flash chip for optimal high-speed operationMLC NAND has a higher likelihood of developing bad cells. It's important to note that the Linux ubifs (sorted block image file system) subsystem does not support MLC NAND. Therefore, if you plan to use NAND flash as the primary storage (boot) device, it is recommended to opt for SLC NAND flash.
10.1 SPI-NAND Interface of SP7350
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The SP7350 supports booting from 8-bit NAND flash. To boot from an 8-bit NAND flash, set the bootstrap pins IV_MX[6:2] to [1 0 0 0 1]. The SP7350 is compatible with 2k-sector, 4k-sector, or 8k-sector NAND flash. For optimal high-speed performance, it's recommended to use a 1.8V VCCQ power supply.
Special Note:
NAND flash memory in the market is categorized into SLC (Single-Level Cell) and MLC (Multi-Level Cell) types. MLC NAND has a higher likelihood of developing bad cells. It's important to note that the Linux ubifs (sorted block image file system) subsystem does not support MLC NAND. Therefore, if you plan to use NAND flash as the primary storage (boot) device, it is recommended to opt for SLC NAND flash.
11.1 8-bit NAND Interface of SP7350
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USB20_DP and USB20_DM: These are the differential data signal pairs operating at 480 MHz. Maintain a differential impedance of 90Ω across the entire trace pair on the PCB.
USB20_VBUS: Connect this pin to the VBUS of a mini-B, mini-AB, micro-B, or micro-AB socket to detect VBUS presence during device mode or OTG function use. A 200kΩ resistor is incorporated in serial combination to divide VBUS (USB20_VBUS_OUT, 5V) voltage into the input range of USB20_VBUS pin, which operates between 0 and 1.8V. The input impedance of the USB20_VBUS pin is approximately 100kΩ. To further enhance stability and reliability, a 47nF 33nF capacitor is integrated to filter out noise, particularly voltage dips, from the VBUS line.
USB20_AVDD33: Connect to a 3.3V power source and add bypass capacitors for stable operation and improved signal integrity.
USB20_AVDD18: Connects to an internal 1.8V LDO. Leave unconnected.
USB20_R_TEST: For internal testing only. Leave unconnected.
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ILIM = 6800/6800 = 1.0 (A)
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Note that R218 and C247 are requested and defined by OTG specification. Do not alter their values.
The UPHY0_DRV5V_EN signal controls VBUS on/off states, generated by the OTG hardware of SP7350.
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17.2 MIPI-RX2 and MIPI-RX3
Note that MIPI-RX2 is not available for version A chips.
When CPIO is disabled, MIPI-RX2 and MIPI-RX3 are available for use. MIPI-RX2 supports four data and one clock lanes (4d1c) with 4 virtual channels if MIPI-RX3 is not enabled. However, if MIPI-RX3 is enabled, both MIPI-RX2 and RX3 support two data and one clock lanes (2d1c). Each data lane can transmit up to 1.5 Gbps. Please refer to the table for pin sharing between MIPI-RX2, MIPI-RX3, and CPIO.
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