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9.1. Power On Sequence
Parameter | Symbol | Min | Typ. | Max. | Units |
XTAL clock output stable time | TXTAL | 5 | - | - | us |
AO33V power on timing range | TAO33VPON | 0 | - | 5 | ms |
VDD33 power on timing range | TVDD33PON | 0 | - | 5 | ms |
Operation mode configure time after AO33V and VDD33 power ready (include internal core power ramp up time and reset circuit time cost) | TMODE | 15 | - | - | ms |
1.1.1.
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9.2. Power Down Sequence
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9.3. Reset State
There are 3 physically event to trigger chip reset.
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3. LVD (Low Voltage Detection)n
POR
The POR has 2 functions when AVDD33/DVDD12 becomes larger than the trip level. The first function is to give a reset pulse and the second function is to give a constant signal that tells whether the supply is on or off.
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Parameter | Symbol | Min | Typ. | Max. | Units |
trip-level | |||||
Low to High Threshold Point | VT+ | 1.51 | 1.61 | 1.67 | V |
High to Low Threshold Point | VT- | 0.92 | 0.98 | 1.02 | |
timing | |||||
Reset keep High Time | TRSTH | 1 | µs | ||
Reset keep Low Time | TRSTL | 1 | µs | ||
n LVD
When 1.5V/ 1.2V/ 0.9V voltage is lower than the setting reference voltage, reset signal will be assert to reset the whole chip.
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