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There are totally 64 pins can be set as Multiplex Peripheral Pins. Multiplex Peripheral Pins include ETH_SW, SDIO, PWM, Input Capture, SPI MASTER, SPI SLAVE, I2C MASTER, UART(1~4), TIMER, GPIO INT functions. This function can be controlled by Group1~3 Group2~3 registers. Please refer to chapter 5 for detail description of this function.
Another pinmux type which provide fixed function in fixed pins is also supported. They can be control by Group1.1~4 registers. For example, in the chapter 4 pin description, the pin92~97 describe as below:
| Pin Name | LQFP 176 Pin No | Type | Description(Multiplex Pins in this interface Shown in Bold) | Drive (mA) |
|---|---|---|---|---|
EMMC_D0/ SPI_NAND_D0 | 92 | I/O I/O | EMMC data pin0 SPI_NAND_D0 | |
EMMC_D1/ SPI_NAND_D2 | 93 | I/O I/O | EMMC data pin1 SPI_NAND_D2 | |
EMMC_CLK/ SPI_NAND_CLK | 94 | I/O I/O | EMMC clock pin SPI_NAND_CLK | |
EMMC_D2/ SPI_NAND_D1 | 95 | I/O I/O | EMMC data pin2 SPI_NAND_D1 | |
EMMC_D7/ SPI_NAND_D3 | 96 | I/O I/O | EMMC data pin7 SPI_NAND_D3 | |
EMMC_D6/ SPI_NAND_CEN | 97 | I/O I/O | EMMC data pin6 SPI_NAND_CEN |
If user set Group1.1[4] as "1", the pin92~97 will support SPI_NAND function interface.
If user set Group1.1[5] as "1". the pin92~97 will become EMMC function interface.
7.7 System GPIO control
There are totally 72 GPIO pins which are separated into 9 I/O ports, and each port contains 8 GPIO signals. The I/O driving capability for signals in GPIO0 is 16mA and 8mA for those in other GPIO ports. All 72 GPIO signals are Tri-state Output with Schmitt Trigger Input. The GPIO can be controlled by Group6~7 registers. Please refer to chapter 5 for detail description of this function.
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