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The physical characteristics of Nand Flash make a certain probability of error in the data reading and writing process, so there must be a corresponding error detection and correction mechanism, so the ECC is used for data error detection and correction. Nand Flash ECC, common algorithms are Hamming code and BCH. The implementation of such algorithms can be software or hardware. SP7021 implements a hardware BCH for this usage.
The BCH algorithm is usually implemented by the corresponding Nand Flash controller, including the corresponding hardware BCH ECC module, and implements the BCH algorithm. As a software aspect, it is necessary to operate the corresponding BCH-related before reading the data and before writing the data. The register is set to BCH mode, and then the corresponding BCH status register is read to know if there is an error, and the generated BCH check code is used for writing.
Figure 22-1 illustrates the general function units should be included in a system to confirm the normal operation flow of BCH engine, except CPU.
Figure 22-1 BCH operation in the system
The BCH IP is a BCH engine for BCH encode/decode with 14-level BCH algorithms. It can fetch data from system memory for encode/decode and write the result back to the system memory. The Memory is used to storage the data transferred. A NAND device is the data storage unit, which can be accessed by the NAND-Flash controller by a group of signals with proper NAND-Flash interface timing. All the function units communicate through the AXI BUS. Software can select auto encode/decode or manual trigger encode/decode mode.
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