1 Design Brief
The SP7021 SOC platform self-test experiment is mainly used to test the reliability of the SOC platform connection. The design of the FBIO is placed on the FPGA daughter board. The Plus1 chip reads and writes the FBIO to realize the reliability test of the connection between the Plus1 chip and the FPGA daughter board pin .
1.1 SP7021 SOC platform self-test design experiment project hardware platform implementation
The SP7021 SOC platform self-test experiment only needs to connect the axi_m and axi_s 64bit bus interfaces of the FBIO Wrapper together, and do the corresponding address mapping. That is, the access to the FBIO start address 0x70000000 is mapped to the access to the DRAM start address 0x00000000 in the Plus1 chip ;As shown below:
This experiment uses the FPGA daughter board supporting the Plus1 7021 practice platform to complete the relevant experiments. The development tool of the FPGA daughter board uses Xilinx's Vivado integrated development environment (version number 2018.3); in order to facilitate the connection of the user's own verification IP to the SOC system Verification, this experiment provides the corresponding design reference basic files, as follows
The corresponding connection between the design case and the pin connection of the SP7021 motherboard and FPGA daughter board is shown in the following table: 1: U20B on the motherboard is connected to J2 of the FPGA daughter board (Pin pin corresponding, such as 1-51 ...), providing the data transmission channel between the Plus1 main chip on the motherboard and the FPGA
Design Demo | FPGA daughter board | SP7021 mother board | |||
fbio_selftest | J2 | U1E | U20B | ||
Top Port Name | Schematic Name | FPGA I/O | Schematic Name | ||
| 1 | GND |
| 51 | GND |
| 2 | GND |
| 52 | GND |
FPGA_PAD[0] | 3 | B34_L24_N | T8 | 53 | FBIO_PAD_0 |
FPGA_PAD[43] | 4 | B34_L24_P | R8 | 54 | FBIO_PAD_1 |
| 5 | VIN |
| 55 | VCC(3.3V) |
| 6 | VCCIO34 |
| 56 | VCC(3.3V) |
FPGA_PAD[1] | 7 | B34_L21_N | V9 | 57 | FBIO_PAD_2 |
FPGA_PAD[42] | 8 | B34_L21_P | U9 | 58 | FBIO_PAD_3 |
FPGA_PAD[2] | 9 | B34_L18_N | N6 | 59 | FBIO_PAD_4 |
FPGA_PAD[41] | 10 | B34_L18_P | M6 | 60 | FBIO_PAD_5 |
FPGA_PAD[3] | 11 | B34_L22_N | U6 | 61 | FBIO_PAD_6 |
FPGA_PAD[40] | 12 | B34_L22_P | U7 | 62 | FBIO_PAD_7 |
FPGA_PAD[4] | 13 | B34_L20_N | V6 | 63 | FBIO_PAD_8 |
FPGA_PAD[39] | 14 | B34_L20_P | V7 | 64 | FBIO_PAD_9 |
FPGA_PAD[5] | 15 | B34_L23_N | T6 | 65 | FBIO_PAD_10 |
FPGA_PAD[38] | 16 | B34_L23_P | R7 | 66 | FBIO_PAD_11 |
FPGA_PAD[6] | 17 | B34_L10_N | V4 | 67 | FBIO_PAD_12 |
FPGA_PAD[37] | 18 | B34_L10_P | V5 | 68 | FBIO_PAD_13 |
FPGA_PAD[7] | 19 | B34_L19_P | R6 | 69 | FBIO_PAD_14 |
FPGA_PAD[36] | 20 | B34_L19_N | R5 | 70 | FBIO_PAD_15 |
FPGA_PAD[8] | 21 | B34_L8_P | U4 | 71 | FBIO_PAD_16 |
FPGA_PAD[35] | 22 | B34_L8_N | U3 | 72 | FBIO_TCLK |
FPGA_PAD[9] | 23 | B34_L9_N | V2 | 73 | FBIO_RCLK |
FPGA_PAD[34] | 24 | B34_L9_P | U2 | 74 | FBIO_PAD_17 |
FPGA_PAD[10] | 25 | B34_L7_N | V1 | 75 | FBIO_PAD_18 |
FPGA_PAD[33] | 26 | B34_L7_P | U1 | 76 | FBIO_PAD_19 |
FPGA_PAD[11] | 27 | B34_L13_P | N5 | 77 | FBIO_PAD_20 |
FPGA_PAD[32] | 28 | B34_L13_N | P5 | 78 | FBIO_PAD_21 |
FPGA_PAD[12] | 29 | B34_L12_P | T5 | 79 | FBIO_PAD_22 |
FPGA_PAD[31] | 30 | B34_L12_N | T4 | 80 | FBIO_PAD_23 |
FPGA_PAD[13] | 31 | B34_L11_N | T3 | 81 | FBIO_PAD_24 |
FPGA_PAD[30] | 32 | B34_L11_P | R3 | 82 | FBIO_PAD_25 |
FPGA_PAD[29] | 33 | B34_L14_P | P4 | 83 | FBIO_PAD_26 |
FPGA_PAD[28] | 34 | B34_L14_N | P3 | 84 | FBIO_PAD_27 |
FPGA_PAD[14] | 35 | B34_L16_N | N4 | 85 | FBIO_PAD_28 |
FPGA_PAD[27] | 36 | B34_L16_P | M4 | 86 | FBIO_PAD_29 |
FPGA_PAD[15] | 37 | B34_L17_N | T1 | 87 | FBIO_PAD_30 |
FPGA_PAD[26] | 38 | B34_L17_P | R1 | 88 | FBIO_PAD_31 |
FPGA_PAD[16] | 39 | B34_L15_N | R2 | 89 | FBIO_PAD_32 |
FPGA_PAD[25] | 40 | B34_L15_P | P2 | 90 | FBIO_PAD_33 |
FPGA_PAD[17] | 41 | B34_L3_N | N1 | 91 | FBIO_PAD_34 |
FPGA_PAD[24] | 42 | B34_L3_P | N2 | 92 | FBIO_PAD_35 |
FPGA_PAD[18] | 43 | B34_L1_N | M1 | 93 | FBIO_PAD_RSTB |
FPGA_PAD[23] | 44 | B34_L1_P | L1 | 94 | EXT0_INT |
| 45 | VCCIO34 |
| 95 | VCC(3.3V) |
| 46 | VIN |
| 96 | VCC(3.3V) |
FPGA_PAD[19] | 47 | B34_L4_P | M3 | 97 | EXT1_INT |
FPGA_PAD[20] | 48 | B34_L4_N | M2 | 98 |
|
| 49 | GND |
| 99 | GND |
| 50 | GND |
| 100 | GND |
1.2 Implementation of SP7021 SOC platform self-testing experiment system software platform
In the IDE environment, as shown below, select the sp7021 project name, click the right mouse button and select Copy in the pop-up menu
Next, select the sp7021 project name again;
Click the right mouse button and select Paste in the pop-up menu, the following picture appears
Fill in the fbio_selftest in the Project name box to complete the establishment of the fbio_selftest project name and directory, as shown below
Next, you need to copy all the files and folders under the installation directory \SP7021\example\ fbio_selftest to the fbio_selftest project directory built above (the path is: installation directory \SP7021\ workspace\fbio_selftest\), the file with the same name is selected to be overwritten, so SP7021 The program code main.c required for SOC platform self-test design practice; put it in the following path:
1) Install main.c in the directory \SP7021\workspace\fbio_selftest\ folder
Finally, as shown in the figure below, select the red box 1 with the mouse, then click the right mouse button to display the drop-down menu, and then select the red box 2, refresh the copy action just now, so that the file just copied can be displayed in the IDE environment.
main.c
int main(void)
{
printf("Build @%s, %s\n", __DATE__, __TIME__);
hw_init();
sys_init();
pin_mux();
disp_hdmi_init();
fbio_self_test();
printf("fbio self test finished \n");
while(1);
}
Compared with the digital tube control IP experiment, the fbio_self_test () function is added to complete the SP7021 SOC platform self-test experimental operation, as explained below.
void fbio_self_test()
{
unsigned int i,temp;
for (i = 0; i < 200; i++)
fbio_addr[i]=i;
for (i = 0; i < 100; i++)
{
temp=fbio_addr[i];
if(temp==i)
printf("@write value=[%x]; read value= [%x]\n", i,temp);
else
printf("Error @ temp= [%x];i= [%x] \n", temp,i);
}
}
The first for loop uses fbio to write to the DRAM address space 1 to 200 of the Plus1 chip;
The first for loop reads the DRAM address space 1 to 100 of the Plus1 chip through fbio; compares the read content with the written content, and if it is different, prints the Error message;
1.3 Program code running
After compile in the Plus1 IDE environment, download to the platform and see the following information in the terminal window
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