i-boot (ROM code)

i-boot, stored in the chip's internal mask ROM, plays a crucial role in the system's initialization process. During power-on reset, the program counters of all four ARM Cortex A55 CPUs are configured to point to the entry point address of i-boot. Upon the completion of power-on reset, the CPUs commence execution from this entry point. i-boot undertakes a series of essential tasks, including CPU initialization, setting up interrupt vectors, stack initialization, cache setup, serial port configuration, timer configuration, and more.

Following this initialization phase, i-boot loads x-boot from external storage devices into SRAM and performs a checksum verification. If the verification passes, i-boot proceeds to execute x-boot.

Key features of i-boot

1. Output log at UART0 with a baud rate of 115,200 bps.

2. UART0 pins can be turned off through an OTP bit.

3. Read bootstrap pins IV_MX[6..3] to decide boot-device.

4. Support for five boot devices: SPI-NOR flash, SPI-NAND flash, 8-bit NAND flash, eMMC, SD card, and USB flash drive (on either USB2.0 or USB3.0 port).

5. Implementation of secure-boot with the ability to verify the digital signature of the x-boot image and decrypt it.

6. Secure-boot activation controlled by an OTP bit.

7. Support for warm-boot, enabling wake-up from deep-sleep mode.

8. Support for the peripheral-reset signal (output from G_MX2).

Main flow

The i-boot flow initiates with the reset vector, followed by the execution of the "cpu_init" subroutine responsible for initializing the CPU. Next in the sequence is the "start_boot" subroutine, which sets up the C execution environment. The flow then advances to execute the "iboot_main" subroutine, serving as the C main function within i-boot.

The "iboot_main" subroutine commences by invoking the "init_cdata" subroutine to initialize global C data. It then proceeds to read boot-strap pins from a dedicated hardware register, storing the information in the C structure g_bootinfo. In the event of a warm-boot scenario, it checks the readiness of DRAM (where CM4 handles the restoration of DDR IO retention data and specific hardware registers or settings). If DRAM is confirmed ready, the subroutine redirects to the start address of the warm-boot module to continue the warm-boot processes.

In cases where a warm-boot is not applicable (in cold-start scenario), the process continues to execute the "AV1_STC_init()", "init_uart()", and "init_hw()" subroutines to initialize hardware components. Finally, it advances to run the "boot_flow()" subroutine.

The "boot_flow()" subroutine begins by examining the C structure g_bootinfo to determine the preferred boot device: eMMC, SPI-NAND flash, 8-bit NAND flash, SD card, or USB flash drive. It then initializes the controller of the selected boot device and loads the x-boot image into SRAM from the chosen source. After loading, the subroutine checks the image checksum. If the checksum passes verification, it proceeds to execute x-boot.

In the case of secure-boot activation through OTP bits, the subroutine additionally checks the digital signature and decrypts the image after the checksum validation.

It's essential to note that i-boot does not initialize DDR DRAM, rendering it temporarily unavailable. Hence, x-boot must be loaded into SRAM for execution.

Device drivers

i-boot supports for 5 boot devices. The following table lists the specifications of each boot device:

Boot core and other cores

CPU core 0 is the boot core and is responsible for booting. It is responsible for all boot processes from i-boot to Linux. CPU core 1, 2 and 3 spin (enter wfe mode) after initializing itself until core 0 wake up them.

Run Control of CPU (at bootcompat session) :

CPU_WAIT_INIT_VAL (0xffffffff)    // CPU waiting (spinning)

CPU_WAIT_A64_VAL (0xfffffffe)    // CPU goes to A64

x (address other than above)    // CPU goes to x

Bootstrap pins of SP7350

State of bootstrap pins of SP7350 will be read into bootstrap register (G0.31) at the moment that power-on reset is released. Refer to definition of boot-strap pins of SP7350 below:

Note:

1. If MX1 = 0, JTAG interface of CA55 of SP7350 will be enabled.

2. If MX2 = 0, SP7350 will enter test mode. Always set to 1 for normal operation.

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