Overview

This article provides a brief overview of the SP7350 software. Subsequent articles will delve into the detailed components of the software. The initial section begins with an introduction to source code and software operations, followed by an explanation of CPU addressing space. The final section touches on the device address map.

Table of Contents

Source Code

The source code for SP7350 is readily available on both GitHub and Gitee repositories:

• GitHub: SP7350 Source Code

• Gitee: SP7350 Source Code

For downloading and compiling the code, detailed instructions can be found at:

Downloading and Compiling Code

Additionally, for in-system programming of flash devices on the SP7350 platform, refer to:

In-system Programming Flash Devices

Software Operations

The software components include i-boot, x-boot, TF-A, OP-TEE, U-Boot, Linux, and FreeRTOS. The operation flow of these components is illustrated in the figure below:

Open

Upon power-on, i-boot loads the x-boot image from an external storage device into SRAM, verifies it, and executes it. x-boot initiates the DDR controller and conducts training for the DDR PHY. Upon the successful completion of DDR PHY training, DDR DRAM becomes operational. Subsequently, x-boot loads TF-A, OP-TEE, and U-Boot images from an external storage device into DRAM, verifying their integrity. Following this, it executes TF-A, which in turn calls OP-TEE and initiates U-Boot. U-Boot loads the Linux image from an external storage device into DRAM and executes it. Once Linux boots successfully, it proceeds to load the firmware of CM4 (FreeRTOS) and starts CM4.

Note that i-boot resides in the chip's internal mask ROM and is a hardware component. x-boot and U-Boot exist temporarily during boot time. Ubuntu server and ROS/ROS2 are optional. After a successful system boot, the stacked software components resemble the figure below:

Open

CPU (Cortex A55) Addressing Space

The CPU of SP7350 supports a 16 GiB addressing space (with 34 address lines), including 8 GiB for DRAM and 4 GiB reserved for CPIO. The addressing space layout is depicted in three figures for 2 GiB DRAM, 4 GiB DRAM, and 8 GiB DRAM.

Addressing Space for 2 GB DRAM

In the first 4 GiB address space, the initial 2 GiB is allocated for DRAM, while the remaining 0.25 GiB is reserved for chip internal devices and registers. The second and fourth 4 GiB address spaces are reserved, and the third 4 GiB address space is for the device (or P-chip) connected with the CPIO bus.

Open

Addressing Space for 4 GB DRAM

The first 0.75 GiB address space is allocated for DRAM, followed by 0.25 GiB for chip internal devices and registers. The initial 0.25 GiB of the second 4 GiB address space is allocated for DRAM, while the remaining 3.75 GiB is reserved. The third 4 GiB address space is for the device (or P-chip) connected with the CPIO bus, and the last 4 GiB address space is reserved.

Open

Addressing Space for 8 GB DRAM

The first 4 GiB address space is the same as the layout of 4 GiB DRAM. The second 4 GiB address space is allocated for DRAM, and the third 4 GiB address space is for the device (or P-chip) connected with the CPIO bus. The initial 0.25 GiB of the last 4 GiB address space is allocated for DRAM, while the remaining 3.75 GiB is reserved.

Open

Address Map of Devices and Registers

The detailed address map begins at address 0xf0000000. It includes segments such as 64 MiB of SPI-NOR flash, 64 MiB of SPI-NAND flash, device registers, AO device registers, DDR SRAM controller registers, Cortex-A55 registers, Cortex-M4 registers, CBDMA SRAM, CM4 SRAM, 8-bit NAND flash controller, and ROM.

Open

Interrupt

CA55 Interrupt Table