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The SPI FLASH controller IP core design is the AMBA AXI slave 32bit bus interface, and our FBIO Wrapper is the AMBA AXI 64bit bus interface. They cannot be directly connected together. A bridge of axi64_to_axi32 is required for connection We choose axi_ bus_ m32_bridge module from Bus Bridge series ,so the AXI master bus interface provided by the bus bride module is used to connect our IP as follows :
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This experiment uses the FPGA daughter board and extended test board supporting the Plus1 7021 SP7021 practice platform to complete the relevant experiments. The development tool of the FPGA daughter board uses the XILINX Vivado integrated development environment (version number 2018.3); in order to facilitate the convenience of the user to verify the IP Connected to the SOC system to verify, this experiment provides the corresponding design reference basic file, as follows
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