SPI FLASH Controller IP design

Case download:
spi_flash_axi.zip

1 Design Brief

SPI (Serial Peripheral Interface) serial peripheral device interface bus system is a high-speed, full-duplex, synchronous communication bus, which enables MCU to communicate with various peripheral devices in a serial manner to exchange information. The SPI bus system can directly interface with a variety of standard peripheral devices produced by various manufacturers. It is mainly used between EEPROM, FLASH, real-time clock, AD converter, digital signal processor and digital signal decoder.

The SPI bus system interface signals are as follows:

（1）SDO-Master device data output, slave device data input

（2）SDI – Master device data input, slave device data output

（3）SCLK – Clock signal, generated by the master device

（4）CS-slave device enable signal, controlled by the master device

The communication principle of SPI is simple. It works in a master-slave mode. This mode usually has a master device and one or more slave devices. It requires 4 wires, and only occupies four wires on the pins of the chip, saving the chip's The pins also save space and provide convenience for the layout of the PCB. It is precisely because of this simple and easy-to-use feature that more and more chips are now integrating this communication protocol.

Among them, CS is to control whether the chip is selected, that is to say, only when the chip selection signal is a predetermined enable signal (high potential or low potential), the operation of this chip is effective. This allows multiple SPI devices to be connected on the same bus. The next three lines are responsible for communication. The SCLK signal line is only controlled by the master device, and the slave device cannot control the signal line. SPI is a serial communication protocol, and data is transmitted bit by bit. SCLK provides the clock pulse, and SDI and SDO complete the data transmission based on this pulse. The data output goes through the SDO line, and the data changes on the rising or falling edge of the clock and is read on the following falling or rising edge. To complete a one-bit data transfer, the input also uses the same principle. In this way, at least 8 clock signal changes (upper edge and lower edge is once), you can complete the 8-bit data transmission.

SPI is also a data exchange protocol: because the data input and output lines of the SPI are independent, it is allowed to complete the data input and output at the same time. Different SPI devices have different implementation methods, mainly because the data change and acquisition time are different. There are different definitions for the upper or lower edge of the clock signal. For details, please refer to the relevant device documentation.

The controller designed in this practice follows the standard and universal SPI Flash control protocol, which can realize the operation of SPI Flash device of multiple manufacturers. The DIP 8 socket on the supporting test expansion board can be plugged into the SPI Flash device of different manufacturers; It is the W25xx series of Winbond, and its port structure is shown in the figure:

Winbond W25xx series SPI NOR Flash

The SPI interface of W25xx consists of 8 pins: /CS, DO, /WP, GND, VCC, /HOLD, CLK and DIO, where GND and VCC are the power supply terminals, and CLK is the clock of the entire SPI bus, DIO is the host Output, slave input, DO is the master input, slave output. /CS is the selection flag port of the slave. In two SPI bus devices that communicate with each other, /CS is controlled by the master. When /CS is low, the master and the slave start to exchange information. / WP is the FLASH status protection port. When /WP is low, some FLASH status bits cannot be changed, which can indirectly protect the data in the FLASH memory and prevent the loss of original data caused by the writing of external data . In this example, through the research and implementation of the most basic Flash device and SPI bus protocol, the SPI Flash Controller is designed to familiarize with the design and verification of the IP core.

2 Design specifications

l Support AMBA4 AXI(lite) 32 bit Bus interface.

l Support SPI flash 1 bit interface.

l Support SPI mode 0 and SPI mode 3 programable

l Support 4 byte read/write buffer.

l Support the following instruction: Write Enable/Disable, Read/Write Status Register, Read Data, Fast Read, Page Program, Block/Sector/Chip Erase, Read JEDEC ID.

l Support write buffer before starting write_opeartion to device.

l Support buffer empty/full interrupt.

l Support transfer complete interrupt.

l Support buffer empty/full and transfer complete status polling.

l Support interrupt status write "1" clear.

l Support interrupt enable/disable/programable.

l Support system clock frequency 25MHz to 100MHz.

l Support SPI interface transfer speed configurable: 1/4 system clock, 1/8 system clock, 1/16 system clock.

l Support software reset.

3 I/O Ports Description

3.1 Global signal

Name

Direction

Width

Description

SYSCLK

Input

1

Global Clock Input

25 -100Mhz

RST_B

Input

1

Global Asynchronous Reset Input

Low active.

3.2 AXI Interface

Name	Direction	Width	Description
AWVALID	Input	1	Write Address Valid This signal indicates that valid write address and control information are available..
AWREADY	Output	1	Write Address Ready This signal indicates that the slave is ready to accept an address and associated control signals..
AWADDR	Input	32	Write Address The write address bus gives the address of the first transfer in a writer burst transaction.
AWPROT	Input	3	Protect type This signal indicates the normal, priviledged, or secure protection level of the transaction and whether the transaction.
WVALID	Input	1	Write Valid This signal indicates that valid write data and strobes are available.
WREADY	Output	1	Write Ready This signal indicates that slave can accept the write data.
WDATA	Input	32	Write Data The write data bus is 32 bit wide.
WSTRB	Input	4	Write strobes This signal indicates which bytes lanes to update in memory.
BVALID	Output	1	Write Response Valid This signal indicates that a valid write response is available.
BREADY	Input	1	Write Response Ready This signal indicates that the master can accept the response information.
BRESP	Output	2	Write Response This signal the status of the write transaction.
ARVALID	Input	1	Read Address Valid This signal indicates, when HIGH, that read address and control information is valid and will remain stable until the address acknowledge signal, ARREADY, is high
ARREADY	Output	1	Read Address Ready This siganl indicates that the slave is ready to accept an address and associated control signal.
ARADDR	Input	32	Read Address The read address bus gives the initial address of a read burst transaction.
ARPORT	Input	3	Protect type This signal indicates the normal,priviledged, or secure protetion level of the transaction and whether the transaction is a data access or an instruction access.
RVALID	Output	1	Read Valid This signal indicates that the required read data is available and the read transfer can complete.
RREADY	Input	1	Read Ready This signal indicates that the master can accept the read data and response information.
RDATA	Output	32	Read Data This read data bus is 32 bit wide.
RRESP	Output	2	Read Response This signal indicates the status of the read transaction.

3.3 SPI Interface

Name	Direction	Width	Description
SPI_CLK	Output	1	SPI Serial Clock Serial Clock for SPI Flash
SPI_DI	Input	1	Serial Data Input Serial Data Output for SPI Flash
SPI_DO	Output	1	Serial Data Input Serial Data Input for SPI Flash
SPI_CS_B	Output	1	SPI Chip Select Chip Enable for SPI Flash.Low active to indicate that the SPI Flash is selected.

3.4 Interrupt

Name

Direction

Width

Description

SPI_INT

Output

1

SPI Interrupt

SPI Flash controller interrupt signal, high active

4 Registers File

Register Lists

Address	Name	Access	Description
32'h0	SPI_CON	RW	SPI Configuration Register .
32'h4	SPI_MODE	RW	SPI Mode Configuration Register.
32'h8	SPI_CMD	RW	SPI Flash Operation Command and Address.
32'hc	INT_FLAG	RW	The Interrupt Status Register
32'h10	INT_MASK	RW	The Interrupt Mask Register.
32'h14	W_DATA	RW	Transfer Data. Data from CPU.
32'h18	R_DATA	RW	Receive Data. Data from SPI Flash.
32'h1c	BYTE_NUM	RW	Indicate Write/Read Bytes.

4.1 SPI Configuration Register (SPI_CON,ADDR=32'h0)

Default value: 32’h00

Register Bits	Access	Function Description
0	STR	Start FLAG High active to indicate start an operation.
1	WR	Write/Read FLAG This bit indicate write or read operation. 0: Write Flash; 1: Read Flash;
2	RST_SW	Software Reset FLAG High active to indicate software reset Flash.
31:3	Reserved	Reserved

4.2 SPI Mode Configuration Register(SPI_MODE,ADDR=32'h4)

Default value: 32’h0

Register Bits	Access	Function Description
0	SPI_MODE	SPI Flash Work Mode This bit indicate the work mode of Flash. 0: mode 0; 1: mode 3;
2:1	CLK_MODE	Clock Mode This bits indicate the Clock mode of Flash. 00:1/4 system clock 01:1/8 system clock 10:1/16 system clock 11:Reserved
31:3	Reserved	Reserved

4.3 SPI Flash Command and Address (SPI_CMD,ADDR=32'h8)

Default value: 32’h0

Register Bits	Access	Function Description
7:0	CMD	Command Code The SPI Flash control operation code.
15:8	ADDR_H	The High 8 bits address The high 8 bits address to indicate the start of W/R into the flash.
23:16	ADDR_M	The Middle 8 bits address The middle 8 bits address to indicate the start of W/R into the flash.
31:24	ADDR_L	The Low 8 bits address The low 8 bits address to indicate the start of W/R into the flash.

4.4 Interrupt Status Register (INT_FLAG,ADDR=32'hc)

Default value: 32’h0

Register Bits	Access	Function Description
0	CMP_FLAG	Transfer complete Flag, Write 1 Clear High active to indicate transfer complete state.
1	T_EMP_FLAG	Transfer FIFO Empty Flag, Write 1 Clear High active to indicate transfer FIFO empty state.
2	T_FUL_FLAG	Transfer FIFO Full Flag, Write 1 Clear High active to indicate transfer FIFO full state.
3	R_EMP_FLAG	Receive FIFO Empty Flag, Write 1 Clear High active to indicate receive FIFO empty state.
4	R_FUL_FLAG	Receive FIFO Full Flag, Write 1 Clear High active to indicate receive FIFO full state.
31:3	Reserved	Reserved

4.5 Interrupt Mask Register (INT_MASK,ADDR=32'h10)

Default value: 32’h0

Register Bits	Access	Function Description
0	CMP_MASK	Mask of Transfer complete Flag High active.
1	T_EMP_MASK	Mask of Transfer FIFO Empty Flag High active.
2	T_FUL_MASK	Mask of Transfer FIFO Full Flag High active.
3	R_EMP_MASK	Mask of Receive FIFO Empty Flag High active .
4	R_FUL_MASK	Mask of Receive FIFO Full Flag High active.
30:5	Reserved