This document elucidates the application circuitry associated with the SP7350. It serves as a supplementary resource to the specification of the SP7350.
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All power sources should be managed using the CM4_PWR_EN signal. Specifically, when CM4_PWR_EN is set to LOW, all power supplies, including those for the CM4 and Main power domain, should be deactivated.
Please refer to the provided power scheme for details on power control.
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Refer to the power scheme illustrated below. All powers in the main power domain should be controlled by both CM4_PWR_EN and MAIN_PWR_EN signals. Specifically, all powers in the main power domain are only turned on when both CM4_PWR_EN and MAIN_PWR_EN are set to HIGH.
It's important to note that during cold booting, CM4_PWR_EN goest to HIGH to initiate the booting process. Therefore, the default state ofMAIN_PWR_EN (when the GPIO is not yet programmed) should be HIGH to allow the CA55 to start booting.
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Typically, MAIN_PWR_EN is controlled by a GPIO in the CM4 domain. CM4 can directly set the power of the main power domain to either on or off.
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DDR Type | Max. Clock | Max. Data Rate | Max. BW (1 ch) | Max. BW (2 ch) |
|---|---|---|---|---|
LPDDR4 | 1.600 GHz | 3200 MT/s | 6.4 GB/s | 12.8 GB/s |
DDR4 | 1.333 GHz | 2666 MT/s | 5.3 GB/s | 10.7 GB/s |
LPDDR3 / DDR3 / DDR3L | 0.933 MHz | 1866 MT/s | 3.7 GB/s | 7.5 GB/s |
Please note that only LPDDR4, DDR4, DDR3L and DDR3 are verified.
5.1 Data Bus and Data Strobe Signals Wiring
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ILIM = 6800/6800 = 1.0 (A)
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Note that R218 and C247 are requested and defined by OTG specification. Do not alter their values.
The UPHY0_DRV5V_EN signal controls VBUS on/off states, generated by the OTG hardware of SP7350.
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17.2 MIPI-RX2 and MIPI-RX3
Note that MIPI-RX2 is not available for version A chips.
When CPIO is disabled, MIPI-RX2 and MIPI-RX3 are available for use. MIPI-RX2 supports four data and one clock lanes (4d1c) with 4 virtual channels if MIPI-RX3 is not enabled. However, if MIPI-RX3 is enabled, both MIPI-RX2 and RX3 support two data and one clock lanes (2d1c). Each data lane can transmit up to 1.5 Gbps. Please refer to the table for pin sharing between MIPI-RX2, MIPI-RX3, and CPIO.
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It's recommended to include ESD protection diodes for MIPITX data and clock differential pairs.
19.
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Audio I2S Interface
The SP7350 board supports the JTAG ICE interface for Cortex A55 (CA55). This interface enables developers to perform real-time debugging by connecting to the CA55 processor's JTAG (audio interface of SP7350 comprises one bidirectional and two unidirectional I2S interfaces. Each interface supports 2-channel (L/R) operation and can function in either master or slave mode, with configurable clock frequency and LRCK polarity.
For a detailed pin-out of the SP7350 audio I2S interface, refer to the https://sunplus.atlassian.net/wiki/spaces/C3/pages/1971126471/SP7350+Specification#10.-Audio-Interface.
19.1 Audio I2S ADC and DAC Chip
Below is the pin-out for channel 0 of the SP7350 audio I2S interface:
Signal Name | Pins of X1 Position | Pins of X2 Position | Type | Config Bits | Remarks | |||||||||
AU_BCK | AO_MX44 | AO_MX22 | I/O | G1.6[1:0] | Bit clock | |||||||||
AU_LRCK | AO_MX45 | AO_MX23 | I/O | LR clock | ||||||||||
ADC_DATA0 | AO_MX46 | AO_MX24 | I | DATA in | ||||||||||
AU_DATA0 | AO_MX47 | AO_MX25 | O | DATA out | ||||||||||
In the schematics, an ES8316 audio ADC and DAC chip is utilized. The I2S interface signals of the ES8316 connect to position X1 of channel 0 on the SP7350. The MCLK pin of the ES8316 connects to the EXT_DAC_XCK (GPIO83) audio clock output pin of the SP7350. Additionally, the I2C interface of the ES8316 connects to I2C4 on the SP7350, with I2C4_CLK and I2C4_DATA configured to GPIO90 and GPIO91, respectively.
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Bypass capacitors are added to all power pins for improved power integrity, and ferrite beads are used on power lines to filter high-frequency noise and interference.
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19.2 4-Pole Audio Jack
A 4-pole 3.5mm TRRS plug is used for the headset, as depicted in the figure below.
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The CTIA TRRS standard, commonly used by modern smartphones and Apple devices, defines the pin-out as:
Tip: Left Audio
Ring 1: Right Audio
Ring 2: Ground
Sleeve: Microphone
In the schematics, the MIC_LIN2 signal from the LIN2 pin of the ES8316 connects to pin 1 of the PJ-393-8PJ audio jack, with a bias circuit driven by the MICBIAS pin of the ES8316. HPR_OUT (from LOUT pin) and HPL_OUT (from ROUT pin) connect to pins 5 and 7 of the audio jack, respectively.
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According to the specifications of the PJ-393-8PJ audio jack, when the audio plug is not inserted, pins 1 and 2, pins 3 and 4, pins 5 and 6, and pins 7 and 8 remain connected. Based on the schematics, if the audio plug is not inserted:
MIC_LIN2 is connected to GND
HPR_OUT is connected to SPKR_OUT
HPL_OUT is connected to SPKL_OUT
The HPR_OUT and HPL_OUT signals are routed to the audio amplifier. When the audio plug is inserted, MIC_LIN2, HPR_OUT, and HPL_OUT exclusively come from the headset.
It's recommended to include ESD protection diodes for MIC_RIN2, SPK1_N, and SPK1_P signals if the devices are human-accessible.
19.3 Audio Amplifier, Speaker and Microphone
In the schematics, an HT6872 audio amplifier drives a small speaker. The SPK_IN signal is mixed from the SPKR_OUT and SPKL_OUT signals. The SPK_CTL signal should connect to a GPIO pin, set to HIGH to enable the amplifier. The microphone output (MIC_RIN2 signal) connects to the RIN2 pin of the ES8316, with a bias circuit driven by the MICBIAS pin of the ES8316.
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It's recommended to include ESD protection diodes for MIC_RIN2, SPK1_N, and SPK1_P signals if the devices are human-accessible.
20. CA55 JTAG Interface
The SP7350 board supports the JTAG ICE interface for Cortex A55 (CA55). This interface enables developers to perform real-time debugging by connecting to the CA55 processor's JTAG (Joint Test Action Group) interface.
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20.1 CA55 JTAG Pins
The interface pins are mapped to GPIO13 to GPIO17, corresponding to the TRST_N, TMS, TCK, TDI, and TDO signals of JTAG.
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To activate the JTAG interface, users should configure G1.1[8] to 1 or set bootstrap pin IV_MX[1] to 0. Please note that the JTAG interface pins share functionality with RGMII pins and cannot be used simultaneously.
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20.2 CA55 JTAG Pin-header
Referring to the schematics below, the standard JTAG connector is a 2x10-pin 100mil-pitch pin-header. Pin 1 serves as the reference voltage for JTAG signals, while Pin 2 provides optional VCC power. The JTAG_nSRST signal (low-active), derived from the RESETB signal, functions as the system reset. It's important to note that the CA55 JTAG signals operate at 1.8V.
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21. CM4 JTAG/SWD Interface
The SP7350 also supports the JTAG and SWD ICE interfaces for Cortex M4 (CM4). Both interfaces allow developers to debug their target systems in real-time. JTAG is the traditional interface, while SWD (Serial Wire Debug) is a two-wire protocol designed specifically for ARM processors, offering an alternative when pin resources are limited or PCB layout is constrained.
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21.1 CM4 JTAG/SWD Pins
For JTAG, the interface pins are GPIO88 to GPIO93, corresponding to TRST_N, TMS, TCK, TDI, and TDO signals. For SWD, the pins are GPIO89, GPIO90, and GPIO93, corresponding to SWDIO, SWCLK, and SWDO signals.
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To activate the JTAG interface, users should configure G1.5[0] to 1.
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21.2 CM4 JTAG and SWD Pin-header
Referring to the schematics below, the standard JTAG/SWD connector is a 2x10-pin 100mil-pitch pin-header. Pin 1 provides the reference voltage for JTAG signals, and Pin 2 offers optional VCC power. Similar to CA55, the CM4_JTAG_nSRST signal (low-active) for system reset is derived from the RESETB signal. Note that the CM4 JTAG signals operate at 1.8V.
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22. UA2AXI Interface
The UA2AXI interface is a proprietary UART interface by Sunplus that connects to the internal AXI bus of the SP7350. The UA2AXI interface shares its interface with UADBG (UART5), which is a standard UART and can be probed by Linux.
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22.1 UA2AXI Pins of SP7350
The interface pins for UA2AXI are GPIO13 (TXD) and GPIO14 (RXD). Both GPIO13 and GPIO14 are 1.8V power GPIO pins belonging to the SYS_1V8 power group.
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22.2 Voltage Translator and UA2AXI Port
The voltage translator for UA2AXI comprises the Si2302 (N-channel MOSFET) and resistors, which convert the signal levels of UA2AXI from SYS_1V8 (1.8V) to SYS_3V3 (3.3V) and vice versa.
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