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Design Brief
SPI（Serial Peripheral Interface）串行外围设备接口总线系统，是一种高速的，全双工，同步的通信总线，它可以使MCU与各种外围设备以串行方式进行通信以交换信息。SPI总线系统可直接与各个厂家生产的多种标准外围器件直接接口，主要应用在 EEPROM，FLASH，实时时钟，AD转换器，还有数字信号处理器和数字信号解码器之间。
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W25xx的SPI接口由8个引脚构成：/CS，DO，/WP，GND，VCC，/HOLD，CLK及DIO，其中GND和VCC是电源端，而CLK是整个SPI总线的时钟， DIO是主机的输出，从机的输入，DO 是主机的输入，从机的输出。/CS是从机的选择标志端口，在互相通信的两个SPI总线的器件，/CS 由主机控制，当/CS为低电平时，主机与从机开始交互信息。/WP为FLASH状态保护端口，当/WP为低电平时，FLASH部分状态位无法改变，这样可以间接对FLASH memory中的数据起到保护作用，防止外来数据的写入而造成原有数据的丢失。本实例通过对最基本的Flash 器件和SPI总线协议的研究和实现，设计了SPI Flash Controller, 以此来熟悉IP核的设计和验证。
2 设计规格
l Support AMBA4 AXI(lite) 32 bit Bus interface.
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l Support software reset.
3 I/O Ports Description
3.1 Global signal
Name | Direction | Width | Description |
SYSCLK | Input | 1 | Global Clock Input 25 -100Mhz |
RST_B | Input | 1 | Global Asynchronous Reset Input Low active. |
3.2 AXI Interface
Name | Direction | Width | Description |
AWVALID | Input | 1 | Write Address Valid This signal indicates that valid write address and control information are available.. |
AWREADY | Output | 1 | Write Address Ready This signal indicates that the slave is ready to accept an address and associated control signals.. |
AWADDR | Input | 32 | Write Address The write address bus gives the address of the first transfer in a writer burst transaction. |
AWPROT | Input | 3 | Protect type This signal indicates the normal, priviledged, or secure protection level of the transaction and whether the transaction. |
WVALID | Input | 1 | Write Valid This signal indicates that valid write data and strobes are available. |
WREADY | Output | 1 | Write Ready This signal indicates that slave can accept the write data. |
WDATA | Input | 32 | Write Data The write data bus is 32 bit wide. |
WSTRB | Input | 4 | Write strobes This signal indicates which bytes lanes to update in memory. |
BVALID | Output | 1 | Write Response Valid This signal indicates that a valid write response is available. |
BREADY | Input | 1 | Write Response Ready This signal indicates that the master can accept the response information. |
BRESP | Output | 2 | Write Response This signal the status of the write transaction. |
ARVALID | Input | 1 | Read Address Valid This signal indicates, when HIGH, that read address and control information is valid and will remain stable until the address acknowledge signal, ARREADY, is high |
ARREADY | Output | 1 | Read Address Ready This siganl indicates that the slave is ready to accept an address and associated control signal. |
ARADDR | Input | 32 | Read Address The read address bus gives the initial address of a read burst transaction. |
ARPORT | Input | 3 | Protect type This signal indicates the normal,priviledged, or secure protetion level of the transaction and whether the transaction is a data access or an instruction access. |
RVALID | Output | 1 | Read Valid This signal indicates that the required read data is available and the read transfer can complete. |
RREADY | Input | 1 | Read Ready This signal indicates that the master can accept the read data and response information. |
RDATA | Output | 32 | Read Data This read data bus is 32 bit wide. |
RRESP | Output | 2 | Read Response This signal indicates the status of the read transaction. |
3.3 SPI Interface
Name | Direction | Width | Description |
SPI_CLK | Output | 1 | SPI Serial Clock Serial Clock for SPI Flash |
SPI_DI | Input | 1 | Serial Data Input Serial Data Output for SPI Flash |
SPI_DO | Output | 1 | Serial Data Input Serial Data Input for SPI Flash |
SPI_CS_B | Output | 1 | SPI Chip Select Chip Enable for SPI Flash.Low active to indicate that the SPI Flash is selected. |
3.4 Interrupt
Name | Direction | Width | Description |
SPI_INT | Output | 1 | SPI Interrupt SPI Flash controller interrupt signal, high active |
4 Registers File
Register Lists
Address | Name | Access | Description |
32'h0 | SPI_CON | RW | SPI Configuration Register . |
32'h4 | SPI_MODE | RW | SPI Mode Configuration Register. |
32'h8 | SPI_CMD | RW | SPI Flash Operation Command and Address. |
32'hc | INT_FLAG | RW | The Interrupt Status Register |
32'h10 | INT_MASK | RW | The Interrupt Mask Register. |
32'h14 | W_DATA | RW | Transfer Data. Data from CPU. |
32'h18 | R_DATA | RW | Receive Data. Data from SPI Flash. |
32'h1c | BYTE_NUM | RW | Indicate Write/Read Bytes. |
4.1 SPI Configuration Register (SPI_CON,ADDR=32'h0)
Default value: 32’h00
Register Bits | Access | Function Description |
0 | STR | Start FLAG High active to indicate start an operation. |
1 | WR | Write/Read FLAG This bit indicate write or read operation. 0: Write Flash; 1: Read Flash; |
2 | RST_SW | Software Reset FLAG High active to indicate software reset Flash. |
31:3 | Reserved | Reserved |
4.2 SPI Mode Configuration Register(SPI_MODE,ADDR=32'h4)
Default value: 32’h0
Register Bits | Access | Function Description |
0 | SPI_MODE | SPI Flash Work Mode This bit indicate the work mode of Flash. 0: mode 0; 1: mode 3; |
2:1 | CLK_MODE | Clock Mode This bits indicate the Clock mode of Flash. 00:1/4 system clock 01:1/8 system clock 10:1/16 system clock 11:Reserved |
31:3 | Reserved | Reserved |
4.3 SPI Flash Command and Address (SPI_CMD,ADDR=32'h8)
Default value: 32’h0
Register Bits | Access | Function Description |
7:0 | CMD | Command Code The SPI Flash control operation code. |
15:8 | ADDR_H | The High 8 bits address The high 8 bits address to indicate the start of W/R into the flash. |
23:16 | ADDR_M | The Middle 8 bits address The middle 8 bits address to indicate the start of W/R into the flash. |
31:24 | ADDR_L | The Low 8 bits address The low 8 bits address to indicate the start of W/R into the flash. |
4.4 Interrupt Status Register (INT_FLAG,ADDR=32'hc)
Default value: 32’h0
Register Bits | Access | Function Description |
0 | CMP_FLAG | Transfer complete Flag, Write 1 Clear High active to indicate transfer complete state. |
1 | T_EMP_FLAG | Transfer FIFO Empty Flag, Write 1 Clear High active to indicate transfer FIFO empty state. |
2 | T_FUL_FLAG | Transfer FIFO Full Flag, Write 1 Clear High active to indicate transfer FIFO full state. |
3 | R_EMP_FLAG | Receive FIFO Empty Flag, Write 1 Clear High active to indicate receive FIFO empty state. |
4 | R_FUL_FLAG | Receive FIFO Full Flag, Write 1 Clear High active to indicate receive FIFO full state. |
31:3 | Reserved | Reserved |
4.5 Interrupt Mask Register (INT_MASK,ADDR=32'h10)
Default value: 32’h0
Register Bits | Access | Function Description |
0 | CMP_MASK | Mask of Transfer complete Flag High active. |
1 | T_EMP_MASK | Mask of Transfer FIFO Empty Flag High active. |
2 | T_FUL_MASK | Mask of Transfer FIFO Full Flag High active. |
3 | R_EMP_MASK | Mask of Receive FIFO Empty Flag High active . |
4 | R_FUL_MASK | Mask of Receive FIFO Full Flag High active. |
30:5 | Reserved | Reserved |
31 | GLO_MASK | Global Mask |
4.6 WRITE DATA (W_DATA,ADDR=32'h14)
Default value: 32’h0
Register Bits | Access | Function Description |
31:0 | W_DATA | Save the Data from CPU 32 bits. |
4.7 Read Data FIFO (R_DATA,ADDR=32'h18)
Default value: 32’h0
Register Bits | Access | Function Description |
31:0 | R_DATA | Save the Data from SPI Flash 32 bits. |
4.8 BYTE _NUM (ADDR=32'h1c)
Default value: 32’h1
Register Bits | Access | Function Description |
15:0 | BYTE_NUM | BYTE COUNT Indicate the bytes of data R/W. |
31:16 | Reserved | Reserved |
5 Functional Description
5.1 SPI Flash Controller Block Diagram
The FSM is used to control and harmonize the whole system. Master configures the necessary information to the controller through AXI Bus
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Interface : Translate the logic
5.2 Internal FSM
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Current State | Function | Next Status | Jump Condition |
IDLE | Wait start signal | T_CMD | STR = 1 |
IDLE | STR = 0 or Reset not end | ||
T_CMD | Transfer Command | T_ADDR_H | T_count = 8 |
T_DATA | The command is 9FH | ||
IDLE | The commnd is 06H|04H| C7H/60H | ||
T_ADDR_H | Transfer the address high 8 bits. | T_ADDR_M | T_count = 8 |
T_ADDR_M | Transfer the address middle 8 bits. | T_ADDR_L | T_count = 8 |
T_ADDR_L | Transfer the address low 8 bits | IDLE | CMD is D8H|52H|20H |
T_DATA | T_count = 8 | ||
T_DATA | Transfer data | T_DATA | Transfer data not end |
IDLE | Transfer data end |
5.3 FIFO
FIFO is important to this design as all data are transferred by it. Following is the 2-pointer FIFO.
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When FIFO is full/empty but still write/read, FIFO will overflow/underflow.
5.4 Polling Status and Interrupt
The design provide programmable interrupt output and polling the interrupt flag through INT_FLAG. SPI_INT will be high when interrupt happens.
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Interrupt source | Description | Mask bit |
CMP_FLAG | Transfer Complete | 0 |
T_EMP_FLAG | Transfer FIFO Empty Flag | 1 |
T_FUL_FLAG | Transfer FIFO Full Flag | 2 |
R_EMP_FLAG | Receive FIFO Empty Flag | 3 |
R_FUL_FLAG | Receive FIFO Full Flag | 4 |
6 Timing Figures
6.1 AXI Bus Write
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6.2 AXI Bus Read
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6.3 SPI Bus Write
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6.4 SPI Bus Read
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6.5 SPI Clock
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6.6 Parallel to Serial
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6.7 Serial to Parallel
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7 SOC 整合实现
7.1 SPI FLASH 控制器IP设计实验项目的硬件平台实现
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operation_done();等待从flash device读8byte数据,直到操作完成
程序代码运行
在Plus1 IDE环境中compile后，下载到平台，在terminal窗口看到如下信息
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