1 设计简介
SPI（Serial Peripheral Interface）串行外围设备接口总线系统，是一种高速的，全双工，同步的通信总线，它可以使MCU与各种外围设备以串行方式进行通信以交换信息。SPI总线系统可直接与各个厂家生产的多种标准外围器件直接接口，主要应用在 EEPROM，FLASH，实时时钟，AD转换器，还有数字信号处理器和数字信号解码器之间。
SPI总线系统接口信号如下：
（1）SDO –主设备数据输出，从设备数据输入
（2）SDI –主设备数据输入，从设备数据输出
（3）SCLK –时钟信号，由主设备产生
（4）CS –从设备使能信号，由主设备控制
SPI的通信原理简单，以主从方式工作，这种模式通常有一个主设备和一个或多个从设备，需要4根线，并且在芯片的管脚上只占用四根线，节约了芯片的管脚，同时为PCB的布局上节省空间，提供方便，正是出于这种简单易用的特性，现在越来越多的芯片集成了这种通信协议。。
其中CS是控制芯片是否被选中的，也就是说只有片选信号为预先规定的使能信号时（高电位或低电位），对此芯片的操作才有效。这就允许在同一总线上连接多个SPI设备成为可能。接下来就负责通讯的3根线了。SCLK信号线只由主设备控制，从设备不能控制信号线。SPI是串行通讯协议，数据是一位一位的传输的。由SCLK提供时钟脉冲，SDI，SDO则基于此脉冲完成数据传输。数据输出通过 SDO线，数据在时钟上升沿或下降沿时改变，在紧接着的下降沿或上升沿被读取。完成一位数据传输，输入也使用同样原理。这样，在至少8次时钟信号的改变（上沿和下沿为一次），就可以完成8位数据的传输。
SPI还是一个数据交换协议：因为SPI的数据输入和输出线独立，所以允许同时完成数据的输入和输出。不同的SPI设备的实现方式不尽相同，主要是数据改变和采集的时间不同，在时钟信号上沿或下沿采集有不同定义，具体请参考相关器件的文档。
本实践所设计控制器遵循标准通用的SPI Flash控制协议，可实现多个厂家的SPI Flash device操作，配套的测试扩展板上的DIP 8插座可插上不同厂家的SPI Flash device; 本实例操作的为Winbond公司的W25xx系列，其端口结构如图所示：
...
华邦W25xx系列SPI NOR Flash
W25xx的SPI接口由8个引脚构成：/CS，DO，/WP，GND，VCC，/HOLD，CLK及DIO，其中GND和VCC是电源端，而CLK是整个SPI总线的时钟， DIO是主机的输出，从机的输入，DO 是主机的输入，从机的输出。/CS是从机的选择标志端口，在互相通信的两个SPI总线的器件，/CS 由主机控制，当/CS为低电平时，主机与从机开始交互信息。/WP为FLASH状态保护端口，当/WP为低电平时，FLASH部分状态位无法改变，这样可以间接对FLASH memory中的数据起到保护作用，防止外来数据的写入而造成原有数据的丢失。本实例通过对最基本的Flash 器件和SPI总线协议的研究和实现，设计了SPI Flash Controller, 以此来熟悉IP核的设计和验证。
...
Case download:
spi_flash_axi.zip
1 Design Brief
SPI (Serial Peripheral Interface) serial peripheral device interface bus system is a high-speed, full-duplex, synchronous communication bus, which enables MCU to communicate with various peripheral devices in a serial manner to exchange information. The SPI bus system can directly interface with a variety of standard peripheral devices produced by various manufacturers. It is mainly used between EEPROM, FLASH, real-time clock, AD converter, digital signal processor and digital signal decoder.
The SPI bus system interface signals are as follows:
（1）SDO-Master device data output, slave device data input
（2）SDI – Master device data input, slave device data output
（3）SCLK – Clock signal, generated by the master device
（4）CS-slave device enable signal, controlled by the master device
The communication principle of SPI is simple. It works in a master-slave mode. This mode usually has a master device and one or more slave devices. It requires 4 wires, and only occupies four wires on the pins of the chip, saving the chip's The pins also save space and provide convenience for the layout of the PCB. It is precisely because of this simple and easy-to-use feature that more and more chips are now integrating this communication protocol.
Among them, CS is to control whether the chip is selected, that is to say, only when the chip selection signal is a predetermined enable signal (high potential or low potential), the operation of this chip is effective. This allows multiple SPI devices to be connected on the same bus. The next three lines are responsible for communication. The SCLK signal line is only controlled by the master device, and the slave device cannot control the signal line. SPI is a serial communication protocol, and data is transmitted bit by bit. SCLK provides the clock pulse, and SDI and SDO complete the data transmission based on this pulse. The data output goes through the SDO line, and the data changes on the rising or falling edge of the clock and is read on the following falling or rising edge. To complete a one-bit data transfer, the input also uses the same principle. In this way, at least 8 clock signal changes (upper edge and lower edge is once), you can complete the 8-bit data transmission.
SPI is also a data exchange protocol: because the data input and output lines of the SPI are independent, it is allowed to complete the data input and output at the same time. Different SPI devices have different implementation methods, mainly because the data change and acquisition time are different. There are different definitions for the upper or lower edge of the clock signal. For details, please refer to the relevant device documentation.
The controller designed in this practice follows the standard and universal SPI Flash control protocol, which can realize the operation of SPI Flash device of multiple manufacturers. The DIP 8 socket on the supporting test expansion board can be plugged into the SPI Flash device of different manufacturers; It is the W25xx series of Winbond, and its port structure is shown in the figure:
...
Winbond W25xx series SPI NOR Flash
The SPI interface of W25xx consists of 8 pins: /CS, DO, /WP, GND, VCC, /HOLD, CLK and DIO, where GND and VCC are the power supply terminals, and CLK is the clock of the entire SPI bus, DIO is the host Output, slave input, DO is the master input, slave output. /CS is the selection flag port of the slave. In two SPI bus devices that communicate with each other, /CS is controlled by the master. When /CS is low, the master and the slave start to exchange information. / WP is the FLASH status protection port. When /WP is low, some FLASH status bits cannot be changed, which can indirectly protect the data in the FLASH memory and prevent the loss of original data caused by the writing of external data . In this example, through the research and implementation of the most basic Flash device and SPI bus protocol, the SPI Flash Controller is designed to familiarize with the design and verification of the IP core.
2 Design specifications
l Support AMBA4 AXI(lite) 32 bit Bus interface.
...
l Support software reset.
3 I/O Ports Description
3.1 Global signal
Name | Direction | Width | Description |
SYSCLK | Input | 1 | Global Clock Input 25 -100Mhz |
RST_B | Input | 1 | Global Asynchronous Reset Input Low active. |
3.2 AXI Interface
Name | Direction | Width | Description |
AWVALID | Input | 1 | Write Address Valid This signal indicates that valid write address and control information are available.. |
AWREADY | Output | 1 | Write Address Ready This signal indicates that the slave is ready to accept an address and associated control signals.. |
AWADDR | Input | 32 | Write Address The write address bus gives the address of the first transfer in a writer burst transaction. |
AWPROT | Input | 3 | Protect type This signal indicates the normal, priviledged, or secure protection level of the transaction and whether the transaction. |
WVALID | Input | 1 | Write Valid This signal indicates that valid write data and strobes are available. |
WREADY | Output | 1 | Write Ready This signal indicates that slave can accept the write data. |
WDATA | Input | 32 | Write Data The write data bus is 32 bit wide. |
WSTRB | Input | 4 | Write strobes This signal indicates which bytes lanes to update in memory. |
BVALID | Output | 1 | Write Response Valid This signal indicates that a valid write response is available. |
BREADY | Input | 1 | Write Response Ready This signal indicates that the master can accept the response information. |
BRESP | Output | 2 | Write Response This signal the status of the write transaction. |
ARVALID | Input | 1 | Read Address Valid This signal indicates, when HIGH, that read address and control information is valid and will remain stable until the address acknowledge signal, ARREADY, is high |
ARREADY | Output | 1 | Read Address Ready This siganl indicates that the slave is ready to accept an address and associated control signal. |
ARADDR | Input | 32 | Read Address The read address bus gives the initial address of a read burst transaction. |
ARPORT | Input | 3 | Protect type This signal indicates the normal,priviledged, or secure protetion level of the transaction and whether the transaction is a data access or an instruction access. |
RVALID | Output | 1 | Read Valid This signal indicates that the required read data is available and the read transfer can complete. |
RREADY | Input | 1 | Read Ready This signal indicates that the master can accept the read data and response information. |
RDATA | Output | 32 | Read Data This read data bus is 32 bit wide. |
RRESP | Output | 2 | Read Response This signal indicates the status of the read transaction. |
3.3 SPI Interface
Name | Direction | Width | Description |
SPI_CLK | Output | 1 | SPI Serial Clock Serial Clock for SPI Flash |
SPI_DI | Input | 1 | Serial Data Input Serial Data Output for SPI Flash |
SPI_DO | Output | 1 | Serial Data Input Serial Data Input for SPI Flash |
SPI_CS_B | Output | 1 | SPI Chip Select Chip Enable for SPI Flash.Low active to indicate that the SPI Flash is selected. |
3.4 Interrupt
Name | Direction | Width | Description |
SPI_INT | Output | 1 | SPI Interrupt SPI Flash controller interrupt signal, high active |
4 Registers File
Register Lists
Address | Name | Access | Description |
32'h0 | SPI_CON | RW | SPI Configuration Register . |
32'h4 | SPI_MODE | RW | SPI Mode Configuration Register. |
32'h8 | SPI_CMD | RW | SPI Flash Operation Command and Address. |
32'hc | INT_FLAG | RW | The Interrupt Status Register |
32'h10 | INT_MASK | RW | The Interrupt Mask Register. |
32'h14 | W_DATA | RW | Transfer Data. Data from CPU. |
32'h18 | R_DATA | RW | Receive Data. Data from SPI Flash. |
32'h1c | BYTE_NUM | RW | Indicate Write/Read Bytes. |
4.1 SPI Configuration Register (SPI_CON,ADDR=32'h0)
Default value: 32’h00
Register Bits | Access | Function Description |
0 | STR | Start FLAG High active to indicate start an operation. |
1 | WR | Write/Read FLAG This bit indicate write or read operation. 0: Write Flash; 1: Read Flash; |
2 | RST_SW | Software Reset FLAG High active to indicate software reset Flash. |
31:3 | Reserved | Reserved |
4.2 SPI Mode Configuration Register(SPI_MODE,ADDR=32'h4)
Default value: 32’h0
Register Bits | Access | Function Description |
0 | SPI_MODE | SPI Flash Work Mode This bit indicate the work mode of Flash. 0: mode 0; 1: mode 3; |
2:1 | CLK_MODE | Clock Mode This bits indicate the Clock mode of Flash. 00:1/4 system clock 01:1/8 system clock 10:1/16 system clock 11:Reserved |
31:3 | Reserved | Reserved |
4.3 SPI Flash Command and Address (SPI_CMD,ADDR=32'h8)
Default value: 32’h0
Register Bits | Access | Function Description |
7:0 | CMD | Command Code The SPI Flash control operation code. |
15:8 | ADDR_H | The High 8 bits address The high 8 bits address to indicate the start of W/R into the flash. |
23:16 | ADDR_M | The Middle 8 bits address The middle 8 bits address to indicate the start of W/R into the flash. |
31:24 | ADDR_L | The Low 8 bits address The low 8 bits address to indicate the start of W/R into the flash. |
4.4 Interrupt Status Register (INT_FLAG,ADDR=32'hc)
Default value: 32’h0
Register Bits | Access | Function Description |
0 | CMP_FLAG | Transfer complete Flag, Write 1 Clear High active to indicate transfer complete state. |
1 | T_EMP_FLAG | Transfer FIFO Empty Flag, Write 1 Clear High active to indicate transfer FIFO empty state. |
2 | T_FUL_FLAG | Transfer FIFO Full Flag, Write 1 Clear High active to indicate transfer FIFO full state. |
3 | R_EMP_FLAG | Receive FIFO Empty Flag, Write 1 Clear High active to indicate receive FIFO empty state. |
4 | R_FUL_FLAG | Receive FIFO Full Flag, Write 1 Clear High active to indicate receive FIFO full state. |
31:3 | Reserved | Reserved |
4.5 Interrupt Mask Register (INT_MASK,ADDR=32'h10)
Default value: 32’h0
Register Bits | Access | Function Description |
0 | CMP_MASK | Mask of Transfer complete Flag High active. |
1 | T_EMP_MASK | Mask of Transfer FIFO Empty Flag High active. |
2 | T_FUL_MASK | Mask of Transfer FIFO Full Flag High active. |
3 | R_EMP_MASK | Mask of Receive FIFO Empty Flag High active . |
4 | R_FUL_MASK | Mask of Receive FIFO Full Flag High active. |
30:5 | Reserved | Reserved |
31 | GLO_MASK | Global Mask |
4.6 WRITE DATA (W_DATA,ADDR=32'h14)
Default value: 32’h0
Register Bits | Access | Function Description |
31:0 | W_DATA | Save the Data from CPU 32 bits. |
4.7 Read Data FIFO (R_DATA,ADDR=32'h18)
Default value: 32’h0
Register Bits | Access | Function Description |
31:0 | R_DATA | Save the Data from SPI Flash 32 bits. |
4.8 BYTE _NUM (ADDR=32'h1c)
Default value: 32’h1
Register Bits | Access | Function Description |
15:0 | BYTE_NUM | BYTE COUNT Indicate the bytes of data R/W. |
31:16 | Reserved | Reserved |
5 Functional Description
5.1 SPI Flash Controller Block Diagram
The FSM is used to control and harmonize the whole system. Master configures the necessary information to the controller through AXI Bus
...
Interface : Translate the logic
5.2 Internal FSM
...
Current State | Function | Next Status | Jump Condition |
IDLE | Wait start signal | T_CMD | STR = 1 |
IDLE | STR = 0 or Reset not end | ||
T_CMD | Transfer Command | T_ADDR_H | T_count = 8 |
T_DATA | The command is 9FH | ||
IDLE | The commnd is 06H|04H| C7H/60H | ||
T_ADDR_H | Transfer the address high 8 bits. | T_ADDR_M | T_count = 8 |
T_ADDR_M | Transfer the address middle 8 bits. | T_ADDR_L | T_count = 8 |
T_ADDR_L | Transfer the address low 8 bits | IDLE | CMD is D8H|52H|20H |
T_DATA | T_count = 8 | ||
T_DATA | Transfer data | T_DATA | Transfer data not end |
IDLE | Transfer data end |
5.3 FIFO
FIFO is important to this design as all data are transferred by it. Following is the 2-pointer FIFO.
...
When FIFO is full/empty but still write/read, FIFO will overflow/underflow.
5.4 Polling Status and Interrupt
The design provide programmable interrupt output and polling the interrupt flag through INT_FLAG. SPI_INT will be high when interrupt happens.
...
Interrupt source | Description | Mask bit |
CMP_FLAG | Transfer Complete | 0 |
T_EMP_FLAG | Transfer FIFO Empty Flag | 1 |
T_FUL_FLAG | Transfer FIFO Full Flag | 2 |
R_EMP_FLAG | Receive FIFO Empty Flag | 3 |
R_FUL_FLAG | Receive FIFO Full Flag | 4 |
6 Timing Figures
6.1 AXI Bus Write
...
6.2 AXI Bus Read
...
6.3 SPI Bus Write
...
6.4 SPI Bus Read
...
6.5 SPI Clock
...
6.6 Parallel to Serial
...
6.7 Serial to Parallel
...
7 SOC 整合实现
7.1 SPI FLASH 控制器IP设计实验项目的硬件平台实现
SPI FLASH控制器IP核设计是AMBA AXI slave 32bit总线接口，而我们FBIO Wrapper是AMBA AXI 64bit总线接口, 不能直接连接在一起，需要一个axi64_to_axi32的Bridge进行连接，如下；如下图所示：
...
本实验以Plus1 7021实践平台配套的FPGA子板和扩展测试板完成相关实验，FPGA子板的开发工具采用XILINX的Vivado集成开发环境(版本号为2018.3);为了方便将用户自己需要验证的IP方便连接到SOC系统中验证，本实验提供了相应的设计参考基础文件，如下
...
设计案例与SP7021主板与FPGA子板脚位对应连接关系如下表所示：
...
6.5 SPI Clock
...
6.6 Parallel to Serial
...
6.7 Serial to Parallel
...
7 SOC integration
7.1 Implementation of hardware platform for SPI FLASH controller IP design experiment project
The SPI FLASH controller IP core design is the AMBA AXI slave 32bit bus interface, We choose axi_ bus_ m32_bridge module from Bus Bridge series ,so the AXI master bus interface provided by the bus bride module is used to connect our IP as follows :
...
This experiment uses the FPGA daughter board and extended test board supporting the SP7021 practice platform to complete the relevant experiments. The development tool of the FPGA daughter board uses the XILINX Vivado integrated development environment (version number 2018.3); in order to facilitate the convenience of the user to verify the IP Connected to the SOC system to verify, this experiment provides the corresponding design reference basic file, as follows
...
The corresponding connection between the design case and the pin connection of the SP7021 motherboard and FPGA daughter board is shown in the following table: 1: U20B on the main board is connected to J2 of the FPGA daughter board (Pin pin corresponding, such as 1-51 ...), 提供主板上的Plus1 主芯片与FPGA的数据传输通道
...
providing the data transmission channel between the Plus1 main chip on the main board and the FPGA
...
Design Demo | FPGA子板 | SP7021主板FPGA daughter board | SP7021 mother board | |||||
spi_flash_axi | J2 | U1E | U20B | |||||
Top Port Name | Schematic Name | FPGA I/O | Schematic Name | |||||
| 1 | GND |
| 51 | GND | |||
| 2 | GND |
| 52 | GND | |||
FPGA_PAD[0] | 3 | B34_L24_N | T8 | 53 | FBIO_PAD_0 | |||
FPGA_PAD[43] | 4 | B34_L24_P | R8 | 54 | FBIO_PAD_1 | |||
| 5 | VIN |
| 55 | VCC(3.3V) | |||
| 6 | VCCIO34 |
| 56 | VCC(3.3V) | |||
FPGA_PAD[1] | 7 | B34_L21_N | V9 | 57 | FBIO_PAD_2 | |||
FPGA_PAD[42] | 8 | B34_L21_P | U9 | 58 | FBIO_PAD_3 | |||
FPGA_PAD[2] | 9 | B34_L18_N | N6 | 59 | FBIO_PAD_4 | |||
FPGA_PAD[41] | 10 | B34_L18_P | M6 | 60 | FBIO_PAD_5 | |||
FPGA_PAD[3] | 11 | B34_L22_N | U6 | 61 | FBIO_PAD_6 | |||
FPGA_PAD[40] | 12 | B34_L22_P | U7 | 62 | FBIO_PAD_7 | |||
FPGA_PAD[4] | 13 | B34_L20_N | V6 | 63 | FBIO_PAD_8 | |||
FPGA_PAD[39] | 14 | B34_L20_P | V7 | 64 | FBIO_PAD_9 | |||
FPGA_PAD[5] | 15 | B34_L23_N | T6 | 65 | FBIO_PAD_10 | |||
FPGA_PAD[38] | 16 | B34_L23_P | R7 | 66 | FBIO_PAD_11 | |||
FPGA_PAD[6] | 17 | B34_L10_N | V4 | 67 | FBIO_PAD_12 | |||
FPGA_PAD[37] | 18 | B34_L10_P | V5 | 68 | FBIO_PAD_13 | |||
FPGA_PAD[7] | 19 | B34_L19_P | R6 | 69 | FBIO_PAD_14 | |||
FPGA_PAD[36] | 20 | B34_L19_N | R5 | 70 | FBIO_PAD_15 | |||
FPGA_PAD[8] | 21 | B34_L8_P | U4 | 71 | FBIO_PAD_16 | |||
FPGA_PAD[35] | 22 | B34_L8_N | U3 | 72 | FBIO_TCLK | |||
FPGA_PAD[9] | 23 | B34_L9_N | V2 | 73 | FBIO_RCLK | |||
FPGA_PAD[34] | 24 | B34_L9_P | U2 | 74 | FBIO_PAD_17 | |||
FPGA_PAD[10] | 25 | B34_L7_N | V1 | 75 | FBIO_PAD_18 | |||
FPGA_PAD[33] | 26 | B34_L7_P | U1 | 76 | FBIO_PAD_19 | |||
FPGA_PAD[11] | 27 | B34_L13_P | N5 | 77 | FBIO_PAD_20 | |||
FPGA_PAD[32] | 28 | B34_L13_N | P5 | 78 | FBIO_PAD_21 | |||
FPGA_PAD[12] | 29 | B34_L12_P | T5 | 79 | FBIO_PAD_22 | |||
FPGA_PAD[31] | 30 | B34_L12_N | T4 | 80 | FBIO_PAD_23 | |||
FPGA_PAD[13] | 31 | B34_L11_N | T3 | 81 | FBIO_PAD_24 | |||
FPGA_PAD[30] | 32 | B34_L11_P | R3 | 82 | FBIO_PAD_25 | |||
FPGA_PAD[29] | 33 | B34_L14_P | P4 | 83 | FBIO_PAD_26 | |||
FPGA_PAD[28] | 34 | B34_L14_N | P3 | 84 | FBIO_PAD_27 | |||
FPGA_PAD[14] | 35 | B34_L16_N | N4 | 85 | FBIO_PAD_28 | |||
FPGA_PAD[27] | 36 | B34_L16_P | M4 | 86 | FBIO_PAD_29 | |||
FPGA_PAD[15] | 37 | B34_L17_N | T1 | 87 | FBIO_PAD_30 | |||
FPGA_PAD[26] | 38 | B34_L17_P | R1 | 88 | FBIO_PAD_31 | |||
FPGA_PAD[16] | 39 | B34_L15_N | R2 | 89 | FBIO_PAD_32 | |||
FPGA_PAD[25] | 40 | B34_L15_P | P2 | 90 | FBIO_PAD_33 | |||
FPGA_PAD[17] | 41 | B34_L3_N | N1 | 91 | FBIO_PAD_34 | |||
FPGA_PAD[24] | 42 | B34_L3_P | N2 | 92 | FBIO_PAD_35 | |||
FPGA_PAD[18] | 43 | B34_L1_N | M1 | 93 | FBIO_PAD_RSTB | |||
FPGA_PAD[23] | 44 | B34_L1_P | L1 | 94 | EXT0_INT | |||
| 45 | VCCIO34 |
| 95 | VCC(3.3V) | |||
| 46 | VIN |
| 96 | VCC(3.3V) | |||
FPGA_PAD[19] | 47 | B34_L4_P | M3 | 97 | EXT1_INT | |||
FPGA_PAD[20] | 48 | B34_L4_N | M2 | 98 |
| |||
| 49 | GND |
| 99 | GND | |||
| 50 | GND |
| 100 | GND | |||
2: 主板上的U20A接FPGA子板的J1(Pin脚以一对应，如 U20A on the motherboard is connected to J1 of the FPGA daughter board (Pin pins correspond to one, such as 1-1 ...)，经由J17将FPGA Bank 35的42 , and the 42 pin IO (3.3v) 扩展出来，供用户使用;本实验案例中接测试扩展板的J2(Pin脚以一对应，如 of FPGA Bank 35 is extended via J17 for users to use; The test case is connected to J2 of the test expansion board (Pin pins correspond to one, such as 1-1 ...), 提供FPGA的IO扩展
...
providing FPGA IO expansion
...
Design Demo | FPGA子板 | SP7021主板 | 测试扩展板FPGA daughter board | SP7021 mother board | Test expansion board | |||||||||||
spi_flash_axi | J1 | U1F | U20A | J17 | J2 | |||||||||||
Top Port Name | Schematic Name | FPGA I/O | Schematic Name | Schematic Name | Schematic Name | |||||||||||
| 1 | GND |
| 1 | GND | 3 | GND | 3 | GND | |||||||
| 2 | GND |
| 2 | GND | 4 | GND | 4 | GND | |||||||
| 3 | B35_L23_N | K1 | 3 | B35_L23_N | 5 | B35_L23_N | 5 | PMOD8 | |||||||
| 4 | B35_L23_P | K2 | 4 | B35_L23_P | 6 | B35_L23_P | 6 | PMOD7 | |||||||
| 5 | VIN |
| 5 | VIN | 1 | VCC | 1 | VCC | |||||||
| 6 | VCCIO35 |
| 6 | VCCIO35 | 2 | VCC | 2 | VCC | |||||||
| 7 | B35_L15_N | G2 | 7 | B35_L15_N | 7 | B35_L15_N | 7 | PMOD6 | |||||||
| 8 | B35_L15_P | H2 | 8 | B35_L15_P | 8 | B35_L15_P | 8 | PMOD5 | |||||||
| 9 | B35_L13_N | F3 | 9 | B35_L13_N | 9 | B35_L13_N | 9 | PMOD4 | |||||||
| 10 | B35_L13_P | F4 | 10 | B35_L13_P | 10 | B35_L13_P | 10 | PMOD3 | |||||||
| 11 | B35_L12_N | D3 | 11 | B35_L12_N | 11 | B35_L12_N | 11 | LED_D1PMOD1 | |||||||
| 12 | B35_L12_P | E3 | 12 | B35_L12_P | 12 | B35_L12_P | 12PMOD1 | LED_D1 | |||||||
| 13 | B35_L22_P | J3 | 13 | B35_L22_P | 13 | B35_L22_P | 13 | LED_D2 | |||||||
| 14 | B35_L22_N | J2 | 14 | B35_L22_N | 14 | B35_L22_N | 14 | PMOD2 | |||||||
| 15 | B35_L17_N | G1 | 15 | B35_L17_N | 15 | B35_L17_N | 15 | LED_D3 | |||||||
| 16 | B35_L17_P | H1 | 16 | B35_L17_P | 16 | B35_L17_P | 16 | LED_D4 | |||||||
| 17 | B35_L18_N | E1 | 17 | B35_L18_N | 17 | B35_L18_N | 17 | LED_D5 | |||||||
| 18 | B35_L18_P | F1 | 18 | B35_L18_P | 18 | B35_L18_P | 18 | LED_D6 | |||||||
| 19 | B35_L14_N | D2 | 19 | B35_L14_N | 19 | B35_L14_N | 19 | LED_D7 | |||||||
| 20 | B35_L14_P | E2 | 20 | B35_L14_P | 20 | B35_L14_P | 20 | LED_D8 | |||||||
| 21 | B35_L16_P | C2 | 21 | B35_L16_P | 21 | B35_L16_P | 21 | SPI_WP | |||||||
FPGA_SPI_DI | 22 | B35_L16_N | C1 | 22 | B35_L16_N | 22 | B35_L16_N | 22 | SPI_DO | |||||||
FPGA_SPI_CS_B | 23 | B35_L9_N | A1 | 23 | B35_L9_N | 23 | B35_L9_N | 23 | SPI_CS | |||||||
| 24 | B35_L9_P | B1 | 24 | B35_L9_P | 24 | B35_L9_P | 24 | SPI_HOLD | |||||||
FPGA_SPI_CLK | 25 | B35_L10_P | B3 | 25 | B35_L10_P | 25 | B35_L10_P | 25 | SPI_CLK | |||||||
FPGA_SPI_DO | 26 | B35_L10_N | B2 | 26 | B35_L10_N | 26 | B35_L10_N | 26 | SPI_DI | |||||||
| 27 | B35_L8_N | A3 | 27 | B35_L8_N | 27 | B35_L8_N | 27 | U1-1 | |||||||
| 28 | B35_L8_P | A4 | 28 | B35_L8_P | 28 | B35_L8_P | 28 | U2-1 | |||||||
| 29 | B35_L11_N | D4 | 29 | B35_L11_N | 29 | B35_L11_N | 29 | U3-1 | |||||||
| 30 | B35_L11_P | D5 | 30 | B35_L11_P | 30 | B35_L11_P | 30 | U4-1 | |||||||
| 31 | B35_L3_N | A5 | 31 | B35_L3_N | 31 | B35_L3_N | 31 | LED-B | |||||||
| 32 | B35_L3_P | A6 | 32 | B35_L3_P | 32 | B35_L3_P | 32 | LED-F | |||||||
| 33 | B35_L2_N | B6 | 33 | B35_L2_N | 33 | B35_L2_N | 33 | LED-A | |||||||
| 34 | B35_L2_P | B7 | 34 | B35_L2_P | 34 | B35_L2_P | 34 | LED-E | |||||||
| 35 | B35_L7_N | B4 | 35 | B35_L7_N | 35 | B35_L7_N | 35 | LED-D | |||||||
| 36 | B35_L7_P | C4 | 36 | B35_L7_P | 36 | B35_L7_P | 36 | LED-RA | |||||||
| 37 | B35_L1_N | C5 | 37 | B35_L1_N | 37 | B35_L1_N | 37 | LED-C | |||||||
| 38 | B35_L1_P | C6 | 38 | B35_L1_P | 38 | B35_L1_P | 38 | LED-G | |||||||
| 39 | B35_L5_N | E5 | 39 | B35_L5_N | 39 | B35_L5_N | 39 | GND | |||||||
| 40 | B35_L5_P | E6 | 40 | B35_L5_P | 40 | B35_L5_P | 40 | GND | |||||||
| 41 | B35_L6_N | D7 | 41 | B35_L6_N | 41 | B35_L6_N |
|
| |||||||
| 42 | B35_L6_P | E7 | 42 | B35_L6_P | 42 | B35_L6_P |
|
| |||||||
| 43 | B35_L19_P | G6 | 43 | B35_L19_P | 43 | B35_L19_P |
|
| |||||||
| 44 | B35_L19_N | F6 | 44 | B35_L19_N | 44 | B35_L19_N |
|
| |||||||
| 45 | VCCIO35 |
| 45 | VCCIO35 | 49 | VCC |
|
| |||||||
| 46 | VIN |
| 46 | VIN | 50 | VCC |
|
| |||||||
| 47 | B35_L4_N | C7 | 47 | B35_L4_N | 45 | B35_L4_N |
|
| |||||||
| 48 | B35_L4_P | D8 | 48 | B35_L4_P | 46 | B35_L4_P |
|
| |||||||
| 49 | GND |
| 49 | GND | 47 | GND |
|
| |||||||
| 50 | GND |
| 50 | GND |
|
|
|
| |||||||
7.2 SPI FLASH 控制器IP设计实验项目的系统软件平台实现
在IDE 环境中如下图所示，选择sp7021工程名，单击鼠标右键在弹出的菜单中选Copy
...
接下来再次选择sp7021工程名
...
单击鼠标右键在弹出的菜单中选Paste,出现下图
...
在Project name框中填写spi_flash_axi,完成spi_flash_axi 工程名及目录建立，如下图所示
...
50 | GND | 48 | GND |
|
|
7.2 Implementation of System Software Platform for SPI FLASH Controller IP Design Experiment Project
In the IDE environment, as shown below, select the sp7021 project name, click the right mouse button and select Copy in the pop-up menu
...
Next, select the sp7021 project name again
...
Click the right mouse button and select Paste in the pop-up menu, the following picture appears
...
Fill in spi_flash_axi in the Project name box to complete the spi_flash_axi project name and directory creation, as shown below
...
Next, you need to copy all the files and folders under the installation directory \SP7021\example\ spi_flash_axi to the spi_flash_axi project directory built above (the path is: installation directory\SP7021\ workspace\spi_flash_axi\). The program codes main.c; spi.c; and spi.h required for the Flash controller IP design practice are placed in the following paths:
1） \SP7021\workspace\spi_flash_axi\),同名文件选择覆盖，这样SPI Flash控制器 IP设计实践所需的程序代码main.c；spi.c；spi.h分别放到如下的路径中:1） 安装目录 main.c
2） \SP7021\workspace\spi_flash_axi\ 文件夹下的maintestapi\util\spi.c2） 安装目录
3） \SP7021\workspace\spi_flash_axi\testapiinclude\util 文件夹下的spi\spi.c
3） 安装目录 \SP7021\workspace\ spi_flash_axi \ include\util文件夹下的spi.h
最后按下图所示，鼠标选中红框1，接着点击鼠标右键出现下拉菜单，然后选中红框2，对刚才复制动作做刷新，这样刚才复制的文件就能在IDE环境中显示出来
h
Finally, as shown in the figure below, clicks the mouse selects the red box 1, then clicks the right mouse button to appear the drop-down menu, and then selects the red box 2, refresh the copy action just now, so that the file just copied can be displayed in the IDE environment
...
main.c
void operation_done()
void flash_device_write_en()
void flash_device_done()
void spi_read_id()
void spi_write_data()
void spi_read_data()
int main(void)
{
printf("Build @%s, %s\n", __DATE__, __TIME__);
hw_init();
sys_init();
pinfbio_muxinit();
disp_hdmi_init();
sp_interrupt_setup(); /* interrupt manager module init */
spi_read_id();
spi_write_data();
spi_read_data();
printf("%s:%5d\n", __FUNCTION__,__LINE__);
while(1);
}对比数码管控制IP实验，增加了spi flash操作控制相关的函数，用来完成对spi flash读写及擦除操作，如下讲解。
Compared with the IP experiment of nixie tube control, spi flash operation control related functions are added to complete the read and write and erase operations of spi flash.
void spi_read_id()
{
spi_reg->SPI_CMD=0x9f;
spi_reg->SPI_CON=0x3;
operation_done();
temp=spi_reg->R_DATA;
printf("@spi @spi flash device id [%x]\n", temp);
}实现读取flash
JEDEC ID的操作，如下：The operation to read the flash JEDEC ID is as follows:
spi_reg->SPI_CMD=0x9f; 设置读JEDEC ID的命令码9f Set the command code 9f to read JEDEC ID;
spi_reg->SPI_CON=0x3;启动读JEDEC ID的操作；Start reading JEDEC ID operation;
operation_done(); 等待本次操作完成； Wait for this operation to complete;
temp=spi_reg->R_DATA; 从RX FIFO里取出读JEDEC ID操作完成后的结果，并打印出； Take out the result after reading JEDEC ID operation from RX FIFO and print it out;
void spi_write_data()
{
/////////sector erase///////////////
flash_device_write_en();
spi_reg->SPI_CMD=0x3020;
spi_reg->SPI_CON=0x1;
operation_done();
flash_device_done();
//////////write data///////////////////////////
flash_device_write_en();
spi_reg->BYTE_NUM=0x8;
spi_reg->W_DATA =0x12345678;
spi_reg->W_DATA =0xabcdef91;
spi_reg->SPI_CMD=0x3002;
spi_reg->SPI_CON=0x1;
operation_done();
flash_device_done();
}
实现写数据到flash device的操作，写数据操作必须先对存储数据的地址空间做擦除，然后才能写入数据，如下;
}
To realize the operation of writing data to the flash device, the write data operation must first erase the address space of the stored data before writing the data, as follows:
flash_device_write_en(); 对flash 的擦除，写操作之前必需写使能，通过设置命令码06实现；For erasing flash, it must be enabled before writing, which is achieved by setting command code 06;
spi_reg->SPI_CMD=0x3020; 擦除flash 从0x300000地址开始的4k byte空间，通过设置命令码20实现 Erase flash 4k byte space starting from address 0x300000, realized by setting command code 20
flash_device_done();等待擦除flash 从0x300000地址开始的4k byte空间，直到操作完成； Wait to erase the 4k byte space starting from address 0x300000 until the operation is completed
spi_reg->BYTE_NUM=0x8;设置写数据到flash device的数目，共8byte_NUM=0x8; Set the number of write data to flash device, a total of 8byte;
spi_reg->W_DATA =0x12345678; spi_reg->W_DATA =0xabcdef91;
设置需要写到flash device的数据Set the data to be written to the flash device
spi_reg->SPI_CMD=0x3002; 设置flash 从0x300000地址开始的4k byte空间为写数据空间；通过设置命令码02实现Set the 4k byte space of flash starting at address 0x300000 as the write data space; realize it by setting the command code 02
spi_reg->SPI_CON=0x1; 使能写数据操作； Enable write data operation;
operation_done();
flash_device_done();等待写8byte数据到flash device,直到操作完成
Wait to write 8byte data to flash device until the operation is completed
void spi_read_data()
{
spi_reg->BYTE_NUM=0x8;
spi_reg->SPI_CMD=0x3003;
spi_reg->SPI_CON=0x3;
operation_done();
temp= spi_reg->R_DATA;
printf("Read SPI Flash: [%x]\n", temp);
temp= spi_reg->R_DATA;
printf("Read SPI Flash: [%x]\n", temp);
}
spi_reg->BYTE_NUM=0x8; 设置从flash device读数据的数目，共8byte_NUM=0x8; Set the total number of data read from the flash device 8byte;
spi_reg->SPI_CMD=0x3003; 设置flash 从0x300000地址开始读数据，通过设置命令码03实现Set flash to read data from address 0x300000, which is realized by setting command code 03
spi_reg->SPI_CON=0x3; 使能读数据操作；Enable read data operation;
operation_done(); 等待从flash device读8byte数据,直到操作完成
程序代码运行
在Plus1 IDE环境中compile后，下载到平台，在terminal窗口看到如下信息Wait to read 8byte data from flash device until the operation is completed
7.3 Run Program code
After compile in the Plus1 IDE environment, download to the platform and see the following information in the terminal window
...