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Case download:
spi_flash_axi.zip

1 Design Brief

SPI (Serial Peripheral Interface) serial peripheral device interface bus system is a high-speed, full-duplex, synchronous communication bus, which enables MCU to communicate with various peripheral devices in a serial manner to exchange information. The SPI bus system can directly interface with a variety of standard peripheral devices produced by various manufacturers. It is mainly used between EEPROM, FLASH, real-time clock, AD converter, digital signal processor and digital signal decoder.

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The SPI interface of W25xx consists of 8 pins: /CS, DO, /WP, GND, VCC, /HOLD, CLK and DIO, where GND and VCC are the power supply terminals, and CLK is the clock of the entire SPI bus, DIO is the host Output, slave input, DO is the master input, slave output. /CS is the selection flag port of the slave. In two SPI bus devices that communicate with each other, /CS is controlled by the master. When /CS is low, the master and the slave start to exchange information. / WP is the FLASH status protection port. When /WP is low, some FLASH status bits cannot be changed, which can indirectly protect the data in the FLASH memory and prevent the loss of original data caused by the writing of external data . In this example, through the research and implementation of the most basic Flash device and SPI bus protocol, the SPI Flash Controller is designed to familiarize with the design and verification of the IP core.

2 Design specifications

l Support AMBA4 AXI(lite) 32 bit Bus interface.

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l Support software reset.

3 I/O Ports Description

3.1 Global signal

Name

Direction

Width

Description

SYSCLK

Input

1

Global Clock Input

25 -100Mhz

RST_B

Input

1

Global Asynchronous Reset Input

Low active.

3.2 AXI Interface

Name	Direction	Width	Description
AWVALID	Input	1	Write Address Valid This signal indicates that valid write address and control information are available..
AWREADY	Output	1	Write Address Ready This signal indicates that the slave is ready to accept an address and associated control signals..
AWADDR	Input	32	Write Address The write address bus gives the address of the first transfer in a writer burst transaction.
AWPROT	Input	3	Protect type This signal indicates the normal, priviledged, or secure protection level of the transaction and whether the transaction.
WVALID	Input	1	Write Valid This signal indicates that valid write data and strobes are available.
WREADY	Output	1	Write Ready This signal indicates that slave can accept the write data.
WDATA	Input	32	Write Data The write data bus is 32 bit wide.
WSTRB	Input	4	Write strobes This signal indicates which bytes lanes to update in memory.
BVALID	Output	1	Write Response Valid This signal indicates that a valid write response is available.
BREADY	Input	1	Write Response Ready This signal indicates that the master can accept the response information.
BRESP	Output	2	Write Response This signal the status of the write transaction.
ARVALID	Input	1	Read Address Valid This signal indicates, when HIGH, that read address and control information is valid and will remain stable until the address acknowledge signal, ARREADY, is high
ARREADY	Output	1	Read Address Ready This siganl indicates that the slave is ready to accept an address and associated control signal.
ARADDR	Input	32	Read Address The read address bus gives the initial address of a read burst transaction.
ARPORT	Input	3	Protect type This signal indicates the normal,priviledged, or secure protetion level of the transaction and whether the transaction is a data access or an instruction access.
RVALID	Output	1	Read Valid This signal indicates that the required read data is available and the read transfer can complete.
RREADY	Input	1	Read Ready This signal indicates that the master can accept the read data and response information.
RDATA	Output	32	Read Data This read data bus is 32 bit wide.
RRESP	Output	2	Read Response This signal indicates the status of the read transaction.

3.3 SPI Interface

Name	Direction	Width	Description
SPI_CLK	Output	1	SPI Serial Clock Serial Clock for SPI Flash
SPI_DI	Input	1	Serial Data Input Serial Data Output for SPI Flash
SPI_DO	Output	1	Serial Data Input Serial Data Input for SPI Flash
SPI_CS_B	Output	1	SPI Chip Select Chip Enable for SPI Flash.Low active to indicate that the SPI Flash is selected.

3.4 Interrupt

Name

Direction

Width

Description

SPI_INT

Output

1

SPI Interrupt

SPI Flash controller interrupt signal, high active

4 Registers File

Register Lists

Address	Name	Access	Description
32'h0	SPI_CON	RW	SPI Configuration Register .
32'h4	SPI_MODE	RW	SPI Mode Configuration Register.
32'h8	SPI_CMD	RW	SPI Flash Operation Command and Address.
32'hc	INT_FLAG	RW	The Interrupt Status Register
32'h10	INT_MASK	RW	The Interrupt Mask Register.
32'h14	W_DATA	RW	Transfer Data. Data from CPU.
32'h18	R_DATA	RW	Receive Data. Data from SPI Flash.
32'h1c	BYTE_NUM	RW	Indicate Write/Read Bytes.

4.1 SPI Configuration Register (SPI_CON,ADDR=32'h0)

Default value: 32’h00

Register Bits	Access	Function Description
0	STR	Start FLAG High active to indicate start an operation.
1	WR	Write/Read FLAG This bit indicate write or read operation. 0: Write Flash; 1: Read Flash;
2	RST_SW	Software Reset FLAG High active to indicate software reset Flash.
31:3	Reserved	Reserved

4.2 SPI Mode Configuration Register(SPI_MODE,ADDR=32'h4)

Default value: 32’h0

Register Bits	Access	Function Description
0	SPI_MODE	SPI Flash Work Mode This bit indicate the work mode of Flash. 0: mode 0; 1: mode 3;
2:1	CLK_MODE	Clock Mode This bits indicate the Clock mode of Flash. 00:1/4 system clock 01:1/8 system clock 10:1/16 system clock 11:Reserved
31:3	Reserved	Reserved

4.3 SPI Flash Command and Address (SPI_CMD,ADDR=32'h8)

Default value: 32’h0

Register Bits	Access	Function Description
7:0	CMD	Command Code The SPI Flash control operation code.
15:8	ADDR_H	The High 8 bits address The high 8 bits address to indicate the start of W/R into the flash.
23:16	ADDR_M	The Middle 8 bits address The middle 8 bits address to indicate the start of W/R into the flash.
31:24	ADDR_L	The Low 8 bits address The low 8 bits address to indicate the start of W/R into the flash.

4.4 Interrupt Status Register (INT_FLAG,ADDR=32'hc)

Default value: 32’h0

Register Bits	Access	Function Description
0	CMP_FLAG	Transfer complete Flag, Write 1 Clear High active to indicate transfer complete state.
1	T_EMP_FLAG	Transfer FIFO Empty Flag, Write 1 Clear High active to indicate transfer FIFO empty state.
2	T_FUL_FLAG	Transfer FIFO Full Flag, Write 1 Clear High active to indicate transfer FIFO full state.
3	R_EMP_FLAG	Receive FIFO Empty Flag, Write 1 Clear High active to indicate receive FIFO empty state.
4	R_FUL_FLAG	Receive FIFO Full Flag, Write 1 Clear High active to indicate receive FIFO full state.
31:3	Reserved	Reserved

4.5 Interrupt Mask Register (INT_MASK,ADDR=32'h10)

Default value: 32’h0

Register Bits	Access	Function Description
0	CMP_MASK	Mask of Transfer complete Flag High active.
1	T_EMP_MASK	Mask of Transfer FIFO Empty Flag High active.
2	T_FUL_MASK	Mask of Transfer FIFO Full Flag High active.
3	R_EMP_MASK	Mask of Receive FIFO Empty Flag High active .
4	R_FUL_MASK	Mask of Receive FIFO Full Flag High active.
30:5	Reserved	Reserved
31	GLO_MASK	Global Mask

4.6 WRITE DATA (W_DATA,ADDR=32'h14)

Default value: 32’h0

Register Bits

Access

Function Description

31:0

W_DATA

Save the Data from CPU

32 bits.

4.7 Read Data FIFO (R_DATA,ADDR=32'h18)

Default value: 32’h0

Register Bits

Access

Function Description

31:0

R_DATA

Save the Data from SPI Flash

32 bits.

4.8 BYTE _NUM (ADDR=32'h1c)

Default value: 32’h1

Register Bits

Access

Function Description

15:0

BYTE_NUM

BYTE COUNT

Indicate the bytes of data R/W.

31:16

Reserved

5 Functional Description

5.1 SPI Flash Controller Block Diagram

The FSM is used to control and harmonize the whole system. Master configures the necessary information to the controller through AXI Bus

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Interface : Translate the logic

5.2 Internal FSM

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Current State	Function	Next Status	Jump Condition
IDLE	Wait start signal	T_CMD	STR = 1
IDLE	Wait start signal	IDLE	STR = 0 or Reset not end
T_CMD	Transfer Command	T_ADDR_H	T_count = 8
		T_DATA	The command is 9FH
		IDLE	The commnd is 06H\|04H\| C7H/60H
T_ADDR_H	Transfer the address high 8 bits.	T_ADDR_M	T_count = 8
T_ADDR_M	Transfer the address middle 8 bits.	T_ADDR_L	T_count = 8
T_ADDR_L	Transfer the address low 8 bits	IDLE	CMD is D8H\|52H\|20H
T_ADDR_L	Transfer the address low 8 bits	T_DATA	T_count = 8
T_DATA	Transfer data	T_DATA	Transfer data not end
T_DATA	Transfer data	IDLE	Transfer data end

5.3 FIFO

FIFO is important to this design as all data are transferred by it. Following is the 2-pointer FIFO.

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When FIFO is full/empty but still write/read, FIFO will overflow/underflow.

5.4 Polling Status and Interrupt

The design provide programmable interrupt output and polling the interrupt flag through INT_FLAG. SPI_INT will be high when interrupt happens.

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Interrupt source	Description	Mask bit
CMP_FLAG	Transfer Complete	0
T_EMP_FLAG	Transfer FIFO Empty Flag	1
T_FUL_FLAG	Transfer FIFO Full Flag	2
R_EMP_FLAG	Receive FIFO Empty Flag	3
R_FUL_FLAG	Receive FIFO Full Flag	4

6 Timing Figures

6.1 AXI Bus Write

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6.2 AXI Bus Read

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6.3 SPI Bus Write

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6.4 SPI Bus Read

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6.5 SPI Clock

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6.6 Parallel to Serial

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6.7 Serial to Parallel

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7 SOC integration

7.1 Implementation of hardware platform for SPI FLASH controller IP design experiment project

The SPI FLASH controller IP core design is the AMBA AXI slave 32bit bus interface, and our FBIO Wrapper is the AMBA AXI 64bit bus interface. They cannot be directly connected together. A bridge of axi64_to_axi32 is required for connection We choose axi_ bus_ m32_bridge module from Bus Bridge series ,so the AXI master bus interface provided by the bus bride module is used to connect our IP as follows :

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This experiment uses the FPGA daughter board and extended test board supporting the Plus1 7021 SP7021 practice platform to complete the relevant experiments. The development tool of the FPGA daughter board uses the XILINX Vivado integrated development environment (version number 2018.3); in order to facilitate the convenience of the user to verify the IP Connected to the SOC system to verify, this experiment provides the corresponding design reference basic file, as follows

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The corresponding connection between the design case and the pin connection of the SP7021 motherboard and FPGA daughter board is shown in the following table: 1: U20B on the main board is connected to J2 of the FPGA daughter board (Pin pin corresponding, such as 1-51 ...), providing the data transmission channel between the Plus1 main chip on the main board and the FPGAImage Removed

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Design Demo	FPGA daughter board			SP7021 mother board
spi_flash_axi	J2		U1E	U20B
Top Port Name	Schematic Name		FPGA I/O	Schematic Name
	1	GND		51	GND
	2	GND		52	GND
FPGA_PAD[0]	3	B34_L24_N	T8	53	FBIO_PAD_0
FPGA_PAD[43]	4	B34_L24_P	R8	54	FBIO_PAD_1
	5	VIN		55	VCC(3.3V)
	6	VCCIO34		56	VCC(3.3V)
FPGA_PAD[1]	7	B34_L21_N	V9	57	FBIO_PAD_2
FPGA_PAD[42]	8	B34_L21_P	U9	58	FBIO_PAD_3
FPGA_PAD[2]	9	B34_L18_N	N6	59	FBIO_PAD_4
FPGA_PAD[41]	10	B34_L18_P	M6	60	FBIO_PAD_5
FPGA_PAD[3]	11	B34_L22_N	U6	61	FBIO_PAD_6
FPGA_PAD[40]	12	B34_L22_P	U7	62	FBIO_PAD_7
FPGA_PAD[4]	13	B34_L20_N	V6	63	FBIO_PAD_8
FPGA_PAD[39]	14	B34_L20_P	V7	64	FBIO_PAD_9
FPGA_PAD[5]	15	B34_L23_N	T6	65	FBIO_PAD_10
FPGA_PAD[38]	16	B34_L23_P	R7	66	FBIO_PAD_11
FPGA_PAD[6]	17	B34_L10_N	V4	67	FBIO_PAD_12
FPGA_PAD[37]	18	B34_L10_P	V5	68	FBIO_PAD_13
FPGA_PAD[7]	19	B34_L19_P	R6	69	FBIO_PAD_14
FPGA_PAD[36]	20	B34_L19_N	R5	70	FBIO_PAD_15
FPGA_PAD[8]	21	B34_L8_P	U4	71	FBIO_PAD_16
FPGA_PAD[35]	22	B34_L8_N	U3	72	FBIO_TCLK
FPGA_PAD[9]	23	B34_L9_N	V2	73	FBIO_RCLK
FPGA_PAD[34]	24	B34_L9_P	U2	74	FBIO_PAD_17
FPGA_PAD[10]	25	B34_L7_N	V1	75	FBIO_PAD_18
FPGA_PAD[33]	26	B34_L7_P	U1	76	FBIO_PAD_19
FPGA_PAD[11]	27	B34_L13_P	N5	77	FBIO_PAD_20
FPGA_PAD[32]	28	B34_L13_N	P5	78	FBIO_PAD_21
FPGA_PAD[12]	29	B34_L12_P	T5	79	FBIO_PAD_22
FPGA_PAD[31]	30	B34_L12_N	T4	80	FBIO_PAD_23
FPGA_PAD[13]	31	B34_L11_N	T3	81	FBIO_PAD_24
FPGA_PAD[30]	32	B34_L11_P	R3	82	FBIO_PAD_25
FPGA_PAD[29]	33	B34_L14_P	P4	83	FBIO_PAD_26
FPGA_PAD[28]	34	B34_L14_N	P3	84	FBIO_PAD_27
FPGA_PAD[14]	35	B34_L16_N	N4	85	FBIO_PAD_28
FPGA_PAD[27]	36	B34_L16_P	M4	86	FBIO_PAD_29
FPGA_PAD[15]	37	B34_L17_N	T1	87	FBIO_PAD_30
FPGA_PAD[26]	38	B34_L17_P	R1	88	FBIO_PAD_31
FPGA_PAD[16]	39	B34_L15_N	R2	89	FBIO_PAD_32
FPGA_PAD[25]	40	B34_L15_P	P2	90	FBIO_PAD_33
FPGA_PAD[17]	41	B34_L3_N	N1	91	FBIO_PAD_34
FPGA_PAD[24]	42	B34_L3_P	N2	92	FBIO_PAD_35
FPGA_PAD[18]	43	B34_L1_N	M1	93	FBIO_PAD_RSTB
FPGA_PAD[23]	44	B34_L1_P	L1	94	EXT0_INT
	45	VCCIO34		95	VCC(3.3V)
	46	VIN		96	VCC(3.3V)
FPGA_PAD[19]	47	B34_L4_P	M3	97	EXT1_INT
FPGA_PAD[20]	48	B34_L4_N	M2	98
	49	GND		99	GND
	50	GND		100	GND

2: U20A on the motherboard is connected to J1 of the FPGA daughter board (Pin pins correspond to one, such as 1-1 ...), and the 42 pin IO (3.3v) of FPGA Bank 35 is extended via J17 for users to use; The test case is connected to J2 of the test expansion board (Pin pins correspond to one, such as 1-1 ...), providing FPGA IO expansion

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Design Demo	FPGA daughter board			SP7021 mother board				Test expansion board
spi_flash_axi	J1		U1F	U20A		J17		J2
Top Port Name	Schematic Name		FPGA I/O	Schematic Name		Schematic Name		Schematic Name
	1	GND		1	GND	3	GND	3	GND
	2	GND		2	GND	4	GND	4	GND
	3	B35_L23_N	K1	3	B35_L23_N	5	B35_L23_N	5	PMOD8
	4	B35_L23_P	K2	4	B35_L23_P	6	B35_L23_P	6	PMOD7
	5	VIN		5	VIN	1	VCC	1	VCC
	6	VCCIO35		6	VCCIO35	2	VCC	2	VCC
	7	B35_L15_N	G2	7	B35_L15_N	7	B35_L15_N	7	PMOD6
	8	B35_L15_P	H2	8	B35_L15_P	8	B35_L15_P	8	PMOD5
	9	B35_L13_N	F3	9	B35_L13_N	9	B35_L13_N	9	PMOD4
	10	B35_L13_P	F4	10	B35_L13_P	10	B35_L13_P	10	PMOD3
	11	B35_L12_N	D3	11	B35_L12_N	11	B35_L12_N	11	LED_D1PMOD1
	12	B35_L12_P	E3	12	B35_L12_P	12	B35_L12_P	12PMOD1	LED_D1
	13	B35_L22_P	J3	13	B35_L22_P	13	B35_L22_P	13	LED_D2
	14	B35_L22_N	J2	14	B35_L22_N	14	B35_L22_N	14	PMOD2
	15	B35_L17_N	G1	15	B35_L17_N	15	B35_L17_N	15	LED_D3
	16	B35_L17_P	H1	16	B35_L17_P	16	B35_L17_P	16	LED_D4
	17	B35_L18_N	E1	17	B35_L18_N	17	B35_L18_N	17	LED_D5
	18	B35_L18_P	F1	18	B35_L18_P	18	B35_L18_P	18	LED_D6
	19	B35_L14_N	D2	19	B35_L14_N	19	B35_L14_N	19	LED_D7
	20	B35_L14_P	E2	20	B35_L14_P	20	B35_L14_P	20	LED_D8
	21	B35_L16_P	C2	21	B35_L16_P	21	B35_L16_P	21	SPI_WP
FPGA_SPI_DI	22	B35_L16_N	C1	22	B35_L16_N	22	B35_L16_N	22	SPI_DO
FPGA_SPI_CS_B	23	B35_L9_N	A1	23	B35_L9_N	23	B35_L9_N	23	SPI_CS
	24	B35_L9_P	B1	24	B35_L9_P	24	B35_L9_P	24	SPI_HOLD
FPGA_SPI_CLK	25	B35_L10_P	B3	25	B35_L10_P	25	B35_L10_P	25	SPI_CLK
FPGA_SPI_DO	26	B35_L10_N	B2	26	B35_L10_N	26	B35_L10_N	26	SPI_DI
	27	B35_L8_N	A3	27	B35_L8_N	27	B35_L8_N	27	U1-1
	28	B35_L8_P	A4	28	B35_L8_P	28	B35_L8_P	28	U2-1
	29	B35_L11_N	D4	29	B35_L11_N	29	B35_L11_N	29	U3-1
	30	B35_L11_P	D5	30	B35_L11_P	30	B35_L11_P	30	U4-1
	31	B35_L3_N	A5	31	B35_L3_N	31	B35_L3_N	31	LED-B
	32	B35_L3_P	A6	32	B35_L3_P	32	B35_L3_P	32	LED-F
	33	B35_L2_N	B6	33	B35_L2_N	33	B35_L2_N	33	LED-A
	34	B35_L2_P	B7	34	B35_L2_P	34	B35_L2_P	34	LED-E
	35	B35_L7_N	B4	35	B35_L7_N	35	B35_L7_N	35	LED-D
	36	B35_L7_P	C4	36	B35_L7_P	36	B35_L7_P	36	LED-RA
	37	B35_L1_N	C5	37	B35_L1_N	37	B35_L1_N	37	LED-C
	38	B35_L1_P	C6	38	B35_L1_P	38	B35_L1_P	38	LED-G
	39	B35_L5_N	E5	39	B35_L5_N	39	B35_L5_N	39	GND
	40	B35_L5_P	E6	40	B35_L5_P	40	B35_L5_P	40	GND
	41	B35_L6_N	D7	41	B35_L6_N	41	B35_L6_N
	42	B35_L6_P	E7	42	B35_L6_P	42	B35_L6_P
	43	B35_L19_P	G6	43	B35_L19_P	43	B35_L19_P
	44	B35_L19_N	F6	44	B35_L19_N	44	B35_L19_N
	45	VCCIO35		45	VCCIO35	49	VCC
	46	VIN		46	VIN	50	VCC
	47	B35_L4_N	C7	47	B35_L4_N	45	B35_L4_N
	48	B35_L4_P	D8	48	B35_L4_P	46	B35_L4_P
	49	GND		49	GND	47	GND
	50	GND		50	GND	48	GND

7.2 Implementation of System Software Platform for SPI FLASH Controller IP Design Experiment Project

In the IDE environment, as shown below, select the sp7021 project name, click the right mouse button and select Copy in the pop-up menu

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Next, you need to copy all the files and folders under the installation directory \SP7021\example\ spi_flash_axi to the spi_flash_axi project directory built above (the path is: installation directory\SP7021\ workspace\spi_flash_axi\). The program codes main.c; spi.c; and spi.h required for the Flash controller IP design practice are placed in the following paths:

1） Install main.c under the directory \SP7021\workspace\spi_flash_axi\ foldermain.c

2） Installspi.c in the directory \SP7021\workspace\spi_flash_axi\testapi\util\spi.c

3） Install spi.h in the directory \SP7021\workspace\spi_flash_axi\include\util\spi.h

Finally, as shown in the figure below, clicks the mouse selects the red box 1, then clicks the right mouse button to appear the drop-down menu, and then selects the red box 2, refresh the copy action just now, so that the file just copied can be displayed in the IDE environment

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operation_done(); Wait to read 8byte data from flash device until the operation is completed

7.3 Run Program code

After compile in the Plus1 IDE environment, download to the platform and see the following information in the terminal window

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Versions Compared

Old Version 6

New Version Current

Key

1 Design Brief

2 Design specifications

3 I/O Ports Description

3.1 Global signal

3.2 AXI Interface

3.3 SPI Interface

3.4 Interrupt

4 Registers File

Register Lists

4.1 SPI Configuration Register (SPI_CON,ADDR=32'h0)

4.2 SPI Mode Configuration Register(SPI_MODE,ADDR=32'h4)

4.3 SPI Flash Command and Address (SPI_CMD,ADDR=32'h8)

4.4 Interrupt Status Register (INT_FLAG,ADDR=32'hc)

4.5 Interrupt Mask Register (INT_MASK,ADDR=32'h10)

4.6 WRITE DATA (W_DATA,ADDR=32'h14)

4.7 Read Data FIFO (R_DATA,ADDR=32'h18)

4.8 BYTE _NUM (ADDR=32'h1c)

5 Functional Description

5.1 SPI Flash Controller Block Diagram

5.2 Internal FSM

5.3 FIFO

5.4 Polling Status and Interrupt

6 Timing Figures

6.1 AXI Bus Write

6.2 AXI Bus Read

6.3 SPI Bus Write

6.4 SPI Bus Read

6.5 SPI Clock

6.6 Parallel to Serial

6.7 Serial to Parallel

7 SOC integration

7.1 Implementation of hardware platform for SPI FLASH controller IP design experiment project

7.2 Implementation of System Software Platform for SPI FLASH Controller IP Design Experiment Project

7.3 Run Program code