SPI FLASH Controller IP design

Case download:
spi_flash_axi.zip

1 Design Brief

SPI (Serial Peripheral Interface) serial peripheral device interface bus system is a high-speed, full-duplex, synchronous communication bus, which enables MCU to communicate with various peripheral devices in a serial manner to exchange information. The SPI bus system can directly interface with a variety of standard peripheral devices produced by various manufacturers. It is mainly used between EEPROM, FLASH, real-time clock, AD converter, digital signal processor and digital signal decoder.

The SPI bus system interface signals are as follows:

（1）SDO-Master device data output, slave device data input

（2）SDI – Master device data input, slave device data output

（3）SCLK – Clock signal, generated by the master device

（4）CS-slave device enable signal, controlled by the master device

The communication principle of SPI is simple. It works in a master-slave mode. This mode usually has a master device and one or more slave devices. It requires 4 wires, and only occupies four wires on the pins of the chip, saving the chip's The pins also save space and provide convenience for the layout of the PCB. It is precisely because of this simple and easy-to-use feature that more and more chips are now integrating this communication protocol.

Among them, CS is to control whether the chip is selected, that is to say, only when the chip selection signal is a predetermined enable signal (high potential or low potential), the operation of this chip is effective. This allows multiple SPI devices to be connected on the same bus. The next three lines are responsible for communication. The SCLK signal line is only controlled by the master device, and the slave device cannot control the signal line. SPI is a serial communication protocol, and data is transmitted bit by bit. SCLK provides the clock pulse, and SDI and SDO complete the data transmission based on this pulse. The data output goes through the SDO line, and the data changes on the rising or falling edge of the clock and is read on the following falling or rising edge. To complete a one-bit data transfer, the input also uses the same principle. In this way, at least 8 clock signal changes (upper edge and lower edge is once), you can complete the 8-bit data transmission.

SPI is also a data exchange protocol: because the data input and output lines of the SPI are independent, it is allowed to complete the data input and output at the same time. Different SPI devices have different implementation methods, mainly because the data change and acquisition time are different. There are different definitions for the upper or lower edge of the clock signal. For details, please refer to the relevant device documentation.

The controller designed in this practice follows the standard and universal SPI Flash control protocol, which can realize the operation of SPI Flash device of multiple manufacturers. The DIP 8 socket on the supporting test expansion board can be plugged into the SPI Flash device of different manufacturers; It is the W25xx series of Winbond, and its port structure is shown in the figure:

Winbond W25xx series SPI NOR Flash

The SPI interface of W25xx consists of 8 pins: /CS, DO, /WP, GND, VCC, /HOLD, CLK and DIO, where GND and VCC are the power supply terminals, and CLK is the clock of the entire SPI bus, DIO is the host Output, slave input, DO is the master input, slave output. /CS is the selection flag port of the slave. In two SPI bus devices that communicate with each other, /CS is controlled by the master. When /CS is low, the master and the slave start to exchange information. / WP is the FLASH status protection port. When /WP is low, some FLASH status bits cannot be changed, which can indirectly protect the data in the FLASH memory and prevent the loss of original data caused by the writing of external data . In this example, through the research and implementation of the most basic Flash device and SPI bus protocol, the SPI Flash Controller is designed to familiarize with the design and verification of the IP core.

2 Design specifications

l  Support AMBA4 AXI(lite) 32 bit Bus interface.

l  Support SPI flash 1 bit interface.

l  Support SPI mode 0 and SPI mode 3 programable

l  Support 4 byte read/write buffer.

l  Support the following instruction: Write Enable/Disable, Read/Write Status Register, Read Data, Fast Read, Page Program, Block/Sector/Chip Erase, Read JEDEC ID.

l  Support write buffer before starting write_opeartion to device.

l  Support buffer empty/full interrupt.

l  Support transfer complete interrupt.

l  Support buffer empty/full and transfer complete status polling.

l  Support interrupt status write "1" clear.

l  Support interrupt enable/disable/programable.

l  Support system clock frequency 25MHz to 100MHz.

l  Support SPI interface transfer speed configurable: 1/4 system clock, 1/8 system clock, 1/16 system clock.

l  Support software reset.

3  I/O Ports Description

3.1 Global signal

3.2 AXI Interface

3.3 SPI Interface

3.4 Interrupt

4 Registers File

Register Lists

4.1 SPI Configuration Register (SPI_CON,ADDR=32'h0)

Default value: 32’h00

4.2  SPI Mode Configuration Register(SPI_MODE,ADDR=32'h4)

Default value: 32’h0

4.3  SPI Flash Command and Address (SPI_CMD,ADDR=32'h8)

Default value: 32’h0

4.4 Interrupt Status Register (INT_FLAG,ADDR=32'hc)

Default value: 32’h0

4.5 Interrupt Mask Register (INT_MASK,ADDR=32'h10)

Default value: 32’h0

4.6 WRITE DATA (W_DATA,ADDR=32'h14)

Default value: 32’h0

4.7 Read Data FIFO (R_DATA,ADDR=32'h18)

Default value: 32’h0

4.8 BYTE _NUM (ADDR=32'h1c)

Default value: 32’h1

5     Functional Description

5.1  SPI Flash Controller Block Diagram

The FSM is used to control and harmonize the whole system. Master configures the necessary information to the controller through AXI Bus

FSM: Control the configuration logic, make the whole system to work normally.

Register File: Store the configure, status and data.

FIFO: Used as a buffer in RECEIVER and TRANSMITTER.

Interface : Translate the logic

5.2    Internal FSM

5.3    FIFO

FIFO is important to this design as all data are transferred by it. Following is the 2-pointer FIFO.

It is a 8*8-bit FIFO, so the width of both write pointer (WP) and read pointer (RP) are 3 bits. Read data once, RP adds one, while write data once, WP adds one. When write, first write data, then move the WP pointer; when read, first read data, then move the RP pointer.

When WP = RP indicates FIFO is empty.

When WP[2] = (~RP[2]) and WP[1:0] = RP[1:0] shows this is a full FIFO.

When FIFO is full/empty but still write/read, FIFO will overflow/underflow.

5.4    Polling Status and Interrupt

The design provide programmable interrupt output and polling the interrupt flag through INT_FLAG.   SPI_INT will be high when interrupt happens.

Each interrupt source can read in proper bits of INT_FLAG.

Each interrupt source can also be mask in the same bits of INT_MASK.

Each interrupt should be clear by sending clear interrupt command.

There are such  interrupt source as below:

6   Timing Figures

6.1 AXI Bus Write

6.2  AXI Bus Read

6.3  SPI Bus Write

6.4  SPI Bus Read

6.5  SPI Clock

6.6   Parallel to Serial

6.7  Serial to Parallel

7 SOC integration

7.1  Implementation of hardware platform for SPI FLASH controller IP design experiment project

The SPI FLASH controller IP core design is the AMBA AXI slave 32bit bus interface, We choose axi_ bus_ m32_bridge module from Bus Bridge series ,so the AXI master bus interface provided by the bus bride module is used to connect our IP as follows :

This experiment uses the FPGA daughter board and extended test board supporting the SP7021 practice platform to complete the relevant experiments. The development tool of the FPGA daughter board uses the XILINX Vivado integrated development environment (version number 2018.3); in order to facilitate the convenience of the user to verify the IP Connected to the SOC system to verify, this experiment provides the corresponding design reference basic file, as follows

The corresponding connection between the design case and the pin connection of the SP7021 motherboard and FPGA daughter board is shown in the following table: 1: U20B on the main board is connected to J2 of the FPGA daughter board (Pin pin corresponding, such as 1-51 ...), providing the data transmission channel between the Plus1 main chip on the main board and the FPGA

2: U20A on the motherboard is connected to J1 of the FPGA daughter board (Pin pins correspond to one, such as 1-1 ...), and the 42 pin IO (3.3v) of FPGA Bank 35 is extended via J17 for users to use; The test case is connected to J2 of the test expansion board (Pin pins correspond to one, such as 1-1 ...), providing FPGA IO expansion

7.2  Implementation of System Software Platform for SPI FLASH Controller IP Design Experiment Project

In the IDE environment, as shown below, select the sp7021 project name, click the right mouse button and select Copy in the pop-up menu

Next, select the sp7021 project name again

Click the right mouse button and select Paste in the pop-up menu, the following picture appears

Fill in spi_flash_axi in the Project name box to complete the spi_flash_axi project name and directory creation, as shown below

Next, you need to copy all the files and folders under the installation directory \SP7021\example\ spi_flash_axi to the spi_flash_axi project directory built above (the path is: installation directory\SP7021\ workspace\spi_flash_axi\). The program codes main.c; spi.c; and spi.h required for the Flash controller IP design practice are placed in the following paths:

1） \SP7021\workspace\spi_flash_axi\main.c

2） \SP7021\workspace\spi_flash_axi\testapi\util\spi.c

3） \SP7021\workspace\spi_flash_axi\include\util\spi.h

Finally, as shown in the figure below, clicks the mouse selects the red box 1, then clicks the right mouse button to appear the drop-down menu, and then selects the red box 2, refresh the copy action just now, so that the file just copied can be displayed in the IDE environment

main.c

void operation_done()

void flash_device_write_en()

void flash_device_done()

void spi_read_id()

void spi_write_data()

void spi_read_data()

int main(void)

{

    printf("Build @%s, %s\n", __DATE__, __TIME__);

    hw_init();

    sys_init();

    fbio_init();

    disp_hdmi_init();

    sp_interrupt_setup(); /* interrupt manager module init */

    spi_read_id();

    spi_write_data();

    spi_read_data();

    printf("%s:%5d\n", __FUNCTION__,__LINE__);

    while(1);

}

Compared with the IP experiment of nixie tube control, spi flash operation control related functions are added to complete the read and write and erase operations of spi flash.

void spi_read_id()

{

    spi_reg->SPI_CMD=0x9f;

    spi_reg->SPI_CON=0x3;

    operation_done();

    temp=spi_reg->R_DATA;

    printf("@spi flash device id [%x]\n", temp);

}

The operation to read the flash JEDEC ID is as follows:

spi_reg->SPI_CMD=0x9f;  Set the command code 9f to read JEDEC ID;

spi_reg->SPI_CON=0x3;Start reading JEDEC ID operation;

operation_done(); Wait for this operation to complete;

temp=spi_reg->R_DATA; Take out the result after reading JEDEC ID operation from RX FIFO and print it out;

void spi_write_data()

{

    /////////sector erase///////////////

    flash_device_write_en();

    spi_reg->SPI_CMD=0x3020;

    spi_reg->SPI_CON=0x1;

    operation_done();

    flash_device_done();

    //////////write data///////////////////////////

    flash_device_write_en();

    spi_reg->BYTE_NUM=0x8;

    spi_reg->W_DATA =0x12345678;

    spi_reg->W_DATA =0xabcdef91;

    spi_reg->SPI_CMD=0x3002;

    spi_reg->SPI_CON=0x1;

    operation_done();

    flash_device_done();

}

To realize the operation of writing data to the flash device, the write data operation must first erase the address space of the stored data before writing the data, as follows:

flash_device_write_en(); For erasing flash, it must be enabled before writing, which is achieved by setting command code 06;

spi_reg->SPI_CMD=0x3020; Erase flash 4k byte space starting from address 0x300000, realized by setting command code 20

flash_device_done(); Wait to erase the 4k byte space starting from address 0x300000 until the operation is completed

spi_reg->BYTE_NUM=0x8; Set the number of write data to flash device, a total of 8byte;

spi_reg->W_DATA =0x12345678; spi_reg->W_DATA =0xabcdef91;

Set the data to be written to the flash device

spi_reg->SPI_CMD=0x3002; Set the 4k byte space of flash starting at address 0x300000 as the write data space; realize it by setting the command code 02

spi_reg->SPI_CON=0x1; Enable write data operation;

operation_done();

flash_device_done();

Wait to write 8byte data to flash device until the operation is completed

void spi_read_data()

{

    spi_reg->BYTE_NUM=0x8;

    spi_reg->SPI_CMD=0x3003;

    spi_reg->SPI_CON=0x3;

    operation_done();

    temp= spi_reg->R_DATA;

    printf("Read SPI Flash:  [%x]\n", temp);

    temp= spi_reg->R_DATA;

    printf("Read SPI Flash:  [%x]\n", temp);

}

    spi_reg->BYTE_NUM=0x8; Set the total number of data read from the flash device 8byte;

    spi_reg->SPI_CMD=0x3003; Set flash to read data from address 0x300000, which is realized by setting command code 03

    spi_reg->SPI_CON=0x3; Enable read data operation;

    operation_done(); Wait to read 8byte data from flash device until the operation is completed

7.3 Run Program code

After compile in the Plus1 IDE environment, download to the platform and see the following information in the terminal window