8. Electrical Characteristics

8.1. Absolute Maximum Ratings

Symbol	Parameter	MIN.	MAX.	Unit
V_DVD33, V_{VDD33_AO}	Supply voltage 3.3V	-0.3	3.45	V
V_DVDD15	Supply voltage 1.5V, DDR3_VDDQ	-0.075	1.575	V
V_CVDD12	Supply voltage 1.2V	-0.12	1.32	V
V_CVDD09	Supply voltage 0.9V	-0.045	1	V
V_O	Output voltage	-0.3	V_DVD33 + 0.3	V
V_i	Input voltage (non 5V tolerant inputs)	-0.3	V_DVD33 + 0.3	V
V_i5vtol	Input voltage (5V tolerant inputs)	-0.3	5.5	V
T_J-MAX	Junction temperature		125	°C
T_STG	Storage temperature	-55	150	°C
T_SOL	Lead temperature (soldering, 4 sec)		260	°C

8.2. Thermal Information

Symbol	Parameter	Unit(°C/W)
_JA	Thermal resistance, junction to ambient(4 Layer PCB), Ambient 85°C	17.66
C_JT	Junction-to-top characterization parameter	1.63

Note: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In the application where high maximum power dissipation exists, special attention must be paid to thermal dissipation issues in board design.

8.3. ESD Ratings

Symbol	Parameter	Value	Unit
V_ESD	Human Body Model (test Per JESD22-A114F, Class 2)	2	KV
V_ESD	Charge Device Model (test per JESD22-C101E, Class III)	500	V
I_LA	Latch-up tolerance (test Per JESD78C, Class I)	100	mA

8.4. DC Operating Conditions

Voltage referenced to VSS=0V, T_OPT =-40°C to 85°C

Symbol	Parameter	MIN.	Nom.	MAX.	Unit
V_DVD33, V_{VDD33_AO}	Supply voltage 3.3V	3.13	3.30	3.45	V
V_DVDD15	Supply voltage 1.5V	1.42	1.50	1.57	V
V_CVDD12	Supply voltage 1.2V	1.18	1.25	1.32	V
V_CVDD09	Supply voltage 0.9V	0.90	0.95	1.00	V
T_J	Operating Junction temperature			125	°C
T_OPT	Operating temperature	-40		85	°C

8.5. DC Characteristics

Symbol	Parameter	Conditions	MIN.	Typ.	MAX.	Unit
TMDSTX Specification
AVcc	Termination Supply Voltage		3.135		3.465	V
R_T	Termination Resistance		4.5		5.5	Ω
V_OFF	Single-ended standby(off) output voltage		AVcc-10mV		AVcc+10mV	V
V_swing	Single-ended output swing voltage		400		600	mV
V_H	Single-ended high level output voltage	Attached Sink supports <= 165MHz	AVcc-10mV		AVcc+10mV	V
V_H	Single-ended high level output voltage	Attached Sink supports > 165MHz	AVcc-200mV		AVcc+10mV	V
V_H	Single-ended low level output voltage	Attached Sink supports <= 165MHz	AVcc-600mV		AVcc-400mV	V
V_H	Single-ended low level output voltage	Attached Sink supports > 165MHz	AVcc-700mV		AVcc-400mV	V
MIPI Basic Specification
AVDD	Analog operation Voltage		1.08	1.2	1.32	V
VDD	Core operation voltage		1.08	1.2	1.32	V
Temp	Operating temperature range		-40		125	℃
TStart	Power up/Power down time		1.08		20	uS
MIPI HS Mode
VCMRX(DC)	Common-mode voltage HS receive mode		70		330	mV
VIDTH	Differential input high threshold				70	mV
VIDTL	Differential input low threshold		-70			mV
VIHHS	Single-ended input high voltage				460	mV
VILHS	Single-ended input low voltage		-40			mV
VOD	Differential voltage swing		70			mV
FCLK	Operating frequency		80		750	MHz
VTERM-EN	Single-ended threshold for HS termination enable				450	mV
ZID	Differential input impedance		80	100	125	Ω
MIPI LP Mode
V_IH	Logic 1 input voltage		880			mV
V_IL	Logic 0 input voltage, not in ULP State				550	mV
V_IL-ULPS	Logic 0 input voltage, ULP State				300	mV
V_HYST	Input hysteresis		25			mV
GPIO
V_IL	Input Low Voltage		-0.3		0.8	V
V_IH	Input High Voltage		2		5.5	V
V_OL	Output Low Voltage				0.4	V
V_OH	Output High Voltage		2.4			V
I_OL	Low Output Current @ V_OL(max) (Port 1 ~ 8)	08:08mA	9.4	14.8	19.8	mA
I_OL1	Low Output Current @ V_OL(max) (Port 0)	16:16mA	18.9	29.5	39.6	mA
I_OH	High Output Current @ V_OL(min) (Port 1 ~ 8)	08:08mA	14.0	28.7	48.2	mA
I_OH1	High Output Current @ V_OL(min) (Port 0)	16:16mA	27.2	55.6	93.4	mA
Power Specification
Supply current @ SYSCLK = 202 MHz / Ram Test @ 25’c Power Saving						mA
I₀₉	0.9V supply current			265		mA
I₁₂	1.2V supply current			1075	1700	mA
I₁₅	1.5V supply current			170		mA
I₃₃	3.3V supply current			73		mA
P_D	Power dissipation	_202MHz		2024		mW
P_s	Standby mode	_{AO33V@32.768KHz}		3.00		mW
P_u	Ultra Low Standby mode	_{AO33V@32.768KHz}		1.75		mW

Note: the maximum current of 1.2V power is about 1700mA in worst case (FF, 90 degree Celsius).

8.6. AC Characteristics

8.6.1. SPI NOR Specification

Figure 8-1 SPI NOR Output Timing

Figure 8-2 SPI NOR Input Timing

Symbol	Parameter	Conditions				Data Bit	Unit
Symbol	Parameter	Conditions	MIN.	Typ.	MAX.	Data Bit	Unit
tCK	Clock cycle for SPI NOR Flash			9.88		D0	ns
tCKH	Clock high-level width for SPI NOR Flash			4.94		D1	ns
tCKL	Clock low-level width for SPI NOR Flash			4.94		D2	ns
tSLCH	SPI_NOR_CEN active setup time relative to SPI_NOR_CLK		19.76			D3	ns
tDDLY	Write data output delay from SPI_NOR_CLK Falling edge		0.30			D0	ns
						D1
						D2
						D3
tRDVLD	Read data valid time		2.50			D0	ns
						D1
						D2
						D3

Note : Test for Clock cycle of SPI_NOR_FLASH device is 101.25Mhz.

8.6.2. SPI NAND FLASH Specification

Figure 8-3 SPI NAND Output Timing

Figure 8-4 SPI NAND Input Timing

Symbol	Parameter	Conditions			Data Bit	Unit
Symbol	Parameter	MIN.	Typ.	MAX.	Data Bit	Unit
tCK	Clock cycle for SPINAND		9.88		D0	ns
tCKH	Clock high-level width for SPI NAND		4.94		D1	ns
tCKL	Clock low-level width for SPI NAND		4.94		D2	ns
tSLCH	SPI_NAND_CEN active setup time relative To SPI_NAND_CLK	19.76			D3	ns
tDDLY	Write data output delay from SPI_NAND_CLK falling edge	0.6			D0	ns
					D1
					D2
					D3
tRDVLD	Read data valid time	3			D0	ns
					D1
					D2
					D3

8.6.3. eMMC Timing Diagrams

Figure 8-5 eMMC Timing

Bus Timing - Parameters Values ( High Speed )
Clock CLK (All values are referred to min (VIH) and max (VIL)) , CL ≦ 30 pF
Parameter	Symbol	Specification			Unit
	Symbol	Min.	Typ.	Max.	Unit
Clock Frequency Data Transfer Mode	FPP		50		MHz
Clock duty cycle			50		%
Clock rise time	tTLH	1.9		2.2	ns
Clock fall time	tTHL	2.6		3.3	ns
Input DAT (referenced to CLK-DDR mode), CL ≦ 20 pF
Input set-up time	tISUddr		5.1		ns
Input hold time	tIHddr		2.8		ns
Output DAT (referenced to CLK-DDR mode), CL ≦ 20 pF
Output delay time during data transfer	tODLYddr		max :6.9 min : 4.0		ns
Signal rise time	tRISE		2.8		ns
Signal fall time	tFALL		2.8		ns
Input CMD (referenced to CLK-SDR mode), CL ≦ 20 pF
Input set-up time	tISU		13.9		ns
Input hold time	tIH		3.5		ns
Output CMD (referenced to CLK-SDR mode), CL ≦ 20 pF
Output delay time during data transfer	tODLY		5.9		ns
Output hold time	tOH		3.5		ns
Signal rise time	tRISE		2.3		ns
Signal fall time	tFALL		2.7		ns

eMMC Interface AC timing

Push-pull Signal Level for High Voltage
Parameter	Symbol	Specification		Unit
Parameter	Symbol	Min.	Max.	Unit
Supplu Voltage	VDD	2.7	3.6	V
Output High Voltage	VOH	3.0		V
Output Low Voltage	VOL		0.45	V
Input High Voltage	VIH	3.0	3.6	V
Input Low Voltage	VIL	0	0.45	V

eMMC Interface signal level measurement

Bus Timing - Parameters Values ( High Speed )
Input DAT (referenced to CLK-DDR mode), CL ≦ 20 pF
Parameter	Symbol	Specification		Unit
Parameter	Symbol	Min.	Max.	Unit
Input set-up time	tISUddr	2.0		ns
Input hold time	tIHddr	2.2		ns

Output delay time during data transfer	tODLYddr (max)		8.6	ns
Output delay time during data transfer	tODLYddr (min)	1.3		ns

8.6.4. SD/SDIO Timing Diagrams

SD/SDIO High speed Mode

Figure 8-6 SD/SDIO Timing

Symbol	Parameter	Conditions	MIN.	Typ.	MAX.	Unit
V_DD	Supplu Voltage		2.7		3.6	V
V_OH	Output High Voltage	IOH = -2mA VDD min	0.75 * V_DD			V
V_OL	Output Low Voltage	IOL = 2mA VDD min			0.125 * V_DD	V
V_IH	Input High Voltage		0.625 * V_DD		V_DD + 0.3	V
V_IL	Input Low Voltage		V_SS-0.3		0.25*V_DD	V
	Power Up Time	From 0V to VDD min			250	ms

Threshold Level for High Voltage

Threshold Level for High Voltage
Parameter	Symbol	Specification		Unit
Parameter	Symbol	Min.	Max.	Unit
Supplu Voltage	V_DD	2.7	3.6	V
Output High Voltage	V_OH	3		V
Output Low Voltage	V_OL		0.25	V
Input High Voltage	V_IH	3.0	3.3	V
Input Low Voltage	V_IL	0.20	0.30	V
Power Up Time			250ms	ns
Bus Timing - Parameters Values ( High Speed )
Clock CLK (All values are referred to min (VIH) and max (VIL)) , C_CARD ≦ 10 pF ( 1 card )
Parameter	Symbol	Specification		Unit
Parameter	Symbol	Min.	Max.	Unit
Clock Frequency Data Transfer Mode	F_PP	0	50	MHz
Clock low time	T_WL	7		ns
Clock high time	T_WH	7		ns
Clock rise time	T_TLH		3	ns
Clock fall time	T_THL		3	ns
Input CMD , DAT (referenced to CLK), C_CARD ≦ 10 pF ( 1 card )
Input set-up time	T_ISU	6		ns
Input hold time	T_IH	2		ns
Output CMD, DAT (referenced to CLK), C_CARD ≦ 40 pF ( 1 card )
Output Delay time during Data Transfer Mode	T_ODLY	0	14	ns
Output Hold time	T_OH	2.5		ns

Bus Timing - Parameters Values (High Speed)

8.6.5. MIPI Low Power receiver AC specification.

Figure 8-7 Input Glitch Rejection of Low-Power receiver

MIPI LP receiver AC specifications

Symbol	Parameter	Conditions	MIN.	Typ.	MAX.	Unit
e_SPIKE	Input pulse rejection				300	V*ps
T_{MIN_RX}	Minimum pulse width response		20			ns
V_INT	Peak interference amplitude				200	mV
F_INT	Interference frequency		300		450	MHz

8.6.6. Ethernet Timing Diagrams

Serial Management Timing

Figure 8-8 Ethernet SMI timing diagram

Symbol	Parameter	Condition			Unit
Symbol	Parameter	MIN.	Typ.	MAX.	Unit
tMDCK	Clock cycle for MDIO	400			ns
tMDCKH	Clock high-level width for MDIO	200			ns
tMDCKL	Clock low-level width for MDIO	200			ns
tMDDLY	MDC to MDIO (input) Delay Time			240	ns
tMDSU	MDIO (output) to MDC Setup Time	10			ns
tMDH	MDIO (output) to MDC Hold Time	10			ns

SMI AC Timing

RMII Timing

Figure 8-9 RMI timing diagram

Symbol	Parameter	Condition			Unit
Symbol	Parameter	MIN.	Typ.	MAX.	Unit
tRMIICK	RMII Clock Period		20		ns
	RMII Clock Duty Cycle	35		65	%
tDSU	TX_Data Setup to RMII Clock rising	4			ns
tDH	TX_Data Hold from RMII Clock rising	2			ns
tESU	TX_EN Setup to RMII Clock rising	4			ns
tEH	TX_EN Hold from RMII Clock rising	2			ns
tDDLY	RX_Data Delay from RMII Clock rising	4	10	14	ns
tCDDLY	CRS_DV Delay from RMII Clock rising	4	10	14	ns

Table 1 RMII AC Timing

8.6.7. I2C AC Timing Diagram

Figure 8-10 I2C AC timing diagram

SYMBOL	STANDARD-MODE		FAST-MODE		UNIT
	MIN.	MAX	MIN.	MAX	UNIT
f_SCL	0	100	0	400	kHZ
t_HD;STA	4.0	–	0.6	–	μs
t_LOW	4.7	–	1.3	–	μs
t_HIGH	4.0	–	0.6	–	μs
t_SU;STA	4.7	–	0.6	–	μs
t_HD;DAT	0	3.45	0	0.9	μs
t_SU;DAT	250	–	100	–	ns
t_r	–	1000	20	300	ns
t_f	–	300		300	ns
t_SU;STO	4.0	–	0.6	–	μs
t_BUF	4.7	–	1.3	–	μs
t_VD;DAT	–	3.45^[4]	–	0.9	μs
t_VD;ACK	–	3.45	–	0.9	μs
t_SP	–	–	0	50	ns

I2C Timing Table.

8.6.8. I2S Master AC Timing Diagrams

Figure 8-11 I2S (Master) AC Timing diagram

Symbol	Parameter	Condition			Unit
Symbol	Parameter	MIN.	Typ.	MAX.	Unit
TLR = 1/FS	LRCK Period (1/FS)				us
FS	LRCK Frequency				KHz
TBCK = 1/ FBCK	BCK Period	32		192	ns
FBCK	BCK Frequency				MHz
TBCKL	BCK Pulse Width Low	2.048		12.288	ns
TBCKH	BCK Pulse Width High			244	ns
TLRB	LRCK Edge to BCK Rising Edge			244	ns
Tsmd	XCK to BCK active edge delay	0		15	ns
Timd	XCK to LRCK delay	0		15	ns

I2S IN (Master) AC Timing

Symbol	Parameter	Condition			Unit
Symbol	Parameter	MIN.	Typ.	MAX.	Unit
TLR = 1/FS	LRCK Period (1/FS)				us
FS	LRCK Frequency				KHz
TBCK = 1/ FBCK	BCK Period	32		192	ns
FBCK	BCK Frequency				MHz
TBCKL	BCK Pulse Width Low	2.048		12.288	ns
TBCKH	BCK Pulse Width High			244	ns
TLRB	LRCK Edge to BCK Rising Edge	4		244	ns
TDS	I2S_D0 Set-Up Time	6			ns
TDH	I2S_D0 Hold Time	6			ns
Tsmd	XCK to BCK active edge delay	0		15	ns
Timd	XCK to LRCK delay	0		15	ns

I2S OUT (Master) AC Timing