1 Design Brief
UART is short for Universal Asynchronous Receiver and Transmitter. Used for communication between serial input and serial output devices. Serial transmission comes at the cost of speed, in exchange for a reduction in cost and complexity of wiring. UART provides synchronization of serial asynchronous received data, parallel-to-serial and serial-to-parallel data conversion of the transmitter and receiver, for digital systems that need to convert serial data streams to parallel data, these functions Is essential. Synchronization of the serial data stream is achieved by adding start and stop bits to the transmitted data to form a data character. Data integrity is achieved by appending a parity bit to the data character, which is provided by the receiver Check this parity bit to check whether there is any transmission bit error. It is mainly composed of data bus interface, control logic, baud rate generator, sending part and receiving part.
1.1 Protocol
The communication protocol is the regulation of the data transmission method, including the definition of the data format and the definition of the data bits. Both parties must follow a unified communication protocol. The following is the transmission format of character data specified by the asynchronous serial communication protocol. In asynchronous communication, data is transmitted frame by frame (including a character code or a byte of data), and the data format of each frame is shown in the following figure
In the frame format, a character is composed of four parts: start bit, data bit, parity bit, and stop bit.
(1)、Start bit
The start bit (low level "0") occupies only one bit and informs the receiving device that a character to be received starts to arrive. Logic 1 state when no data is being transmitted on the communication line. When the sending device wants to send a character data, first add a logic 0 signal, this logic low level is the start bit, the receiving end continuously detects the state of the line, the receiving device detects this logic low level and starts Ready to accept data bit signals. The start bit of the character is also used to synchronize the clock of the receiving end to ensure that the subsequent reception can be performed correctly. The start bit enables the device to synchronize, and both parties must coordinate the synchronization before transmitting the data bit.
(2)、Data bit
The start bit is immediately followed by the data bit, which can be 5, 6, 7, or 8 bits. When the receiving device receives the start bit, it immediately receives the data bit. These data bits are received into the shift register and constitute the transmitted data characters. In the transmission of character data, the data bits are sent from the least significant bit and are sequentially converted into data in the receiving device.
(3)、Parity bit
After the data bits are sent, parity bits can be sent. The parity bit only occupies one bit, and the parity bit can be omitted, or this bit can be omitted, or this bit can also be used to determine the nature of the information represented by the characters in this frame (address / data, etc.) Parity check belongs to limited error detection, and both parties in communication must agree on a consistent parity check method. If you select even parity, the number of logic 1s that make up the data bits and parity bits must be even; if you select odd parity, then the number of logic 1s must be odd.
(4)、Stop bit convention
The stop bit is sent after the parity bit or data bit (when there is no parity check). The stop bit is the end mark of a character data, which can be a high level of 1, 5, or 2 bits. After receiving the stop bit, the receiving end indicates that the previous character has been transmitted, and at the same time, it is also ready to receive the next character. If it receives 0 again, the new character begins to transmit. If the stop bit is not followed by a character, the line level is kept high ("1"), which is the idle bit. After the receiving device receives the stop bit, the logic 1 state is restored on the communication line until the start bit of the next character data arrives.
(5)、Baud rate setting
All bit signals transmitted on the communication line maintain a consistent signal duration, and the signal duration of each bit is determined by the data transmission speed, that is, measured by how many binary bits per second, this speed is called the baud rate. If the data is transmitted on the communication line with 300 binary bits per second, the transmission speed is 300 baud, which is usually recorded as 300 b/s.
(6)、Handshake signal agreement
When the computer and modem exchange data, they often use some signal lines as a prerequisite for exchanging data. When the conditions are met, the data is allowed to be transmitted; when the conditions are not met, they are in a waiting state and wait until the signal that allows data transmission occurs. Data transmission begins again.
1.2 Serial-to-parallel conversion
Serial communication is to convert the parallel data to be transmitted inside the computer into serial data and transmit it through a communication line; then convert the received serial data into parallel data and send it to the computer. Before the computer serially sends data, the parallel data inside the computer is sent to the shift register and shifted out bit by bit, converting the parallel data into serial data. As shown below
When receiving data, the serial data from the communication line is sent to the shift register, and after being shifted and saved to 8 bits, it is sent to the computer in parallel
1.3 Data sampling
When the receiver receives data, the internal clock frequency of the UART is often higher than the external data input frequency. When the receiver starts to receive the signal, if the frequency of the internal clock is close to or less than the external data transmission frequency, when the receiver receives data, it is likely that the data will not be collected at the edge of data sampling, or the wrong data will be collected. The sampling frequency can be set to 8 times, 16 times the external data transmission frequency. The UART uses 16 times the external clock frequency, and the sampled waveforms are as follows:
In this example, through the research of the UART bus protocol, the UART Controller IP is designed to familiarize with the design and verification of the UART IP core
2 Design specifications
l Support AMBA APB2.0 BUS interface.
l Support 5/6/7/8 bits data (packet) transmit and receive.
l Support odd, even or none parity bit generation and declaration.
l Support 1, 1.5 or 2 stop bits generation and declaration.
l Support baud rate configuration (4800bps, 9600bps, 38400bps and 115200bps).
l Support 4 types depth RX FIFO and TX FIFO.
l Support software reset and enable.
l Support polling status – FIFO full and empty, parity check error, stop bit check error.
l Programmable interrupt enable control.
l Support the SW write clear the interrupt.
.
3 I/O Ports Description
3.1 APB Register Bus Interface
Name | Direction | Width | Description |
PSEL | Input | 1 | APB Bus Selected Active high to select CTRL group registers. |
PWRITE | Input | 1 | APB Bus Write Enable Active high to enable register bus write operation. Active low to enable register bus read operation. |
PENABLE | Input | 1 | APB Bus Enable Active high to select CTRL group registers. |
PWDATA | Input | 32 | APB Write Data Bus 32 bit data with [31] is most significant bit. |
PADDR | Input | 5 | APB Bus Address 5 bit address bus with [4] is most significant bit. |
PRDATA | Output | 32 | APB Read Data Bus Register read data bus, [31] is most significant bit. Valid when SL_APB_ACK is active. |
3.2 Interrupt Line
Name | Direction | Width | Description |
INT_B | Output | 1 | Interrupt Low active. When finished a operation, INT_B will be active, such as received a packet or error case happened. |
3.3 System Clock and Reset
Name | Direction | Width | Description |
SYSCLK | Input | 1 | System Clock Free running clock, all registers must be synchronous with SYSCLK. |
RST_B | Input | 1 | System Reset Low active. When this pin is asserted, all flip-flops must be reset to their default value. |
3.4 UART interface
Name | Direction | Width | Description |
RX | Input | 1 | Serial Data input |
TX | output | 1 | Serial Data output |
4 Registers File
4.1 Registers List
Address | Name | Access | Description |
5’h00 | LCR | RW | Line Control Register |
5’h01 | SER | RW | Software Enable Register |
5’h02 | BAUD_CNT | RW | Baud-rate Configuration Register |
5’h03 | LSR | RW | Line State Register |
5’h04 | RX_FIFO | RO | RX FIFO Register |
5’h05 | TX_FIFO | RW | TX FIFO Register |
4.2 Line Configuration Register (LCR, Addr = 5’h0)
Default value: 0x0000_0000
Register Bits | Name | Function Description |
1:0 | WORD_SEL | Word Length Select of the UART 00 : 8 bit data transmit and receive 01 : 7 bit data transmit and receive 10 : 6 bit data transmit and receive 11 : 5 bit data transmit and receive |
3:2 | STOP_SEL | Stop Bit Length of the UART 00 : 1 cycle stop bit 01 : 1.5 cycle stop bit 10 : 2 cycle stop bit Default : 1 cycle stop bit |
5:4 | PTY_SEL | Parity Select of the UART 00 : even parity 01 : odd parity 10 : no parity Default : even parity |
31:6 | RSV | Reserved |
4.3 Software Enable Register (SER, Addr = 5’h1)
Default Value: 0x0000_003f
Register Bits | Name | Function Description |
0 | RX_DONE_EN | Data Ready Interrupt Enable Low active, when this bit is 1, Data Ready will not assert interrupt. |
1 | TX_DONE_EN | Transmitted Complete Interrupt Enable Low active, when this bit is 1, Transmitted Complete will not assert interrupt. |
2 | PTY_ERR_EN | Parity Error Interrupt Enable Low active, when this bit is 1, Parity Error will not assert interrupt. |
3 | STOP_ERR_EN | Stop Bit Error Interrupt Enable Low active, when this bit is 1, Stop Bit Error will not assert interrupt. |
4 | RX_FULL_EN | RX FIFO Full interrupt Enable Low active, when this bit is 1, TRX FIFO full will not assert interrupt. |
5 | TX_EMPTY_EN | TX FIFO Empty interrupt Enable Low active, when this bit is 1, TX FIFO empty will not assert interrupt. |
6 | SW_RST | Soft Reset UART High active , the UART will reset when Master writing 1 to this bit |
7 | RX_EN | Receiver FSM Stop Low active , the Receiver will not work when this bit is 1 |
8 | TX_EN | Transmitter FSM Stop Low active , the Transmitter will not work when this bit is 1 |
31:9 | RSV | Reserved |
4.4 Baud-rate Configuration Register (BAUD_CNT, Addr = 5’h2)
Default Value: 0x0000_0000
Register Bits | Name | Function Description |
31:0 | BAUD_CNT | Baud Rate configure data Store the count value of baud rate generation |
4.5 Line State Register (LSR, Addr = 5’h3)
Default value: 0x0000_0000
Register Bits | Name | Function Description |
0 | RX_DONE | Data Ready High active, the flag of the interrupt that Received a complete packet. The interrupt will be cleaned when this bit is written 0 by master. |
1 | TX_DONE | Transmitted Data Complete High active, the flag of the interrupt that Transmitted a complete packet. The interrupt will be cleaned when this bit is written 0 by master. |
2 | PTY_ERR | Parity Error High active. The interrupt flag that Parity error. The interrupt will be cleaned when this bit is written 0 by master. |
3 | STOP_ERR | Stop Bit Error High active. The interrupt flag that Stop bit error. The interrupt will be cleaned when this bit is written 0 by master. |
4 | RX_FULL | RX FIFO Full High active. The interrupt flag that RX FIFO full. The interrupt will be cleaned when master reads out a data once. |
5 | RX_EMPTY | RX FIFO Empty High active. The flag that the RX FIFO empty |
6 | TX_FULL | TX FIFO Full High active. The flag that the TX FIFO full |
7 | TX_EMPTY | TX FIFO Empty High active. The flag of the interrupt that TX FIFO empty. The interrupt will be cleaned when master writes a data once. |
31:8 | RSV | Reserved |
4.6 RX FIFO Register (RX_FIFO, Addr = 5’h4)
Default Value: 0x00
Register Bits | Name | Function Description |
7:0 | RX_FIFO | Read Data Buffer The depth is 4. Store the data written to Receiver buffer register. |
4.7 TX FIFO Register (TX_FIFO, Addr =5’h5)
Default Value: 0x00
Register Bits | Name | Function Description |
7:0 | TX_FIFO | Write Data Buffer The depth is 4. Store the data written to Transmitter buffer register. |
5 Functional Description
5.1 UART Structure
Interface model: communicate with CPU, configure the UART.
FIFO: store data which will be transmitted or received
Transmit/Receive register: transmit or receive the data stored in the FIFO.
Baud rate occur: occur the clock for transmitter and receiver
5.2 UART Receiver FSM
Current State | Function | Next Status | Jump Condition |
IDLE | Wait start signal. | SHIFT | Start bit detected right and receiver buffer register isn’t full |
IDLE | RX_EN enable or start bit not detected | ||
SHIFT | Receive data | STOP | Last data bit and parity disable |
PARITY | Last data bit and parity enable | ||
SHIFT | Not last data bit | ||
PARITY | Odd/even parity check | STOP | Parity check done |
STOP | Stop bit check | IDLE | Check right, then jump to IDLE Or check right wrong ,INT_B enable, then jump to IDLE |
5.3 UART Transmitter FSM
Current State | Function | Next Status | Jump Condition |
IDLE | Wait for transmitting | START | TX_FIFO is not empty |
IDLE | TX_FIFO is empty or TX_EN enable | ||
START | Transmit start bit | SHIFT | Transmit done |
SHIFT | Transmit data | STOP_1BIT | Last data bit and parity disable |
PARITY | Last data bit and parity enable | ||
SHIFT | Not last data bit | ||
PARITY | Parity bit | STOP_1BIT | Finished the parity configuration |
STOP_1BIT | 1 stop bit | START | 1.5/2 stop bit disable |
STOP_HALFBIT | 1.5 stop bit enable | ||
STOP_2BIT | 2 stop bit enable | ||
STOP_HALFBIT | 1.5 stop bit | START | Finished the stop bit configuration |
STOP_2BIT | 2 stop bit | START | Finished the stop bit configuration |
5.4 FIFO
FIFO is very important to this design as all data are transferred by it. Following is the 2-pointer FIFO
It is a 4X8-bit FIFO, so the width of both write pointer (WP) and read pointer (RP) are 3 bits. Read data once, RP adds one, while write data once, WP adds one.
When write, first write data, then move the WP pointer; when read, first read data, then move the RP pointer.
When WP = RP indicates FIFO is empty.
When WP [2] = (~RP [2]) and WP [1:0] = RP [1:0] shows this is a full FIFO
5.5 Timing Figures
Receive the serial data from RX
Transmit the serial data to TX
6 SOC integration
6.1 Hardware platform implementation of UART controller IP design experiment project
The UART controller IP core design is the AMBA APB bus interface, and our FBIO Wrapper is the AMBA AXI bus interface, which cannot be directly connected together, and requires an AXI2ABP Bridge to connect;
This experiment uses the FPGA daughter board supporting the Plus1 7021 SOC practice platform to complete the relevant experiment. The experiment is carried out in loopback mode, which is to connect the TX and RX of the UART controller IP core design; The development tool of FPGA daughter board uses XILINX's Vivado integrated development environment (version number is 2018.3); in order to facilitate the connection of the user's own verification IP to the SOC system for verification, this experiment provides the corresponding design reference basic files, as follows
The corresponding connection between the design case and the pin connection of the SP7021 motherboard and FPGA daughter board is shown in the following table: 1: U20B on the main board is connected to J2 of the FPGA daughter board (Pin pin corresponding, such as 1-51 ...), providing the data transmission channel between the Plus1 main chip on the main board and the FPGA
Design Demo | FPGA daughter board | SP7021 mother board | |||
uart_apb | J2 | U1E | U20B | ||
Top Port Name | Schematic Name | FPGA I/O | Schematic Name | ||
| 1 | GND |
| 51 | GND |
| 2 | GND |
| 52 | GND |
FPGA_PAD[0] | 3 | B34_L24_N | T8 | 53 | FBIO_PAD_0 |
FPGA_PAD[43] | 4 | B34_L24_P | R8 | 54 | FBIO_PAD_1 |
| 5 | VIN |
| 55 | VCC(3.3V) |
| 6 | VCCIO34 |
| 56 | VCC(3.3V) |
FPGA_PAD[1] | 7 | B34_L21_N | V9 | 57 | FBIO_PAD_2 |
FPGA_PAD[42] | 8 | B34_L21_P | U9 | 58 | FBIO_PAD_3 |
FPGA_PAD[2] | 9 | B34_L18_N | N6 | 59 | FBIO_PAD_4 |
FPGA_PAD[41] | 10 | B34_L18_P | M6 | 60 | FBIO_PAD_5 |
FPGA_PAD[3] | 11 | B34_L22_N | U6 | 61 | FBIO_PAD_6 |
FPGA_PAD[40] | 12 | B34_L22_P | U7 | 62 | FBIO_PAD_7 |
FPGA_PAD[4] | 13 | B34_L20_N | V6 | 63 | FBIO_PAD_8 |
FPGA_PAD[39] | 14 | B34_L20_P | V7 | 64 | FBIO_PAD_9 |
FPGA_PAD[5] | 15 | B34_L23_N | T6 | 65 | FBIO_PAD_10 |
FPGA_PAD[38] | 16 | B34_L23_P | R7 | 66 | FBIO_PAD_11 |
FPGA_PAD[6] | 17 | B34_L10_N | V4 | 67 | FBIO_PAD_12 |
FPGA_PAD[37] | 18 | B34_L10_P | V5 | 68 | FBIO_PAD_13 |
FPGA_PAD[7] | 19 | B34_L19_P | R6 | 69 | FBIO_PAD_14 |
FPGA_PAD[36] | 20 | B34_L19_N | R5 | 70 | FBIO_PAD_15 |
FPGA_PAD[8] | 21 | B34_L8_P | U4 | 71 | FBIO_PAD_16 |
FPGA_PAD[35] | 22 | B34_L8_N | U3 | 72 | FBIO_TCLK |
FPGA_PAD[9] | 23 | B34_L9_N | V2 | 73 | FBIO_RCLK |
FPGA_PAD[34] | 24 | B34_L9_P | U2 | 74 | FBIO_PAD_17 |
FPGA_PAD[10] | 25 | B34_L7_N | V1 | 75 | FBIO_PAD_18 |
FPGA_PAD[33] | 26 | B34_L7_P | U1 | 76 | FBIO_PAD_19 |
FPGA_PAD[11] | 27 | B34_L13_P | N5 | 77 | FBIO_PAD_20 |
FPGA_PAD[32] | 28 | B34_L13_N | P5 | 78 | FBIO_PAD_21 |
FPGA_PAD[12] | 29 | B34_L12_P | T5 | 79 | FBIO_PAD_22 |
FPGA_PAD[31] | 30 | B34_L12_N | T4 | 80 | FBIO_PAD_23 |
FPGA_PAD[13] | 31 | B34_L11_N | T3 | 81 | FBIO_PAD_24 |
FPGA_PAD[30] | 32 | B34_L11_P | R3 | 82 | FBIO_PAD_25 |
FPGA_PAD[29] | 33 | B34_L14_P | P4 | 83 | FBIO_PAD_26 |
FPGA_PAD[28] | 34 | B34_L14_N | P3 | 84 | FBIO_PAD_27 |
FPGA_PAD[14] | 35 | B34_L16_N | N4 | 85 | FBIO_PAD_28 |
FPGA_PAD[27] | 36 | B34_L16_P | M4 | 86 | FBIO_PAD_29 |
FPGA_PAD[15] | 37 | B34_L17_N | T1 | 87 | FBIO_PAD_30 |
FPGA_PAD[26] | 38 | B34_L17_P | R1 | 88 | FBIO_PAD_31 |
FPGA_PAD[16] | 39 | B34_L15_N | R2 | 89 | FBIO_PAD_32 |
FPGA_PAD[25] | 40 | B34_L15_P | P2 | 90 | FBIO_PAD_33 |
FPGA_PAD[17] | 41 | B34_L3_N | N1 | 91 | FBIO_PAD_34 |
FPGA_PAD[24] | 42 | B34_L3_P | N2 | 92 | FBIO_PAD_35 |
FPGA_PAD[18] | 43 | B34_L1_N | M1 | 93 | FBIO_PAD_RSTB |
FPGA_PAD[23] | 44 | B34_L1_P | L1 | 94 | EXT0_INT |
| 45 | VCCIO34 |
| 95 | VCC(3.3V) |
| 46 | VIN |
| 96 | VCC(3.3V) |
FPGA_PAD[19] | 47 | B34_L4_P | M3 | 97 | EXT1_INT |
FPGA_PAD[20] | 48 | B34_L4_N | M2 | 98 |
|
| 49 | GND |
| 99 | GND |
| 50 | GND |
| 100 | GND |
2: U20A on the motherboard is connected to J1 of the FPGA daughter board (Pin pins correspond to one, such as 1-1 ...), and the 42 pin IO (3.3v) of FPGA Bank 35 is extended via J17 for users to use
Design Demo | FPGA daughter board | SP7021 mother board | |||||
uart_apb | J1 | U1F | U20A | J17 | |||
Top Port Name | Schematic Name | FPGA I/O | Schematic Name | Schematic Name | |||
| 1 | GND |
| 1 | GND | 3 | GND |
| 2 | GND |
| 2 | GND | 4 | GND |
FPGA_TX | 3 | B35_L23_N | K1 | 3 | B35_L23_N | 5 | B35_L23_N |
| 4 | B35_L23_P | K2 | 4 | B35_L23_P | 6 | B35_L23_P |
| 5 | VIN |
| 5 | VIN | 1 | VCC |
| 6 | VCCIO35 |
| 6 | VCCIO35 | 2 | VCC |
FPGA_RX | 7 | B35_L15_N | G2 | 7 | B35_L15_N | 7 | B35_L15_N |
| 8 | B35_L15_P | H2 | 8 | B35_L15_P | 8 | B35_L15_P |
| 9 | B35_L13_N | F3 | 9 | B35_L13_N | 9 | B35_L13_N |
| 10 | B35_L13_P | F4 | 10 | B35_L13_P | 10 | B35_L13_P |
| 11 | B35_L12_N | D3 | 11 | B35_L12_N | 11 | B35_L12_N |
| 12 | B35_L12_P | E3 | 12 | B35_L12_P | 12 | B35_L12_P |
| 13 | B35_L22_P | J3 | 13 | B35_L22_P | 13 | B35_L22_P |
| 14 | B35_L22_N | J2 | 14 | B35_L22_N | 14 | B35_L22_N |
| 15 | B35_L17_N | G1 | 15 | B35_L17_N | 15 | B35_L17_N |
| 16 | B35_L17_P | H1 | 16 | B35_L17_P | 16 | B35_L17_P |
| 17 | B35_L18_N | E1 | 17 | B35_L18_N | 17 | B35_L18_N |
| 18 | B35_L18_P | F1 | 18 | B35_L18_P | 18 | B35_L18_P |
| 19 | B35_L14_N | D2 | 19 | B35_L14_N | 19 | B35_L14_N |
| 20 | B35_L14_P | E2 | 20 | B35_L14_P | 20 | B35_L14_P |
| 21 | B35_L16_P | C2 | 21 | B35_L16_P | 21 | B35_L16_P |
| 22 | B35_L16_N | C1 | 22 | B35_L16_N | 22 | B35_L16_N |
| 23 | B35_L9_N | A1 | 23 | B35_L9_N | 23 | B35_L9_N |
| 24 | B35_L9_P | B1 | 24 | B35_L9_P | 24 | B35_L9_P |
| 25 | B35_L10_P | B3 | 25 | B35_L10_P | 25 | B35_L10_P |
| 26 | B35_L10_N | B2 | 26 | B35_L10_N | 26 | B35_L10_N |
| 27 | B35_L8_N | A3 | 27 | B35_L8_N | 27 | B35_L8_N |
| 28 | B35_L8_P | A4 | 28 | B35_L8_P | 28 | B35_L8_P |
| 29 | B35_L11_N | D4 | 29 | B35_L11_N | 29 | B35_L11_N |
| 30 | B35_L11_P | D5 | 30 | B35_L11_P | 30 | B35_L11_P |
| 31 | B35_L3_N | A5 | 31 | B35_L3_N | 31 | B35_L3_N |
| 32 | B35_L3_P | A6 | 32 | B35_L3_P | 32 | B35_L3_P |
| 33 | B35_L2_N | B6 | 33 | B35_L2_N | 33 | B35_L2_N |
| 34 | B35_L2_P | B7 | 34 | B35_L2_P | 34 | B35_L2_P |
| 35 | B35_L7_N | B4 | 35 | B35_L7_N | 35 | B35_L7_N |
| 36 | B35_L7_P | C4 | 36 | B35_L7_P | 36 | B35_L7_P |
| 37 | B35_L1_N | C5 | 37 | B35_L1_N | 37 | B35_L1_N |
| 38 | B35_L1_P | C6 | 38 | B35_L1_P | 38 | B35_L1_P |
| 39 | B35_L5_N | E5 | 39 | B35_L5_N | 39 | B35_L5_N |
| 40 | B35_L5_P | E6 | 40 | B35_L5_P | 40 | B35_L5_P |
| 41 | B35_L6_N | D7 | 41 | B35_L6_N | 41 | B35_L6_N |
| 42 | B35_L6_P | E7 | 42 | B35_L6_P | 42 | B35_L6_P |
| 43 | B35_L19_P | G6 | 43 | B35_L19_P | 43 | B35_L19_P |
| 44 | B35_L19_N | F6 | 44 | B35_L19_N | 44 | B35_L19_N |
| 45 | VCCIO35 |
| 45 | VCCIO35 | 49 | VCC |
| 46 | VIN |
| 46 | VIN | 50 | VCC |
| 47 | B35_L4_N | C7 | 47 | B35_L4_N | 45 | B35_L4_N |
| 48 | B35_L4_P | D8 | 48 | B35_L4_P | 46 | B35_L4_P |
| 49 | GND |
| 49 | GND | 47 | GND |
| 50 | GND |
| 50 | GND | 48 | GND |
6.2 Implementation of System Software Platform for UART Controller IP Design Experiment Project
In the IDE environment, as shown below, select the sp7021 project name, click the right mouse button and select Copy in the pop-up menu
Next, select the sp7021 project name again
Click the right mouse button and select Paste in the pop-up menu, the following picture appears
Fill in the uart_apb in the Project name box to complete the establishment of the uart_apb project name and directory, as shown below
Next, you need to copy all the files and folders under the installation directory \SP7021\example\uart_apb to the uart_apb project directory built above (the path is: installation directory \SP7021\workspace\uart_apb\), the file with the same name is selected to be overwritten, so that the UART The program codes main.c; uart.c; uart.h required for the IP design practice of the controller are placed in the following paths:
1） In the install directory \SP7021\workspace\uart_apb\main.c
2） In the install directory \SP7021\workspace\uart_apb\testapi\util\uart.c
3） In the install directory \SP7021\workspace\uart_apb\include\util\uart.h
Finally, as shown in the figure below, the mouse selects the red box 1, then clicks the right mouse button to appear the drop-down menu, and then selects the red box 2, refresh the copy action just now, so that the file just copied can be displayed in the IDE environment
main.c
int main(void)
{
printf("Build @%s, %s\n", __DATE__, __TIME__);
hw_init();
sys_init();
fbio_init();
uart_ctl();
disp_hdmi_init();
uart_interrupt_init(); /*uart interrupt configure */
sp_interrupt_setup(); /* system interrupt manager module init */
printf("UART IP test ready ");
while(1)
{
unsigned int i;
for (i = 0; i < 256; i++)
{
while(1)
{
if((uart_reg->LSR&0x20)==0x20)
{
uart_reg->SER=0x3f;
uart_reg->TX_FIFO=i;
printf("@tx_data [%d]\n", i);
uart_reg->SER=0x3e;
break;
}
}
}
}
}
Compared with the digital tube control IP experiment, the uart_ctl () function is added to complete the configuration and initialization of the UART, as explained below.
void uart_ctl()
{
uart_reg->LCR=0x20;
printf("@LCR[%x]\n", temp);
uart_reg->SER=0x3e;
printf("@SER[%x]\n", temp);
///////////////// system clock is 65.057MHz//////65057000/16/buad//////
uart_reg->BUAD_CNT=0x1A9; //9600
printf("@BUAD_CNT[%x]\n", temp);
}
Realize the configuration and initialization operation of UART control IP as follows:
uart_reg->LCR=0x20;
Set UART to 8bit data bit, 1bit stop bit, no parity bit;
uart_reg->SER=0x3e;
Set the UART interrupt to: allow interrupts to be generated after receiving data is complete; disable interrupts to be generated after data transmission is complete; prohibit stop bits from receiving data and generate interrupts when the check bit is wrong; disable interrupts when receiving data FIFO is full; Generate an interrupt;
uart_reg->BUAD_CNT=0x1A9;
Set the UART baud rate to 9600;
The following introduces while (1) loop
if((uart_reg->LSR&0x20)==0x20) : Judge that the received data FIFO is empty
uart_reg->SER=0x3f; Forbid receiving data interruption;
uart_reg->TX_FIFO=i; Send data i to TX FIFO;
uart_reg->SER=0x3e; Allow interrupt generation after receiving data
uart.c
#include "common_all.h"
#include "cache.h"
#include "sp_interrupt.h"
#define FPGA_EXT0_INT (29)
#define FPGA_EXT1_INT (30)
static unsigned int g_repeat_cnt = 0;
unsigned int rx_data;
void fpga_ext0_interrupt_control_mask(int enable)
void fpga_ext1_interrupt_control_mask(int enable)
static void fpga_ext0_isr_cfg()
static void fpga_ext1_isr_cfg()
void fpga_ext0_callback(void)
void fpga_ext1_callback(void)
void uart_interrupt_init ()
void fpga_ext1_test_init()
Compared with the LED.c of the LED control IP experiment, the structure is similar, the difference is that the interrupt handler is different, as explained below
void fpga_ext0_callback(void)
{
rx_data=uart_reg->RX_FIFO;
printf("@rx_data [%d]\n", rx_data);
uart_reg->LSR=0x0;
}
The role of this interrupt handler: take the 8bit data received by the RX FIFO; then clear the status flag bit of this interrupt, so that the serial reception and transmission experiments of 1byte data are completed.
uart.h
#ifndef __FPGAINT_H__
#define __FPGAINT_H__
#define FBIO_BASE_ADDR 0x70000000
typedef struct uart_reg_s {
unsigned long LCR;
unsigned long SER;
unsigned long BUAD_CNT;
unsigned long LSR;
unsigned long RX_FIFO;
unsigned long TX_FIFO;
} uart_reg_t;
extern uart_reg_t *uart_reg;
void uart_interrupt_init ();
void fpga_ext1_test_init();
#endif // __FPGAINT_H__
Defined UART control IP related registers
6.3 Run Program code
After compile in the Plus1 IDE environment, download to the platform and see the following information in the terminal window
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