Full duplex asynchronous serial communication UART controller IP design
Case download:
uart_apb.zip
1 Design Brief
UART is short for Universal Asynchronous Receiver and Transmitter. Used for communication between serial input and serial output devices. Serial transmission comes at the cost of speed, in exchange for a reduction in cost and complexity of wiring. UART provides synchronization of serial asynchronous received data, parallel-to-serial and serial-to-parallel data conversion of the transmitter and receiver, for digital systems that need to convert serial data streams to parallel data, these functions Is essential. Synchronization of the serial data stream is achieved by adding start and stop bits to the transmitted data to form a data character. Data integrity is achieved by appending a parity bit to the data character, which is provided by the receiver Check this parity bit to check whether there is any transmission bit error. It is mainly composed of data bus interface, control logic, baud rate generator, sending part and receiving part.
1.1 Protocol
The communication protocol is the regulation of the data transmission method, including the definition of the data format and the definition of the data bits. Both parties must follow a unified communication protocol. The following is the transmission format of character data specified by the asynchronous serial communication protocol. In asynchronous communication, data is transmitted frame by frame (including a character code or a byte of data), and the data format of each frame is shown in the following figure
In the frame format, a character is composed of four parts: start bit, data bit, parity bit, and stop bit.
(1)、Start bit
The start bit (low level "0") occupies only one bit and informs the receiving device that a character to be received starts to arrive. Logic 1 state when no data is being transmitted on the communication line. When the sending device wants to send a character data, first add a logic 0 signal, this logic low level is the start bit, the receiving end continuously detects the state of the line, the receiving device detects this logic low level and starts Ready to accept data bit signals. The start bit of the character is also used to synchronize the clock of the receiving end to ensure that the subsequent reception can be performed correctly. The start bit enables the device to synchronize, and both parties must coordinate the synchronization before transmitting the data bit.
(2)、Data bit
The start bit is immediately followed by the data bit, which can be 5, 6, 7, or 8 bits. When the receiving device receives the start bit, it immediately receives the data bit. These data bits are received into the shift register and constitute the transmitted data characters. In the transmission of character data, the data bits are sent from the least significant bit and are sequentially converted into data in the receiving device.
(3)、Parity bit
After the data bits are sent, parity bits can be sent. The parity bit only occupies one bit, and the parity bit can be omitted, or this bit can be omitted, or this bit can also be used to determine the nature of the information represented by the characters in this frame (address / data, etc.) Parity check belongs to limited error detection, and both parties in communication must agree on a consistent parity check method. If you select even parity, the number of logic 1s that make up the data bits and parity bits must be even; if you select odd parity, then the number of logic 1s must be odd.
(4)、Stop bit convention
The stop bit is sent after the parity bit or data bit (when there is no parity check). The stop bit is the end mark of a character data, which can be a high level of 1, 5, or 2 bits. After receiving the stop bit, the receiving end indicates that the previous character has been transmitted, and at the same time, it is also ready to receive the next character. If it receives 0 again, the new character begins to transmit. If the stop bit is not followed by a character, the line level is kept high ("1"), which is the idle bit. After the receiving device receives the stop bit, the logic 1 state is restored on the communication line until the start bit of the next character data arrives.
(5)、Baud rate setting
All bit signals transmitted on the communication line maintain a consistent signal duration, and the signal duration of each bit is determined by the data transmission speed, that is, measured by how many binary bits per second, this speed is called the baud rate. If the data is transmitted on the communication line with 300 binary bits per second, the transmission speed is 300 baud, which is usually recorded as 300 b/s.
(6)、Handshake signal agreement
When the computer and modem exchange data, they often use some signal lines as a prerequisite for exchanging data. When the conditions are met, the data is allowed to be transmitted; when the conditions are not met, they are in a waiting state and wait until the signal that allows data transmission occurs. Data transmission begins again.
1.2 Serial-to-parallel conversion
Serial communication is to convert the parallel data to be transmitted inside the computer into serial data and transmit it through a communication line; then convert the received serial data into parallel data and send it to the computer. Before the computer serially sends data, the parallel data inside the computer is sent to the shift register and shifted out bit by bit, converting the parallel data into serial data. As shown below
When receiving data, the serial data from the communication line is sent to the shift register, and after being shifted and saved to 8 bits, it is sent to the computer in parallel
1.3 Data sampling
When the receiver receives data, the internal clock frequency of the UART is often higher than the external data input frequency. When the receiver starts to receive the signal, if the frequency of the internal clock is close to or less than the external data transmission frequency, when the receiver receives data, it is likely that the data will not be collected at the edge of data sampling, or the wrong data will be collected. The sampling frequency can be set to 8 times, 16 times the external data transmission frequency. The UART uses 16 times the external clock frequency, and the sampled waveforms are as follows:
In this example, through the research of the UART bus protocol, the UART Controller IP is designed to familiarize with the design and verification of the UART IP core
2 Design specifications
l Support AMBA APB2.0 BUS interface.
l Support 5/6/7/8 bits data (packet) transmit and receive.
l Support odd, even or none parity bit generation and declaration.
l Support 1, 1.5 or 2 stop bits generation and declaration.
l Support baud rate configuration (4800bps, 9600bps, 38400bps and 115200bps).
l Support 4 types depth RX FIFO and TX FIFO.
l Support software reset and enable.
l Support polling status – FIFO full and empty, parity check error, stop bit check error.
l Programmable interrupt enable control.
l Support the SW write clear the interrupt.
.
3 I/O Ports Description
3.1 APB Register Bus Interface
Name | Direction | Width | Description |
PSEL | Input | 1 | APB Bus Selected Active high to select CTRL group registers. |
PWRITE | Input | 1 | APB Bus Write Enable Active high to enable register bus write operation. Active low to enable register bus read operation. |
PENABLE | Input | 1 | APB Bus Enable Active high to select CTRL group registers. |
PWDATA | Input | 32 | APB Write Data Bus 32 bit data with [31] is most significant bit. |
PADDR | Input | 5 | APB Bus Address 5 bit address bus with [4] is most significant bit. |
PRDATA | Output | 32 | APB Read Data Bus Register read data bus, [31] is most significant bit. Valid when SL_APB_ACK is active. |
3.2 Interrupt Line
Name | Direction | Width | Description |
INT_B | Output | 1 | Interrupt Low active. When finished a operation, INT_B will be active, such as received a packet or error case happened. |
3.3 System Clock and Reset
Name | Direction | Width | Description |
SYSCLK | Input | 1 | System Clock Free running clock, all registers must be synchronous with SYSCLK. |
RST_B | Input | 1 | System Reset Low active. When this pin is asserted, all flip-flops must be reset to their default value. |
3.4 UART interface
Name | Direction | Width | Description |
RX | Input | 1 | Serial Data input |
TX | output | 1 | Serial Data output |
4 Registers File
4.1 Registers List
Address | Name | Access | Description |
5’h00 | LCR | RW | Line Control Register |
5’h01 | SER | RW | Software Enable Register |
5’h02 | BAUD_CNT | RW | Baud-rate Configuration Register |
5’h03 | LSR | RW | Line State Register |
5’h04 | RX_FIFO | RO | RX FIFO Register |
5’h05 | TX_FIFO | RW | TX FIFO Register |
4.2 Line Configuration Register (LCR, Addr = 5’h0)
Default value: 0x0000_0000
Register Bits | Name | Function Description |
1:0 | WORD_SEL | Word Length Select of the UART 00 : 8 bit data transmit and receive 01 : 7 bit data transmit and receive 10 : 6 bit data transmit and receive 11 : 5 bit data transmit and receive |
3:2 | STOP_SEL | Stop Bit Length of the UART 00 : 1 cycle stop bit 01 : 1.5 cycle stop bit 10 : 2 cycle stop bit Default : 1 cycle stop bit |
5:4 | PTY_SEL | Parity Select of the UART 00 : even parity 01 : odd parity 10 : no parity Default : even parity |
31:6 | RSV | Reserved |
4.3 Software Enable Register (SER, Addr = 5’h1)
Default Value: 0x0000_003f
Register Bits | Name | Function Description |
0 | RX_DONE_EN | Data Ready Interrupt Enable Low active, when this bit is 1, Data Ready will not assert interrupt. |
1 | TX_DONE_EN | Transmitted Complete Interrupt Enable Low active, when this bit is 1, Transmitted Complete will not assert interrupt. |
2 | PTY_ERR_EN | Parity Error Interrupt Enable Low active, when this bit is 1, Parity Error will not assert interrupt. |
3 | STOP_ERR_EN | Stop Bit Error Interrupt Enable Low active, when this bit is 1, Stop Bit Error will not assert interrupt. |
4 | RX_FULL_EN | RX FIFO Full interrupt Enable Low active, when this bit is 1, TRX FIFO full will not assert interrupt. |
5 | TX_EMPTY_EN | TX FIFO Empty interrupt Enable Low active, when this bit is 1, TX FIFO empty will not assert interrupt. |
6 | SW_RST | Soft Reset UART High active , the UART will reset when Master writing 1 to this bit |
7 | RX_EN | Receiver FSM Stop Low active , the Receiver will not work when this bit is 1 |
8 | TX_EN | Transmitter FSM Stop Low active , the Transmitter will not work when this bit is 1 |
31:9 | RSV | Reserved |
4.4 Baud-rate Configuration Register (BAUD_CNT, Addr = 5’h2)
Default Value: 0x0000_0000
Register Bits | Name | Function Description |
31:0 | BAUD_CNT | Baud Rate configure data Store the count value of baud rate generation |
4.5 Line State Register (LSR, Addr = 5’h3)
Default value: 0x0000_0000
Register Bits | Name | Function Description |
0 | RX_DONE | Data Ready High active, the flag of the interrupt that Received a complete packet. The interrupt will be cleaned when this bit is written 0 by master. |
1 | TX_DONE | Transmitted Data Complete High active, the flag of the interrupt that Transmitted a complete packet. The interrupt will be cleaned when this bit is written 0 by master. |
2 | PTY_ERR | Parity Error High active. The interrupt flag that Parity error. The interrupt will be cleaned when this bit is written 0 by master. |
3 | STOP_ERR | Stop Bit Error High active. The interrupt flag that Stop bit error. The interrupt will be cleaned when this bit is written 0 by master. |
4 | RX_FULL | RX FIFO Full High active. The interrupt flag that RX FIFO full. The interrupt will be cleaned when master reads out a data once. |
5 | RX_EMPTY | RX FIFO Empty High active. The flag that the RX FIFO empty |
6 | TX_FULL | TX FIFO Full High active. The flag that the TX FIFO full |
7 | TX_EMPTY | TX FIFO Empty High active. The flag of the interrupt that TX FIFO empty. The interrupt will be cleaned when master writes a data once. |
31:8 | RSV | Reserved |
4.6 RX FIFO Register (RX_FIFO, Addr = 5’h4)
Default Value: 0x00
Register Bits | Name | Function Description |
7:0 | RX_FIFO | Read Data Buffer The depth is 4. Store the data written to Receiver buffer register. |
4.7 TX FIFO Register (TX_FIFO, Addr =5’h5)
Default Value: 0x00
Register Bits | Name | Function Description |
7:0 | TX_FIFO | Write Data Buffer The depth is 4. Store the data written to Transmitter buffer register. |
5 Functional Description
5.1 UART Structure
Interface model: communicate with CPU, configure the UART.
FIFO: store data which will be transmitted or received
Transmit/Receive register: transmit or receive the data stored in the FIFO.
Baud rate occur: occur the clock for transmitter and receiver
5.2 UART Receiver FSM
Current State | Function | Next Status | Jump Condition |
IDLE | Wait start signal. | SHIFT | Start bit detected right and receiver buffer register isn’t full |
IDLE | RX_EN enable or start bit not detected | ||
SHIFT | Receive data | STOP | Last data bit and parity disable |
PARITY | Last data bit and parity enable | ||
SHIFT | Not last data bit | ||
PARITY | Odd/even parity check | STOP | Parity check done |
STOP | Stop bit check | IDLE | Check right, then jump to IDLE Or check right wrong ,INT_B enable, then jump to IDLE |
5.3 UART Transmitter FSM
Current State | Function | Next Status | Jump Condition |
IDLE | Wait for transmitting | START | TX_FIFO is not empty |
IDLE | TX_FIFO is empty or TX_EN enable | ||
START | Transmit start bit | SHIFT | Transmit done |
SHIFT |