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SP7350 PCB Design Guidelines
SP7350 PCB Design Guidelines
This document serves as a comprehensive guide for PCB design tailored specifically for the SP7350. It supplements the application circuits provided for the SP7350. Chapter 1 outlines essential guidelines for high-speed signal routing, while Chapter 2 presents technical data or criteria for designing SP7350 PCBs.
Table of Contents
- 1 1. General Guidelines for High-Speed Signal Routing
- 1.1 1.1 General Guidelines
- 1.2 1.2 Practical Techniques
- 2 2. Technical Data or Criteria for Designing SP7350 PCB
- 2.1 2.1 6-Layer PCB Stack Up
- 2.2 2.2 High-Current Digital Powers
- 2.3 2.3 DDR SDRAM
- 2.3.1 2.3.1 LPDDR4 for 3200 Mbps
- 2.3.1.1 2.3.1.1 Target Impedance for Powers
- 2.3.1.2 2.3.1.2 DQ to DQ Mismatch Within a Byte
- 2.3.1.3 2.3.1.3 DQ to DQS Skew
- 2.3.1.4 2.3.1.4 CS, CKE, ODT, CA to CK Skew
- 2.3.1.5 2.3.1.5 DQS to CK Skew
- 2.3.1.6 2.3.1.6 DQS/DQS# and CK/CK# Intra-pair Skew
- 2.3.1.7 2.3.1.7 Trace Impedance
- 2.3.1.8 2.3.1.8 SI Criteria
- 2.3.1.9 2.3.1.9 PI Criteria
- 2.3.1.10 2.3.1.10 Reference Layout
- 2.3.2 2.3.2 DDR4 for 2666 Mbps
- 2.3.2.1 2.3.2.1 Target Impedance for Powers
- 2.3.2.2 2.3.2.2 DQ to DQ Mismatch
- 2.3.2.3 2.3.2.3 DQ to DQS Skew
- 2.3.2.4 2.3.2.4 CS, CKE, ODT, Command and Address to CK Skew
- 2.3.2.5 2.3.2.5 DQS to CK Skew
- 2.3.2.6 2.3.2.6 DQS/DQS# and CK/CK# Intra-pair Skew
- 2.3.2.7 2.3.2.7 Trace Impedance
- 2.3.2.8 2.3.2.8 SI Criteria
- 2.3.2.9 2.3.2.9 PI Criteria
- 2.3.3 2.3.3 DDR3 for 1866 Mbps
- 2.3.3.1 2.3.3.1 Target Impedance for Powers
- 2.3.3.2 2.3.3.2 DQ to DQ Mismatch
- 2.3.3.3 2.3.3.3 DQ to DQS Skew
- 2.3.3.4 2.3.3.4 CS, CKE, ODT, Command and Address to CK Skew
- 2.3.3.5 2.3.3.5 DQS to CK Skew
- 2.3.3.6 2.3.3.6 DQS/DQS# and CK/CK# Intra-pair Skew
- 2.3.3.7 2.3.3.7 Trace impedance
- 2.3.3.8 2.3.3.8 SI Criteria
- 2.3.3.9 2.3.3.9 PI Criteria
- 2.3.4 2.3.4 DDR3L for 1866 Mbps
- 2.3.4.1 2.3.4.1 Target Impedance for Powers
- 2.3.4.2 2.3.4.2 DQ to DQ Mismatch
- 2.3.4.3 2.3.4.3 DQ to DQS Skew
- 2.3.4.4 2.3.4.4 CS, CKE, ODT, Command and Address to CK Skew
- 2.3.4.5 2.3.4.5 DQS to CK Skew
- 2.3.4.6 2.3.4.6 DQS/DQS# and CK/CK# Intra-pair Skew
- 2.3.4.7 2.3.4.7 Trace Impedance
- 2.3.4.8 2.3.4.8 SI Criteria
- 2.3.4.9 2.3.4.9 PI Criteria
- 2.3.1 2.3.1 LPDDR4 for 3200 Mbps
- 2.4 2.4 High-speed Devices
- 2.4.1 2.4.1 SPI-NOR Flash
- 2.4.1.1 2.4.1.1 General Rules
- 2.4.1.2 2.4.1.2 D[3:0] to CLK Skew
- 2.4.1.3 2.4.1.3 Trace Impedance
- 2.4.2 2.4.2 SPI-NAND Flash
- 2.4.2.1 2.4.2.1 General Rules
- 2.4.2.2 2.4.2.2 D[3:0] to CLK Skew
- 2.4.2.3 2.4.2.3 Trace Impedance
- 2.4.3 2.4.3 8-bit NAND Flash
- 2.4.3.1 2.4.3.1 General Rules
- 2.4.3.2 2.4.3.2 Signals Skew
- 2.4.3.3 2.4.3.3 Trace Impedance
- 2.4.4 2.4.4 eMMC Device
- 2.4.4.1 2.4.4.1 General Rules
- 2.4.4.2 2.4.4.2 Skew of CLK, CMD, DQ and DS Signals
- 2.4.4.3 2.4.4.3 Trace Impedance
- 2.4.4.4 2.4.4.4 Reference Layout
- 2.4.5 2.4.5 USB2.0
- 2.4.5.1 2.4.5.1 General Rules
- 2.4.5.2 2.4.5.2 DP/DM Differential-pair Mismatch
- 2.4.5.3 2.4.5.3 Trace Impedance
- 2.4.5.4
- 2.4.1 2.4.1 SPI-NOR Flash