User Manual of C3V-W (LPDDR4) Core Board
- Wells Lu
This manual serves as a comprehensive guide for utilizing the C3V-W (LPDDR4) Core Board, a cutting-edge hardware solution tailored for diverse applications. The C3V-W (LPDDR4) Core Board integrates a robust set of components, including the C3V-W chip, an 8 GiB eMMC flash, a 4 GiB LPDDR4 SDRAM, many switching-mode and linear power regulators, and two 120-pin 0.4mm-pitch connectors essential for interfacing with an IO board. Crafted with precision using state-of-the-art 6-layer, HDI PCB technology, this board ensures optimal performance, with LPDDR4 capable of operating at speeds up to 3200 MT/s and eMMC reaching speeds of up to HS200. Customers have the flexibility to design their IO boards tailored to specific applications, leveraging cost-effective 4-layer PCBs. Refer to functional block diagram of C3V-W (LPDDR4) Core Board below:
Contents
Pictures of C3V-W (LPDDR4) Core Board
The C3V-W (LPDDR4) Core Board is compact, measuring 40mm x 55mm, ensuring efficient integration into various systems. Refer to pictures of C3V-W (LPDDR4) Core Board below: Top-view, Bottom-view and Top-view with heat-sink:
IO Connectors
All IO pins, except for the eMMC device, are conveniently accessible through the 120-pin 0.4mm-pitch connectors. Please refer to the pin-assignment diagrams for Connector CN1 and Connector CN2 for detailed pinout information.
Pin-assignment of Connector CN1
Pin-assignment of Connector CN2
Powers
The C3V-W (LPDDR4) Core Board is powered by a +5V power source. To guarantee stable power distribution and facilitate optimal performance and energy efficiency, the board incorporates advanced internal power regulation circuitry.
Integrated with both DC2DC and linear power regulators, the Core Board efficiently generates 12 distinct power supplies. These supplies are intelligently divided into 5 power domains, each catering to specific functional requirements of the board.
AO Power Domain:
The Always-On (AO) Power Domain ensures CM4 remain operational even when other power domains are deactivated. Key power supplies include:
AO_0V8: 0.8V
AO_1V8: 1.8V
AO_3V3: 3.3V
DRAM_VDDQ: 1.1V
When other power domains are turned off, the AO Power Domain persists, ensuring that CM4 system functionalities are sustained. During this state, the image of the Linux kernel is suspend to (stored in) DRAM, allowing for rapid restoration to normal operation within a few seconds upon user request.
Video Codec Power Domain:
This domain powers the video codec and can be selectively disabled to conserve energy when the video codec is not in use.
VDD_VV: 0.8V
NPU Power Domain:
The NPU Power Domain powers the Neural Processing Unit (NPU) and can be toggled off when not required, minimizing power consumption..
VDD_NPU: 0.85V
CPU Power Domain:
The CPU Power Domain is responsible for supplying power to the CPU and is equipped with features to optimize power usage. Notably, it supports Dynamic Voltage and Frequency Scaling (DVFS), allowing for dynamic adjustments in voltage and frequency based on workload demands, thereby enhancing power efficiency.
When the CPU is not actively engaged, the CPU Power Domain can be deactivated to conserve power consumption, contributing to overall energy savings. Key voltage specifications for the CPU Power Domain:
VDD_CA55: Adjustable within the range of 0.7V to 1.0V
Voltage control within this domain is facilitated through the I2C interface, providing a convenient means to manage and regulate power settings according to system requirements.
Main Power domain:
The Main Power Domain serves as the backbone of the system, encompassing various components and peripherals essential for system operation. It provides crucial voltages necessary for the operation of peripherals, ensuring seamless functionality across the system.
SYS_0V8 = DPHY_0V8 = MIPI_0V8: 0.8V
SYS_1V8: 1.8V
SYS_3V: 3.0V
SYS_3V3: 3.3V
SYS_5V: 5.0V
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