6.1 General Description
The SP7021 ARM CPU uses a 32-bit memory map for all accesses. The memory map shows in Table 6-1. At reset, the memory is configured by the internal BootROM mirrored at address 0xFFFF0000 where the ARM will start execution.
Name | CPU view | memory range size | Description |
|---|---|---|---|
DRAM | 0x0000_0000 - 0x1FFF_FFFF | 512MB | DRAM memory area |
Reserved | 0x2000_0000 - 0x6FFF_FFFF | 1280MB | |
FPGA Device | 0x7000_0000 - 0x77FF_FFFF | 128MB | For FPGA application Exchange data with external device (FPGA) via FBIO slave port |
Reserved | 0x7800_0000 - 0x97FF_FFFF | 512MB | |
SPI-NOR Flash (External ROM) | 0x9800_0000 - 0x9BFF_FFFF | 64MB | External boot ROM area |
Device Register | 0x9C00_0000 - 0x9DFE_FFFF | 32MB | Device Register Space, refer to Section 6.2 Device Register Map for more detail |
Reserved | 0x9DFF_0000 - 0x9DFF_FFFF | 64KB | |
| Internal BootROM | 0x9E00_0000 - 0x9E0F_FFFF | 1MB | Internal boot ROM area |
Reserved | 0x9E10_0000 - 0x9E7F_FFFF | 7MB | |
Internal SRAM (CB_DMA0) | 0x9E80_0000 - 0x9E81_FFFF | 128KB | Access exceeds the CBDMA range, the Write data will be discarded, Read will get the error data, and trigger interrupt |
Internal SRAM (CB_DMA1) | 0x9E82_0000 - 0x9E82_0FFF | 4KB | Access exceeds the CBDMA range, the Write data will be discarded, Read will get the error data, and trigger interrupt |
Reserved | 0x9EA0_0000 - 0x9EAF_FFFF | 1MB | |
Reserved | 0x9EC0_0000 - 0x9EFF_FFFF | 4MB | |
Hivec_ROM | 0xFFFF_0000 - 0xFFFF_FFFF | 64KB | In the Internal BootROM mode, CPU address will remap from 0xFFFF_xxxx to 0x9E00_xxxx (64KB range) after reset. In the External Boot from SPI_NOR mode, CPU address will transfer from 0xFFFF_xxxx to 0x9800_xxxx (64KB range) |
Table 6-1 Memory Map
6.2 Device Register Map
The device register space, located in the memory map address range of 0x9C000000~0x9DFEFFFF, control most SP7021 functions. The device registers is separated into 2 segments, one is called RGST table (Register table) which base address is 0x9C000000, another one is called AMBA table (Advanced Microcontroller Bus Architecture table) which base address is 0x9C100000. Table 6-2 /6-3 show the group number with memory map start address of each module.
Table 6-2 Chip control registers group list of RGST table
Memory Map Start Address | Data Width | Module | Chapter Link |
|---|---|---|---|
0x9C101000 | 32 | BCH | 22. BCH |
0x9C102000 | 32 | USB0 HOST | 13. Universal Serial Bus (USB) |
0x9C103000 | 32 | USB1 HOST | 13. Universal Serial Bus (USB) |
0x9C106000 | 32 | FBIO | |
0x9C108000 | 32 | Ethernet Switch | 14. Ethernet Switch |
| 0x9C108200 | 32 | Ethernet Switch | 14. Ethernet Switch |
Table 6-3 Chip control registers group list of AMBA table
6.3 DRAM area
The DRAM area located in memory map address range 0x00000000~0x1FFFFFFF.
6.4 FPGA Device area
The FPGA device area located in memory map address range 0x70000000~0x77FFFFFF, it used for FPGA application.
6.5 External ROM area
The External ROM area located in memory map address range 0x98000000~0x9BFFFFFF. In the External Boot ROM mode, CPU address will transfer from 0xFFFF_xxxx to 0x9800_xxxx and progress boot procedure.
6.6 Internal Boot ROM area
The Internal Boot ROM area located in memory map address range 0x9E000000~0x9E0FFFFF. In the Internal Boot ROM mode, CPU address will transfer from 0xFFFF_xxxx to 0x9E00_xxxx and progress boot procedure.
6.7 Internal SRAM area
The Internal SRAM area include CB_DMA0 and CB_DMA1 which located in memory map address range 0x9E800000~0x9E81FFFF and 0x9E820000~0x9E820FFF. Internal SRAM in addition to the temporary storage data in operation, another function is to let the data have some place before the system has initialized DRAM. In addition, this hardware also provides DMA function, which is quite flexible.
6.8 Hivec_ROM area
The Hivec_ROM area located in memory map address range 0xFFFF0000~0xFFFFFFFF, it used for remap Boot ROM address.