25. CBDMA

25.1 Introduction

The CB_DMA provides CBUS (CPU Bus) MASTER storage space for use as DATA RAM, and also provides DMA function. DATA RAM can be used without any settings, and reading and writing is very efficient. Both d DATA RAM and CACHE are two forms of on-chip memory. The goal is to improve system performance (read-write speed is faster than DRAM), but the implementation is completely different. The cache is fully automatic. Software colleagues can be used as no such hardware. For data ram, software needs to specify the location to access.
Data ram In addition to the temporary storage data in operation, another function is to let the system have some place to store the data before the system has been initialized. In addition, this hardware also provides DMA function, which is quite flexible. Let software In the future, there is an opportunity to use hardware acceleration in critical places to perform memset, read/write/move the flexibility of large amounts of data.
SP7021 CB_DMA support internal SRAM that size is 128Kbytes. CB_DMA is accessed by DMA_CTRL (master) and also access to DRAM (slave). CB_DMA also support security function.
The control registers locate at RGST table Group 26 which memory map in 0x9C000D00~0x9C000D7F.

25.2 Function Diagram

The function diagram of CBDMA is shown in Figure 25-1.

Figure 25-1 CBDMA Functional Blocks

• REG_IO: Judging by the AXI command coming in from the slave end, when read / write is interleaved, there is a corresponding arbitration mechanism to determine which read / write command is first served.

• Exclusive access: The CB_DMA slave side supports AXI Exclusive access, but only supports it at most once.

• Write response: The write command is received by the slave side, and the feedback will be sent when the wdata is received.

• CB_DMA_REG: HE_RGST BUS slave, used to control the internal settings of register.

• CBUS interface: Receive the command sent by the BUS master and convert it to the interface of CBSRAM_CTRL to access CBSRAM.

• CBSRAM_CTRL: As Internal SRAM, the CBDMA slave / master may be accessed at the same time, so it needs to be arbiration. The priority of the slave is defined to be greater than the master.

• DMA_CTRL: As the master, parse the DMA settings issued by CB_DMA_REG and convert them to AXI command to send them out.

 

25.3 System Operation Mode

CMD_QUE_DEPTH, MEMSET_VALUE, DMA_MODE, DMA_LENGTH, DMA_SRC_ADR and DMA_DES_ADR cannot be changed during DMA_GO == 1. If it is violated, H/W can self-protect, and the software will not be written in until DMA_GO = 0, which can be determined by a bit. Owner. The Semaphore mechanism may be safer and better.
CMD_QUE_DEPTH, MEMSET_VALUE, DMA_MODE, DMA_LENGTH, DMA_SRC_ADR, DMA_DES_ADR and DMA_GO parameters are defined in registers map segments.

25.3.1 MEMSET Mode

• Set below registers:

  • dma_mode: Set dma_mode to MEMSET mode

  • memset: Value is the value you want to fill in main memory.

  • Length: The number of bytes to memset this time.

  • Dest Addr: The number of bytes to memset this time.

  • Src addr[1:0]: The offset of memset data.

• After DMA Go, the result will be the memset value filled to Dest Addr, totally filled "length" byte.

• Write data flow :

Please refer figure 25-2 Step8 ~ step9.

25.3.2 DMA Write Mode

• Set below registers:

  • dma_mode: Set dma_mode to DMA Write mode.

  • Length: The number of bytes to be transferred from CBSRAM Write to SDRAM this time.

  • Dest Addr: Write out data into DRAM address.

  • Src Addr: From which address of CBSRAM, read data and write to DRAM.

• After DMA Go, CB_DMA will move data from the CBSRAM of Src_Addr to the SDRAM starting with Dest_Addr, with a total of "length" bytes. DMA_DONE_FLAG will be set after Write ends. If the interrupt of DMA_DONE is not masked, there will be an interrupt of DMA_DONE.

• Write data flow :

Please refer figure 25-2 Step1 ~ step5.

Figure 25-2 Write Data Flow

25.3.3 DMA Read Mode

• Set below registers:

  • dma_mode: Set dma_mode to DMA Read mode.

  • Length: The number of bytes to be returned from DRAM read this time.

  • Dest Addr: Read back data into the address of CBSRAM.

  • Src Addr: Read data from which address of DRAM.

• After DMA Go, CB_DMA will move data from the SDRAM of Src_Addr to the CBSRAM starting with Dest_Addr, for a total of "length" bytes. After the Read ends, DMA_DONE_FLAG will be set to 1. If the interrupt of DMA_DONE is not masked, there will be an interrupt of DMA_DONE.

• Read data flow :

Please refer figure 25-3 Step1 ~ step5.

Figure 25-3 Read Data Flow

25.3.4 DMA Copy Mode

• Set below registers:

  • dma_mode: Set dma_mode to DMA Copy mode.

  • Length: The number of bytes to copy.

  • Dest Addr: Copy the data into the address of the DRAM.

  • Src Addr: Read the data from the address of the DRAM and write it to Dest DRAM.

• After DMA Go, CB_DMA will move data from the DRAM of Src_Addr to the DRAM starting with Dest_Addr, for a total of "length" bytes. After the copy ends, DMA_DONE_FLAG will be set to 1. If the interrupt of DMA_DONE is not masked, there will be an interrupt of DMA_DONE.

• The last 256 bytes inside CB_DMA will be treated as buffer and the contents will be destroyed.

• Copy data flow :

Please refer figure 25-4 Step1 ~ step9.

Figure 25-4 Copy Data Flow

 

25.3.5 SG(Scatter-gather) DMA Mode

The SG DMA mode is like auto repeat mode of MEMSET or DMA write or DMA read or DMA copy. Through this function, user can read several area data and write to a gather area. User also can read data in a continue area and write to several discontinue area. The max operation times is 32. The control registers are G26.10~15. Below shows the registers setting flow for continue DMA copy:

• Set below registers:

  • LLI_ACCESS_INDEX: Determine which LLI(Link List Item) mapping to following registers.

  • LAST_LLI_IN_TASK: If this flag setup, it indicate the last LLI.

  • dma_mode: Set dma_mode to DMA Copy mode.

  • Length: The number of bytes to copy.

  • Dest Addr: Copy the data into the address of the DRAM.

  • Src Addr: Read the data from the address of the DRAM and write it to Dest DRAM.

  • Repeat above action.

• After SG DMA Go, CB_DMA will move data from the DRAM of Src_Addr to the DRAM starting with Dest_Addr according index. After the copy ends, DMA_DONE_FLAG will be set to 1. If the interrupt of DMA_DONE is not masked, there will be an interrupt of DMA_DONE.

Figure 25-5 shows an example of SG DMA with DMA copy mode

Figure 25-5 SG DMA with DMA copy mode

25.4 CBDMA Interrupts

The CBDMA interrupt events are connected to the same interrupt vector, please refer to Group 26.5 register. These events generate an interrupt if the corresponding "Enable Control Bit" is set, please refer to Group 26.6 register.

25.5 Registers Map

25.5.1 Registers Memory Map

 

 

25.5.2 Registers Description

 

RGST Table Group 26 CB DMA: CBUS DMA Controller

26.0 DMA HW VER (dma hw ver)
Address: 0x9C000D00
Reset: 0x1751300

26.1 DMA CONFIG (dma config)
Address: 0x9C000D04
Reset: 0x80030000

26.2 DMA LENGTH (dma length)
Address: 0x9C000D08
Reset: 0x00000000

26.3 DMA SRC ADR (dma src adr)
Address: 0x9C000D0C
Reset: 0x00000000 

 

26.4 DMA DES ADR (dma des adr)
Address: 0x9C000D10
Reset: 0x00000000