6. Memory Map

6.1 General Description

The SP7021 ARM CPU uses a 32-bit memory map for all accesses. The memory map shows in Table 6-1. At reset, the memory is configured by the internal BootROM mirrored at address 0xFFFF0000 where the ARM will start execution.

Name	CPU view	memory range size	Description

Name	CPU view	memory range size	Description
DRAM	0x0000_0000 - 0x1FFF_FFFF	512MB	DRAM memory area
Reserved	0x2000_0000 - 0x6FFF_FFFF	1280MB
FPGA Device	0x7000_0000 - 0x77FF_FFFF	128MB	For FPGA application Exchange data with external device (FPGA) via FBIO slave port
Reserved	0x7800_0000 - 0x97FF_FFFF	512MB
SPI-NOR Flash (External ROM)	0x9800_0000 - 0x9BFF_FFFF	64MB	External boot ROM area
Device Register	0x9C00_0000 - 0x9DFE_FFFF	32MB	Device Register Space, refer to Section 6.2 Device Register Map for more detail
Reserved	0x9DFF_0000 - 0x9DFF_FFFF	64KB
Internal BootROM	0x9E00_0000 - 0x9E0F_FFFF	1MB	Internal boot ROM area
Reserved	0x9E10_0000 - 0x9E7F_FFFF	7MB
Internal SRAM (CB_DMA0)	0x9E80_0000 - 0x9E81_FFFF	128KB	Access exceeds the CBDMA range, the Write data will be discarded, Read will get the error data, and trigger interrupt
Internal SRAM (CB_DMA1)	0x9E82_0000 - 0x9E82_0FFF	4KB	Access exceeds the CBDMA range, the Write data will be discarded, Read will get the error data, and trigger interrupt
Reserved	0x9EA0_0000 - 0x9EAF_FFFF	1MB
Reserved	0x9EC0_0000 - 0x9EFF_FFFF	4MB
Hivec_ROM	0xFFFF_0000 - 0xFFFF_FFFF	64KB	In the Internal BootROM mode, CPU address will remap from 0xFFFF_xxxx to 0x9E00_xxxx (64KB range) after reset. In the External Boot from SPI_NOR mode, CPU address will transfer from 0xFFFF_xxxx to 0x9800_xxxx (64KB range)

Table 6-1 Memory Map

6.2 Device Register Map

The device register space, located in the memory map address range of 0x9C000000~0x9DFEFFFF, control most SP7021 functions. The device registers is separated into 2 segments, one is called RGST table (Register table) which base address is 0x9C000000, another one is called AMBA table (Advanced Microcontroller Bus Architecture table) which base address is 0x9C100000. Table 6-2 /6-3 show the group number with memory map start address of each module.

Memory Map Start Address	Data Width	Group No.	Module	Chapter link

Memory Map Start Address	Data Width	Group No.	Module	Chapter link
0x9C000000	32	0	MOON0	7. System Control
0x9C000080	32	1	MOON1	7. System Control
0x9C000100	32	2	MOON2	7. System Control
0x9C000180	32	3	MOON3	7. System Control
0x9C000200	32	4	MOON4	7. System Control
0x9C000280	32	5	MOON5	7. System Control
0x9C000300	32	6	GPIOXT	7. System Control
0x9C000380	32	7	GPIOXT	7. System Control
0x9C000400	16	8	IOP	26. IOP8051
0x9C000600	32	12	STC/Timer/Watchdog	10. General Purpose Timers
0x9C000780	32	15	INTERRUPT2	9. Interrupt Controller
0x9C000800	16	16	UA2	13. Universal Asynchronous Receiver Transmitter (UART)
0x9C000880	16	17	UA3	13. Universal Asynchronous Receiver Transmitter (UART)
0x9C000900	16	18	UA0	13. Universal Asynchronous Receiver Transmitter (UART)
0x9C000980	16	19	UA1	13. Universal Asynchronous Receiver Transmitter (UART)
0x9C000A80	32	21	INTERRUPT3	9. Interrupt Controller
0x9C000B00	32	22	SPINOR	17. SPI NOR
0x9C000B80	32	23	SPINOR Protection	17. SPI NOR
0x9C000D00	32	26	CBDMA0	25. CBDMA
0x9C001900	32	50	DPHY0	16. SDRAM
0x9C001980	32	51	DPHY0	16. SDRAM
0x9C001A00	32	52	DPHY0	16. SDRAM
0x9C001A80	32	53	DPHY0	16. SDRAM
0x9C001B80	32	55	DDC0	20. HDMI TX
0x9C002880	32	81	ICM	11. Input Capture Module (ICM)
0x9C002980	32	83	SECGRP1	23. SDPROT
0x9C002A00	32	84	SEC	24. SECURITY
0x9C002A80	32	85	SEC	24. SECURITY
0x9C002B80	32	87	SPINAND	18. SPI NAND
0x9C002C00	32	88	SPINAND Protection	18. SPI NAND
0x9C002D80	32	91	SPI_MASTER_0	30. Serial Peripheral Interface (SPI)
0x9C002E00	32	92	SPI_SLAVE_0	30. Serial Peripheral Interface (SPI)
0x9C003A00	32	116	RTC	8. Real Time Clock (RTC)
0x9C003B00	32	118	CARD0	22. CARD_CTL (eMMC, SD, SDIO)
0x9C003B80	32	119	CARD0	22. CARD_CTL (eMMC, SD, SDIO)
0x9C003C00	32	120	CARD0	22. CARD_CTL (eMMC, SD, SDIO)
0x9C003E80	32	125	CARD1	22. CARD_CTL (eMMC, SD, SDIO)
0x9C003F00	32	126	CARD1	22. CARD_CTL (eMMC, SD, SDIO)
0x9C003F80	32	127	CARD1	22. CARD_CTL (eMMC, SD, SDIO)
0x9C004000	32	128	CARD1	22. CARD_CTL (eMMC, SD, SDIO)
0x9C004080	32	129	CARD1	22. CARD_CTL (eMMC, SD, SDIO)
0x9C004600	32	140	I2CM0	31. Inter-Integrated Circuit (I2C)
0x9C004680	32	141	I2CM0_GDMA	31. Inter-Integrated Circuit (I2C)
0x9C004700	32	142	I2CM1	31. Inter-Integrated Circuit (I2C)
0x9C004780	32	143	I2CM1_GDMA	31. Inter-Integrated Circuit (I2C)
0x9C004800	32	144	I2CM2	31. Inter-Integrated Circuit (I2C)
0x9C004880	32	145	I2CM2_GDMA	31. Inter-Integrated Circuit (I2C)
0x9C004900	32	146	I2CM3	31. Inter-Integrated Circuit (I2C)
0x9C004980

6. Memory Map

6.1 General Description

6.2 Device Register Map

Comments