4.7 Design testing and simulation

After completing the design of the seven-segment digital tube display, the next work will be test simulation and verification; this work requires corresponding EDA tools to support the completion of functional simulation verification; This manual uses Synopsys' VCS + Verdi to realize the simulation and verification of the design; if the user does not have this tool, the ModelSim commonly used in universities can be used to achieve the simulation and verification of the design.

4.7.1 Introduction to test architecture

The verification of the IP module is a very important task. The IP module is a "black box" for other users. In order to ensure that other users can safely use this IP core, testing is essential. In order to check the correctness of the IP core and whether it meets the timing requirements, you must first write a test platform, add external incentives to the written program, and at the same time write the Behavior model, which is used to automatically compare with the output of the Design (Design Under Test). After completing the above verification, synthesize the design through the synthesis tool and check the synthesizability of the language, as well as the synthesis efficiency, cost, and area. Then use the simulation tool to further analyze the waveforms of the output and internal registers to complete the simulation. Then download the IP to the FPGA platform, use the Plus1 IDE environment on the PC to write the C language program, and debug the design online; through register configuration and digital tube display buffer content settings, it is finally displayed on the seven-segment digital tube. By observing the data sent by the CPU and the finally displayed data results, we can know whether the IP function is correct, change the register configuration and other parameters and then test to complete FPGA verification.

The structure of the overall test environment is as follows：

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The basic idea of ​​the test is: First, sim.v calls the WD task in FAKE_CPU.v to generate the APB BUS Writer operation behavior, and completes the initial configuration of the EX_CON, EX_TO, EX_BUFFER registers, such as digital tube display control enable, timer overflow interrupt control enable, timing time setting ; After the interrupt signal is generated, call the RO task in FAKE_CPU.v to generate APB BUS Read operation behavior, read the corresponding bit in the status register EX_STATE to determine whether the design works according to the design requirements

 4.7.2 Test environment introduction

The entire test environment of this IP design module refers to \src\ip\led\sim, where model is used to store the APB BUS's have model design, tsk is used to store all test documents, and work is used to store intermediate temporary files generated by simulation. The following figure shows the specific file architecture

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The relevant file codes are as follows

sim.v：The top module of the test environment instantiates the FAKE_CPU.v and LED.v design files The simulated excitation generates files, and at the same time judges whether the output result of these excitations after passing through the LED is correct. The relevant codes are as follows:

`define   WD       sim.I_FAKE_CPU.WD  //Call the function in FAKE_CPU.v

`define   RO       sim.I_FAKE_CPU.RO

`define   WAIT_INT sim.I_FAKE_CPU.WAIT_INT

`timescale 1ns/1ns

module  sim;

reg         SYSCLK;

reg         RST_B;

wire        PSEL;

wire       PWRITE;

wire       PENABLE;

wire [4 :0] PADDR;

wire [31:0] PWDATA;

wire [31:0] PRDATA;

wire       INT_B;

wire   [7:0]    SEG_HEX;   

wire   [7:0]    COM;

//////////////////To Genarate CLK and RST_B///////////////////////////

parameter  CYCLE=10;

always  #(CYCLE/2)  SYSCLK = ~SYSCLK;

initial

begin

SYSCLK=0;

RST_B=1;

#5 RST_B=0;

#5 RST_B=1;

end

////////////////////////////testcase////////////////////////////////////

 reg [31:0] rx_data;

initial

    begin

    #50;

    $display ("=============================================");

    $display ("                TEST  BEGIN                  ");

    $display ("=============================================");

    @(posedge SYSCLK) #1;

    `WD (5'h0,32'h0000_0007);//

    `WD (5'h1,32'h0000_0019);// Timing time is set to 1u

    `WD (5'h2,32'h0000_aa55);//

    repeat(100)

    @(posedge SYSCLK);

    `WAIT_INT;     //Wait for interrupt signal

    `RO (5'h3,rx_data); 

    `WD (5'h0,32'h0000_000f);// 

    `RO (5'h3,rx_data); 

    `WD (5'h0,32'h0000_0007);// 

    `WD (5'h2,32'h9999_9999);//

    repeat(100)

    @(posedge SYSCLK);

    $display ("=============================================");

    $display ("                TEST  FINISH                 ");

    $display ("============================================="); 

        $finish; 

    end

 ///////////////////////Instantiate the LED design module///////////////////////////////////////

LED  I_LED(

        .SYSCLK     (SYSCLK),

        .RST_B      (RST_B),

        .PSEL       (PSEL),

        .PWRITE      (PWRITE),

        .PENABLE      (PENABLE),

        .PADDR        (PADDR),

        .PWDATA       (PWDATA),

        .SEG_HEX        (SEG_HEX),

        .COM           (COM),

        .PRDATA       (PRDATA),

        .INT_B      (INT_B)

                    );

///////////////////////Instantiate the FAKE_CPU design module///////////////////////////////////

FAKE_CPU I_FAKE_CPU(

        .SYSCLK     (SYSCLK),

        .RST_B      (RST_B),

        .INT_B      (INT_B),

        .PWDATA     (PWDATA),

        .PSEL       (PSEL),

        .PWRITE     (PWRITE),

        .PADDR      (PADDR),

        .PRDATA     (PRDATA),

    .PENABLE    (PENABLE)           

                    );

endmodule

FAKE_CPU.v：Provide a series of tasks, functions and interfaces for generating APB master BUS signals. The APB bus protocol is shown below：

 The relevant code is as follows:

 module FAKE_CPU(

       SYSCLK,

       RST_B,

       INT_B,

       PWDATA,

       PADDR,

       PWRITE,

       PSEL,

       PRDATA,

       PENABLE

    );

output         PWRITE;

output         PSEL;

output [4 :0]  PADDR;

output [31:0]  PWDATA;

input          SYSCLK;

input          RST_B;

input          INT_B;

input  [31:0]  PRDATA;

output         PENABLE;

reg            PWRITE;

reg            PENABLE;

reg            PSEL;

reg    [4 :0]  PADDR;

reg    [31:0]  PWDATA;

wire           SYSCLK;

wire           RST_B;

wire           INT_B;

wire   [31:0]  PRDATA;

initial

    begin

    PWRITE=0;

    PENABLE=0;

    PSEL=0;

    PWDATA=0;

    PADDR=0;

End

/////////////////APB BUS Write operation ///////////////////////////////

task WD;

    input [4 :0]M_ADR;

    input [31:0]M_BUS;

    begin

    @(posedge SYSCLK) #1;

    PSEL=1;

    PWRITE=1;

    PENABLE=0;

    PADDR=M_ADR;

    PWDATA=M_BUS;

    @(posedge SYSCLK) #1;

    PENABLE=1;

    @(posedge SYSCLK) #1;

    PSEL=0;

    PWRITE=0;

    PENABLE=0;

    PADDR=0;

    PWDATA=0;

    end

endtask

/////////////// Interrupt detect operation ////////////////

task WAIT_INT;

    begin

    wait(!INT_B);

    end

endtask

///////////////// APB BUS Read operation ///////////////////////////

task RO;

    input [4 :0]M_ADR;

    output[31:0]DATA;

    begin

    @(posedge SYSCLK) #1;

    PSEL=1;

    PENABLE=0;

    PADDR=M_ADR;

    @(posedge SYSCLK) #1;

    PENABLE=1;   

    @(posedge SYSCLK) #1;

    PSEL=0;

    PENABLE=0;

    PADDR=0; 

    DATA=PRDATA;

    end

endtask

endmodule

After the user prepares the relevant EDA tool environment, enter the sim directory and execute the make command; the Makefile in the current directory automatically executes and calls the VCS tool to start the designed simulation, and finally generates the FSDB format waveform file (waveform) for subsequent Verdi tools Perform debugging analysis

Next, analyze and debug the simulation results. In the sim directory, execute the make verdi command. The Makefile in the current directory is automatically executed and the Verdi tool is called to start the analysis of the design results.

The corresponding test environment simulation corresponding waveforms are as follows:

4.7.3 Test function point introduction

In order to fully verify the correctness of the designed seven-segment display control, the test function points shown below are listed.

Table 4.7.3 Test function points

  4.7.3.1 Reset verification

In this design, the following two methods can be used to verify the reset function: one is to reset at the beginning of the simulation, and the other is to reset during the digital tube working process. The main verification idea is to compare whether all the internal registers are equal to the initial value after reset

4.7.3.2 Verification of LED display control

In this design, through the configuration of EX_CON register bit 0 to achieve the opening and closing of the digital tube display

4.7.3.3 Verification of timer overflow identification

In this design, through the configuration of bit 0 and bit 3 of the EX_TO, EX_CON registers, the generation and clearing of the overflow flag of the timer in the digital tube display design are realized

4.7.3.4 Verification of timer overflow flag interrupt

In this design, through the configuration of EX_TO, EX_CON register bit 0,1,2, 3, to achieve the generation of timer overflow interrupt and clear the overflow flag in the digital tube display design