Open source RISC-V CPU core design practice

Case download:

1 Design Brief

In 2010, the RISC-V architecture was born at the University of California, Berkeley. With its streamlined and efficient advantages, it quickly gained the support of academia. After nearly ten years of development, the RISC-V architecture has been widely recognized by academia and industry. With the increasing maturity of the RISC-V ecosystem, future RISC-V-based processors will be widely used.

PicoRV32 is an open source RISC-V processor core that implements the RISC-V RV32IMC instruction set. It can be configured as RV32E, RV32I, RV32IC, RV32IM, or RV32IMC core, and optionally includes a built-in interrupt controller, implemented in Verilog hardware description language, which can be obtained from the RISC-V website http://riscv.org/ code, tools (gcc, binutils, etc.). PicoRV32 uses RISC-V ISR, but Trap / interrupt / interrupt return is redesigned, using a simplified scheme to complete the interrupt operation and implement a simple built-in custom interrupt controller.

The focus of this PicoRV32 is to pursue the optimization of area and frequency. The cost of its published data on Xilinx7-Series FPGA is 750-2000 LUTs, and it can be integrated to the main frequency of 250-450MHz. This practice deeply integrates the theoretical knowledge of computer architecture with the engineering practice of SP7021 + FPGA SOC platform to realize CPU-related functions, and strives to enable students to quickly and deeply master the design capabilities of embedded CPU cores for future large-scale SoC design and high-performance core Design lays a solid foundation

2 Design specifications

1  Supportt AMBA4 AXI 32 bit Bus interface.

2  Support RISC-V RV32IMC Instruction Set

3 Support Extend Co-Processor Interface

3 SOC integration

3.1 Implementation of hardware platform for RISC-V CPU experiment project

PicoRV32 supports 32-bit AXI4-Lite master bus system, we choose axi_ bus_ s32_bridge module from Bus Bridge series, it provides AXI slave bus interface to connect our IP,as shown in the figure below:

Open

In this experiment, the related experiment is completed with the FPGA daughter board supporting the SP 7021 practice platform. The development tool of the FPGA daughter board uses XILINX's Vivado integrated development environment (version number 2018.3); in order to facilitate the connection of the user's own verification IP to the SOC system Verification, this experiment provides the corresponding design reference basic files, as follows

Open

The corresponding connection between the design case and the pin connection of the SP7021 motherboard and FPGA daughter board is shown in the following table: 1: U20B on the motherboard is connected to J2 of the FPGA daughter board (Pin pin corresponding, such as 1-51 ...), providing the data transmission channel between the Plus1 main chip on the motherboard and the FPGA

Open