14. Universal Serial Bus (USB)

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Last updated: Dec 16, 2019

14.1 Introduction

The USB is specified to be an industry-standard extension to the PC architecture. It provides an USB compliant connection between the host PC and the function implemented by the microcontroller. It also supports USB-OTG (On-The-Go) function to connect with peripheral USB devices. Data transfer between the host PC and the system memory occurs through a dedicated packet buffer memory accessed directly by the USB peripheral. The size of this dedicated buffer memory must be according to the number of endpoints used and maximum packet size. The dedicated memory is sized to 512bytes and up to 16 mono-directional endpoints can be used. This USB supports 4 kind endpoint transactions, they are Control, Bulk, Interrupt and Isochronous transfer mode.
A USB system is described by three definitional areas, USB PHY (UPHY) , USB Controller System (USBC) and On-The-Go (OTG) Controller. Where USB Controller system includes two major parts: USB host controller(UHC) and USB device controller(UDC). The USB transfer signals and power over a four-wire cable, the signaling occurs over wires on each point-to-point segment.
The USB HOST IP (UHC) is a USB2.0 Host Controller,  Support both Enhanced Host Controller Interface (EHCI) and Open Host Controller Interface (OHCI), 32bit AHB/AXI configure bus, 64bit AXI data bus. The USB DEVICE IP (UDC) is a standard USB Device Controller  which supports USB2.0 High Speed and Full speed, AXI Master bus, AXI Master1 bus (used for ISO auto DMA), AHB slave bus and UTMI (USB2.0 Transceiver Macrocell Interface) interface. The USB PHY module supports working in Host or Device mode and can dynamic switch.
The USB control registers located in the memory map address range of 9c102000h~9c103fffh. The USB PHY control registers located in the 9c004a80h~9c004b7fh. SP7021 totally supports two USB2.0 modules, the features list as below.

  • UTMI+ level3 compatible with OTG
  • 27MHz crystal input to support Battery Charger and sync signals
  • Integrated Phase-Locked Loop (PLL) oscillator generate 120M CLK to DPHY
  • Supports various power down modes include Operating, Partial and Suspend modes
  • Supports high-speed (HS, 480 Mbps), full-speed (FS, 12Mbps) and low-speed (LS, 1.5Mbps) data transfer rates
  • OTG supports Attach Detection Protocol (ADP), Session Request Protocol (SRP) and Host Negotiation Protocol (HNP)
  • Support boot from each USB port
  • Support USB video class (UVC)

14.2 Function Diagram

A generalized function diagram of USB is shown in Figure 14-1.

Figure 14-1 USB Functional Blocks

  • AHB_IF: Advanced High-performance Bus (AHB) Interface block, used as AHB bus master data and configure register
  • AXI_IF: Advanced Extensible Interface (AXI) block, used for high performance read, write and address access.
  • Enhanced Host Controller Block(EHCI): Standard Enhanced Host Controller Interface IP.
  • Open Host Controller Block(OHCI): Standard Open Host Controller Interface IP.
  • USB Device Controller Block(UDC): SUNPLUS USB Device Controller IP.
  • Hub Configure registers(RHREG): Root Hub Configure registers block
  • PORT Routing & Control Logic: Generate PHY Control signals (UTMI).
  • UPHY: Convert parallel data of UTMI into serial data, and output to the outside of the chip through differential data lines.


14.2.1 OHCI Block Diagram

The EHCI has the same structure as OHCI, so below description will focus on OHCI block. Figure 14-2 shows generic OHCI Block Diagram.


Figure 14-2 OHCI Block Diagram

  • ohci_reg: This is OHCI register control block. Use the AHB master to read/write the OHCI register which generate control signal to OHCI.
  • ohci_td: This is OHCI data structure process block. The TD is Transfer Descriptor of OHCI.
  • ohci_core: This is OHCI main block, used to R/W ED (Endpoint Descriptor) and TD, and control USB Transfers.
  • ohci_pie: This block is used to control USB port state, such as reset、suspend and resume, generate port control signals.


14.2.2 USB Device Controller (UDC) Block Diagram

Figure 14-3 shows a generic UDC Block Diagram.

Figure 14-3 UDC Block Diagram

  • AXI master1:
    • Receive the command from USB and issue AXI transition
    • It contains 1*audio DMA, 1*video DMA and 3*bulk DMA
    • It contains the DMA arbitration mechanism
  • AXI master2:
    • Including AXI transition control for ISO auto DMA mode
  • AHB slave:
    • receive the command from system and issue AHB transition
    • It contains the configure registers, CPU can write or read these registers by AHB bus
  • DMA: DMA logic, issue data transition
  • ISO DMA: ISO auto DMA block
    • Including ISO IN and ISO OUT DMA control for TRB and Data Read/Write
    • Including DMA arbitration mechanism
  • SYNC: Sync logic between SYS clock domain and PHY clock domain
  • Async FIFO: Sync data between the two clock domain
  • Buffer: data buffer
  • EPx: EPx (Endpoint x) control logic
  • Device IP Link-layer: USB link layer transition logic
  • EP5 DMA: ISO IN DMA for Endpoint5
  • EP7 DMA: ISO IN DMA for Endpoint7
  • EPC DMA: ISO OUT DMA for EndpointC
  • DMA ARB: DMA Arbiter for ISO Endpoints


14.2.3 OTG Transceiver Block Diagram

Figure 14-4 shows a generic OTG Transceiver Block Diagram.

Figure 14-4 OTG Transceiver Block Diagram

  • REG: Receive the command from system and issue AHB transition. It contains the configure registers and CPU can read or write these registers by AHB bus.
  • OTG ctrl: Provide flags to deal with OTG functions (SRP/HNP/ADP). It also provides select signal to MUX module.
  • MUX: Select UTMI data to host controller or device controller.

14.2.4 UPHY Block Diagram

Figure 14-5 shows a generic UPHY Block Diagram

Figure 14-5 UPHY Block Diagram

  • FS_TX_ALL/HS_TX_ALL : Receive signals from the UTMI interface in full-speed, low-speed and high-speed mode, through bit stuffer and encode, then pass the buffer to the APHY
  • FS_RX_ALL : Receive data from the APHY in full-speed or low-speed mode. After Decode and bit unstuffing, the data is converted to UTMI and output to Host or Device.
  • HS_RX_ALL : In high-speed mode, 20bit data is accepted from the APHY, and the data is separated from the clock according to the CDR, and 5 bit data is sampled. After Decode and bit unstuffing, the data is output from the UTMI interface to Host or Device.
  • PATTERNGEN: Generate test-related patterns through I2C or BIST mode
  • CTRL_TOP :
    • The TX/RX enable signal of HS/FS/LS is generated based on the UTMI signal.
    • Output line state signal on UTMI interface
    • Control pull-up and pull-down resistors on the DP/DM line
    • In HS mode, generate HOST_DISC signal, HOST_DISC=0, device connection, HOST_DISC=1, device disconnected
  • SERIAL_CTRL: Write or read register values to UPHY internally via I2C or RGST BUS mode
  • CLOCK_MANAGER: Generate L120_CLK and UTMI_CLK. When suspend, generate PLL_OFF to turn off the PLL.
  • RXCHECKER_PHY: Check if the data during transmission is correct


14.3 USB Host Controller

When insert a USB device, the USB host controller will trigger EHCI/OHCI interrupt to tell software that there is a USB device inserted.

14.3.1 OHCI Controller

Figure 14-6 shows four main areas of a Universal Serial Bus system. These areas are the Client Software/USB Driver, Host Controller Driver (HCD), Host Controller (HC) and USB Device. OHCI specifies the interface between the Host Controller Driver and the Host Controller and the fundamental operation of each.

Figure 14-6 OHCI controller
There are two communication channels between the Host Controller and the Host Controller Driver (Please refer to figure 14-7). The first channel uses a set of operational registers located on the HC. The Host Controller is the target for all communication on this channel. The operational registers contain control, status, and list pointer registers. Within the operational register set is a pointer to a location in shared memory named the Host Controller Communications Area (HCCA). The HCCA is the second communication channel. The Host Controller is the master for all communication on this channel. The HCCA contains the head pointers to the interrupt Endpoint Descriptor lists, the head pointer to the done queue, and status information associated with start-of-frame processing.

Figure 14-7 OHCI communication channel

14.3.2 EHCI Controller

A USB Host System is composed of a number of hardware and software layers. The Figure 14-8 illustrates a conceptual block diagram of the building block layers in a host system that work in concert to support USB2.0.

Figure 14-8 EHCI controller
This architecture allows the USB 2.0 host controller to provide USB functionality as long as there is at least USB 1.1 software support in the resident operating system. Full USB 2.0 functionality is delivered when both USB 1.1 and EHCI software is available in the operating system. The port transceiver routing logic is key to delivering this flexible operating environment. The state of the routing logic initially depends on whether software has configured the EHCI controller. Once the EHCD driver has configured the EHCI controller, it can specifically release the transceiver to the companion host controller port register if the attached device is not a high-speed device. When the operating system does not include support for the EHCI controller, the ports are default-routed to the companion host controllers and existing USB support for Full- and Low-speed devices remains.

Figure 14-9 Companion Host Controller
The Companion Host Controller (CHC) may be any USB 1.1 host controller (e.g. OHCI or UHCI). The Companion Host Controllers always manage Full- and Low-speed USB devices connected to the root ports. The CHCs have no knowledge of the high-speed-mode host controller. They can possibly be integrated into a USB 2.0 host controller with no modification.
The EHCI interface defines three interface spaces:

  1. PCI Configuration Space: If the implementation includes PCI registers, they are used for system component enumeration and PCI power management.
  2. Register Space: Implementation-specific parameters and capabilities, plus operational control and status registers. This space, normally referred to as I/O space, must be implemented as memory-mapped I/O space.
  3. Schedule Interface Space: This is typically memory allocated and managed by the EHC Driver for the periodic and asynchronous schedules.


Figure 14-10 EHCI interface

14.3.3 OTG Controller

OTG driver used to control OTG controller work normally. OTG driver mainly maintain a OTG state machine and reflect platform USB state. When OTG is in the different OTG state, OTG driver will control OTG controller to do different things. For example, when OTG state become A-device, OTG driver configure registers to raise VBUS signal and control OTG controller to switch platform to USB host mode. When OTG state become B-device, OTG driver will configure registers to drop VBUS signal and control OTG controller to switch platform to USB device mode to wait host enumerate itself. And so on.

14.4 Data Transfer Types

There are four data transfer types defined in USB. Each type is optimized to match the service requirements between the client software and the USB device. The four types are:

  • Control Transfers: Nonperiodic data transfers used to communicate configuration/command/status type information between client software and the USB device. It must be through Endpoint 0, and there can only be one device, and it must be supported. The maximum data size that can be transmitted at one time is 64 bytes and is bidirectional. Basically, when a USB device is plugged into the computer, the computer will ask for some information through Endpoint 0. According to the USB 2.0 specification, Host must reserve 10% of the bandwidth for Control transmission.
  • Bulk Transfers: Nonperiodic data transfers used to communicate large amounts of information between client software and the USB device. The maximum size of data that can be transmitted at one time is 512 bytes (HS). It does not guarantee the bandwidth, it is usually HOST that the BUS has a bandwidth to choose to transmit Bulk data. In contrast, if the bandwidth is very idle, the amount of data that can be transmitted per second is large.
  • Interrupt Transfers: Small data transfers used to communicate information from the USB device to the client software. The Host Controller Driver polls the USB device by issuing tokens to the device at a periodic interval sufficient for the requirements of the device. The maximum data size that can be transmitted at one time is 1024 bytes (HS), and it is transmitted periodically. The device side needs to declare how long this period is. In HS, it is in micro-second. It requires HOST to guarantee the bandwidth. If HOST cannot meet the bandwidth requirements of this device, HOST can refuse to start the device.
  • Isochronous Transfers: Periodic data transfers with a constant data rate. Data transfers are correlated in time between the sender and receiver. It is very similar to Interrupt transmission, but it has no mechanism for error retransmission. All above three mode have a mechanism of error retransmission, and this mechanism is based on the premise that each transmission will have an ACK packet. Isochronous transmission does not require ACK packets, so it naturally can't detect errors.

In OHCI the data transfer types are classified into two categories: periodic and nonperiodic. Periodic transfers are interrupt and isochronous since they are scheduled to run at periodic intervals. Nonperiodic transfers are control and bulk since they are not scheduled to run at any
specific time, but rather on a time-available basis.

14.5 Data Structure

14.5.1 OHCI Data Structure

The basic building blocks for communication across the interface are the Endpoint Descriptor(ED) and Transfer Descriptor (TD). Each data transfer type has its own linked list of Endpoint Descriptors to be processed. Figure 14-10, Typical List Structure, is a representation of the data structure relationships.

Figure 14-11 OHCI data structure
Endpoint Descriptors
The Host Controller Driver assigns an Endpoint Descriptor to each endpoint in the system. The Endpoint Descriptor contains the information necessary for the Host Controller to communicate with the endpoint. The fields include the maximum packet size, the endpoint address, the speed of the endpoint, and the direction of data flow. Endpoint Descriptors are linked in a list.
An Endpoint Descriptor (ED) is a 16-byte, memory resident structure that must be aligned to a 16-byte boundary. The Host Controller traverses lists of EDs and if there are TDs linked to an ED, the Host Controller performs the indicated transfer.
Figure 14-11 shows Endpoint Descriptor Format.

Figure 14-12 Endpoint Descriptor Format
Notes:
1. Fields containing '—' are not interpreted or modified by the Host Controller and are available for use by the Host Controller Driver for any purpose.
2. Fields containing '0' must be written to 0 by the Host Controller Driver before queued for Host Controller processing. If Host Controller has write access to the field, it will always write the field to 0.
Transfer Descriptors
A queue of Transfer Descriptors is linked to the Endpoint Descriptor for the specific endpoint. The Transfer Descriptor contains the information necessary to describe the data packets to be transferred. The fields include data toggle information, shared memory buffer location and completion status codes. Each Transfer Descriptor contains information that describes one or more data packets. The data buffer for each Transfer Descriptor ranges in size from 0 to 8192 bytes with a maximum of one physical page crossing. Transfer Descriptors are linked in a queue, the first one queued is the first one processed.
A Transfer Descriptor (TD) is a system memory data structure that is used by the Host Controller to define a buffer of data that will be moved to or from an endpoint. TDs come in two types: general and isochronous. The General TD is used for Interrupt, Control, and Bulk Endpoints and an Isochronous TD is used to deal with the unique requirements of isochronous transfers. Two TD types are supported because the nature of isochronous transfers does not lend itself to the standard DMA buffer format and the packetizing of the buffer required for isochronous transfers is too restrictive for general transfer types.
General Transfer Descriptor
Transfers for control, bulk, and interrupt all use the same format for their Transfer Descriptor (TD). This General TD is a 16-byte, host memory structure that must be aligned to a 16-byte boundary.
Figure 14-12 shows General Transfer Descriptor Format.

Figure 14-13 General Transfer Descriptor Format
Isochronous Transfer Descriptor
An Isochronous TD is used exclusively for isochronous endpoints. All TDs linked to an ED with F = 1 must use this format. This 32-byte structure must be aligned to a 32-byte boundary in system memory.
Figure 14-13 shows General Transfer Descriptor Format.

Figure 14-14 Isochronous Transfer Descriptor Format

14.5.2 EHCI Data Structure

The data structure definitions in this chapter support a 32-bit memory buffer address space. The interface consists of a Periodic Schedule, Periodic Frame List, Asynchronous Schedule, Isochronous Transaction Descriptors, Split-transaction Isochronous Transfer Descriptors, Queue Heads and Queue Element Transfer Descriptors.
Periodic Frame List
This schedule is for all periodic transfers (isochronous and interrupt). The periodic schedule is referenced from the operational registers space using the PeriodicListBase address register and the FRINDEX register. The periodic schedule is based on an array of pointers called the Periodic Frame List. The PeriodicListBase address register is combined with the FRINDEX register to produce a memory pointer into the frame list. The Periodic Frame List implements a sliding window of work over time.

Figure 14-15 Periodic Frame List
Asynchronous List Queue Head Pointer
The Asynchronous Transfer List (based at the AsyncListAddr register), is where all the control and bulk transfers are managed. Host controllers use this list only when it reaches the end of the periodic list, the periodic list is disabled, or the periodic list is empty.

Figure 14-16 Asynchronous Transfer List

14.6 UTM Interface Timing Diagram


Figure 14-17 TX odd byte data

Figure 14-18 TX even byte data

Figure 14-19 RX odd byte data

Figure 14-20 RX even byte data

14.7 OHCI USB States

The Host Controller has four USB states visible to the Host Controller Driver via the Operational Registers: USBOPERATIONAL, USBRESET, USBSUSPEND, and USBRESUME. These states define the Host Controller responsibilities relating to USB signaling and bus states.

Figure 14-21 USB states

14.7.1 USBOPERATIONAL

When in the USBOPERATIONAL state, the Host Controller may process lists and will generate SOF Tokens. The USBOPERATIONAL state may be entered from the USBRESUME or USBRESET states. It may be exited to the USBRESET or USBSUSPEND states. When transitioning from USBRESET or USBRESUME to USBOPERATIONAL, the Host Controller is responsible for terminating the USB reset or resume signaling as defined in the USB Specification prior to sending a token.

14.7.2 USBRESET

When in the USBRESET state, the Host Controller forces reset signaling on the bus. The Host Controller's list processing and SOF Token generation are disabled while in USBRESET. The USBRESET state can be entered from any state at any time. The Host Controller defaults to the USBRESET state following a hardware reset. The Host Controller Driver is responsible for satisfying USB Reset signaling timing defined by the USB Specification.

14.7.3 USBSUSPEND

The USBSUSPEND state defines the USB Suspend state. The Host Controller's list processing and SOF Token generation are disabled. However, the Host Controller's remote wakeup logic must monitor USB wakeup activity. USBSUSPEND is entered following a software reset or from the USBOPERATIONAL state on command from the Host Controller Driver. While in USBSUSPEND, the Host Controller may force
a transition to the USBRESUME state due to a remote wakeup condition. This transition may conflict with the Host Controller Driver initiating a transition to the USBRESET state. If this situation occurs, the HCD-initiated transition to USBRESET has priority. The Host Controller Driver must wait 5 ms after transitioning to USBSUSPEND before transitioning to the USBRESUME state. Likewise, the Root Hub must wait 5 ms after the Host Controller enters USBSUSPEND before generating a local wakeup event and forcing a transition to USBRESUME. Following a software reset, the Host Controller Driver may cause a transition to USBOPERATIONAL if the transition occurs no more than 1 ms from the transition into USBSUSPEND. If the 1-ms period is violated, it is possible that devices on the bus will go into Suspend.

14.7.4 USBRESUME

When in the USBRESUME state, the Host Controller forces resume signaling on the bus. While in USBRESUME, the Root Hub is responsible for propagating the USB Resume signal to downstream ports as specified in the USB Specification. The Host Controller's list processing and SOF Token generation are disabled while in USBRESUME. USBRESUME is only entered from USBSUSPEND. The transition to USBRESUME can be initiated by the Host Controller Driver or by a USB remote wakeup signaled by the Root Hub. The Host
Controller is responsible for resolving state transition conflicts between the hardware wakeup and Host Controller Driver initiated state transitions. Legal state transitions from USBRESUME are to USBRESET and to USBOPERATIONAL. The Host Controller Driver is responsible for USB Resume signal timing as defined by the USB Specification.

14.8 USB OPERATION

14.8.1 OHCI Initialization

Initialize the open host controller, software should perform the following steps:

  • Set software reset in Group1.1 UHO_HcControl register bit[7:6]=0.
  • Configure OHCI command in Group1.1 UHO_HcControl register.
  • Select routed all ports to OHCI by set 0 to bit0 of Group2.24 UHE_CONFIGFLAG register.

Note: Due to some devices on the USB that may take a long time to reset, it is desirable that the Host Controller Driver startup process not transition to the USBRESET state if possible.

14.8.2 EHCI Initialization

In order to initialize the enhanced host controller, software should perform the following steps:

  • Set software reset in Group2.8 UHE_USBCMD register bit[1]=1.
  • Program the Group2.12 UHE_CTRLDESSEGMENT register with 4-Gigabyte segment where all of the interface data structures are allocated.
  • Write the appropriate value to the Group2.10 UHE_USBINTR register to enable the appropriate interrupts.
  • Write the base address of the Periodic Frame List to the Group2.13 UHE_PERIODICLISTBASE register. Write the base address of the Asynchronous Frame List to the Group2.14 UHE_ASYNCLISTBASE register.
  • Enable Periodic schedule in Gruop2.8 UHE_USBCMD register bit4, enable Asynchronous schedule in Gruop2.8 UHE_USBCMD register bit5.
  • Write the Group2.8 UHE_USBCMD register to set the desired interrupt threshold, frame list size (if applicable).
  • Write 1 to bit0 of Group2.24 UHE_CONFIGFLAG register to route all ports to the EHCI controller.
  • Wait device connect by check Group2.25 UHE_PORTSC register bit0=1.
  • Issue port reset by set Group2.25 UHE_PORTSC register bit8=1.
  • Turn the host controller ON via setting the Run/Stop bit in Gruop2.8 UHE_USBCMD register bit0.


14.8.3 OTG Initialization

  • Select work mode in Group8.0 MODE_SELECT register bit[1:0]. Default as 0 with OTG2.0.
  • Confirm work role by read Group8.0 MODE_SELECT register bit[1:0] after "ID_CHANGE_IF" interrupt is assert. The ID_CHANGE_IF flag is in Group8.3 OTG_ST register bit1.
  • Depend on work mode, set initial of OTG CTRL in Group8.1 OTG_DEVICE_CTRL register. Set SRP/ADP_SUPPORT in Group8.0 MODE_SELECT bit2 and bit3
  • Set SRP/HNP/ADP related timers in Group8.4~8.29 registers.


14.9 Pattern of come to USB2.0

Define the line state J, K, SE0 of USB, that is, D+, D-, as shown in the following table.


J

K

SE0

D+

1

0

0

D-

0

1

0


USB 2.0 is made under the existing architecture that does not destroy USB1.1. Unless host and device are both 2.0, they are all transmitted with 1.1. The method of recognition is chirp, which is described as follows. The yellow line is D+ and the blue line is D-. The timing is as follows:

Figure 14-22 USB2.0 chirp pattern

  • D+ pull up to 3.3V after device plug in
  • Host drive bus reset (se0, both D+,D- = 0)
  • Device chirp K 1ms-7ms. (D- = 800mV)
  • Host chirp KJKJKJ sequence pattern
  • Device recognizes 6 groups of kj and enters USB2.0 mode, turn on 45 Ohm pull down to GND at the same time, it make 800mV level become 400mV.



14.10 USB Interrupts

14.10.1 OHCI Interrupts

OHCI interrupt is from OHCI block with level signals. The detail interrupt information refer to the USBC0 Group1.3 bit[6:0] UHO_HcInterruptStatus Register. The enable register is USBC0 Group1.4 bit[6:0] UHO_HcInterruptEnable. Figure 14-23 shows the OHCI interrupt tree.

Figure 14-23 OHCI interrupt tree

  • RHSC: Root Hub content change status bit
  • FNO: Frame number overflow status bit
  • UE: Un-recoverable error
  • RD: Resume signaling detected status bit
  • SF: Each start of a frame status bit
  • WDH: HC has written HcDoneHead to HccaDoneHead status bit
  • SO: USB schedule for the current Frame overruns status bit


14.10.2 EHCI Interrupts

EHCI interrupt is from EHCI block with level signals. The detail interrupt information refer to the USBC0 Group2.9 bit[5:0] UHE_USBSTS register. The enable register is USBC0 Group2.10 bit[5:0] UHE_USBINTR. Figure 14-24 shows the EHCI interrupt tree.

Figure 14-24 EHCI interrupt tree

  • IAA: Indicates the assertion of Async Advance interrupt
  • HSE: Host system error
  • FLR: Indicate the Frame List Index rolls over from its maximum value to zero
  • PCD: Indicate any port of the port owner bit is set to zero or from zero to a one
  • USBERRINT: Indicate completion of a USB transaction results in an error condition
  • USBINT: Indicate the completion of a USB transaction


14.10.3 OTG Interrupts

The detail OTG interrupt information refer to the USBC0 Group8.3 bit[9:0] OTG_ST register. The enable register is USBC0 Group8.2 bit[9:0] OTG_INT_EN. Figure 14-25 shows the OTG interrupt tree.

Figure 14-25 OTG interrupt tree

  • ADP_CHANGE_IF: Indicate the ADP changed
  • A_SRP_DET_IF: Indicate A-device(Host side) have detected SRP
  • B_AIDL_BDIS_IF: Indicate B-device(Device side) disconnects to A-device(Host side) to start HNP
  • A_BIDL_ADIS_IF: Indicate A-device(Host side) disconnects to B-device(Device side) to start HNP
  • A_AIDL_BDIS_TMOUT_IF: Waiting for a disconnect timeout when HNP
  • B_SRP_FAIL_IF: B-device SRP fail
  • BDEV_CONNECT_TMOUT_IF: A-device waits B-device connect timeout
  • VBUS_RISE_TMOUT_IF: A-device waits vbus valid timeout
  • ID_CHANGE_IF: ID pin has changed
  • OVERCURRENT_IF: An attached B-device draws more current



14.11 Registers Map

14.11.1 Registers Memory Map

Memory Map Start Address

Data Width

Group No.

Module

0x9C004A80

32

149

UPHY0 (USB PHY 0)

0x9C004B00

32

150

UPHY1 (USB PHY1)

Table 14-1 USB PHY registers group list of RGST table

Both USB PHY registers have the same offset in corresponding register group. Only USB PHY0 (UPHY0) registers are described in following register description, for USB PHY1 please refer to UPHY0 description for more detail.

Memory Map Start Address

Data Width

Group No.

Module

0x9C102000

32

USBC0 Group 0

USB0 HOST

0x9C102080

32

USBC0 Group 1

USB0 OHCI

0x9C102100

32

USBC0 Group 2

USB0 EHCI

0x9C102400

32

USBC0 Group 8

USB0 OTG

0x9C102800

32

USBC0 Group 16

USB0 DMA

0x9C102880

32

USBC0 Group 17

USB0 INTERRUPT

0x9C102900

32

USBC0 Group 18

USB0 EP0~4

0x9C102980

32

USBC0 Group 19

USB0 EP5/6/7

0x9C102A00

32

USBC0 Group 20

USB0 EP8/9/A/B

0x9C102A80

32

USBC0 Group 21

USB0 EPC/D

0x9C102B00

32

USBC0 Group 22

USB0 Phyclk Domain Interrupt

0x9C102B80

32

USBC0 Group 23

USB0 Bulk Out FIFO

0x9C103000

32

USBC1 Group 0

USB1 HOST

0x9C103080

32

USBC1 Group 1

USB1 OHCI

0x9C103100

32

USBC1 Group 2

USB1 EHCI

0x9C103400

32

USBC1 Group 8

USB1 OTG

0x9C103800

32

USBC1 Group 16

USB1 DMA

0x9C103880

32

USBC1 Group 17

USB1 INTERRUPT

0x9C103900

32

USBC1 Group 18

USB1 EP0~4

0x9C103980

32

USBC1 Group 19

USB1 EP5/6/7

0x9C103A00

32

USBC1 Group 20

USB1 EP8/9/A/B

0x9C103A80

32

USBC1 Group 21

USB1 EPC/D

0x9C103B00

32

USBC1 Group 22

USB1 Phyclk Domain Interrupt

0x9C103B80

32

USBC1 Group 23

USB1 Bulk Out FIFO

Table 14-2 USB control registers group list of AMBA table

Only USB0 relative register group will be described in register description, for USB1, please refer to USB0 corresponding group description for more detail


14.11.2 Registers Description

RGST Table Group 149 UPHY0

149.0 CONFIG0 (cfg0)
Address: 0x9C004A80
Reset: 0x0000 0080


Field NameBitAccessDescription
Reserved31:8RORESERVED
J WAKE SEL7:5RWJ WAKE SEL controls wake up time.
0x0 : 0.54ms ˜ 1.09ms
0x1 : 1.09ms ˜ 1.68ms
0x2 : 1.68ms ˜ 2.18ms
0x3 : 2.18ms ˜ 2.73ms
0x4 : 2.73ms ˜ 3.27ms(default)
0x5 : 3.27ms ˜ 3.82ms
0x6 : 4.36ms ˜ 4.91ms
0x7 : 4.91ms ˜ 5.46ms
J ANG LB4RWAnalog Loopback mode.
0x0 : turn off analog loopback(default).
0x1 : turn on analog loopback.
J DIG LB3RWDigital Loopback mode.
0x0 : turn off digital loopback(default).
0x1 : turn on digital loopback.

J IPX2

2

RW

Charge Pump Current Option.
macro spec.

J ENABLE CNTR

1

RW

Bist mode counter enable of succcess and fail.
0 : Disable(default).
1 : Enable.

J CLEAR CNTR

0

RW

Bist mode counter clear of succcess and fail.
0 : Unclear(default).
1 : Clear.



149.1 CONFIG1 (cfg1)
Address: 0x9C004A84
Reset: 0x0000 0021


Field NameBitAccessDescription
Reserved31:8RORESERVED
J HS TX DELAY7:6RWFine tune TX Delay
0x0 : No delay(default).
0x1 : Delay 1 clock.
0x2 : Delay 2 clock.
0x3 : No delay.
J HS TX PWRSAV5RW

High Speed TX power saving. When this item actives, it means TX driver will turn on with TXValid.

When this item is low, it means TX driver will always turn on.
0x0 : Turn off power saving.
0x1 : Turn on power saving(default)

J HS RX DROP24RW

Set the EOP receive condition sensitive

If DEV_DET fall very quickly, this may cause some valid EOP bit lose and cause correct packet become RXERROR,

so this register set medium EOP detection.

0x0: do nothing(default)
0x1: set the EOP receive condition to be sensitive

J HS RX DROP43RW

Set the EOP receive condition very sensitive

If DEV_DET fall very quickly, this may cause some valid EOP bit lose and cause correct packet become RXERROR,

so this register set very sensitive EOP detection.

0: do nothing(default)
1: set the EOP receive condition to be very sensitive. In this case the setting will replace J HS RX DROP2

J HS RX LPFIL2:1RW

CDR data channel phase shift precision

0x0: shift precision is very high

0x1: shift precision is high

0x2: shift precision is medium

0x3: shift precision is slow

J FS TX PREDR IDLE0RWFor 1st cross over point perfection
0: Disable(default)
1 : Enable


149.2 CONFIG2 (cfg2)
Address: 0x9C004A88
Reset: 0x0000 0000 


Field NameBitAccessDescription
Reserved31:8RORESERVED
J DPN7:4RW

DP Full speed falling time select.

The larger the value, the shorter the DP falling transition time.

Default: 4'b0000

J DPP3:0RW

DP Full speed rising time select.

The larger the value, the shorter the DP rising transition time.

Default: 4'b0000



149.3 CONFIG3 (cfg3)

Address: 0x9C004A8C

Reset: 0x0000 0021


Field Name

Bit

Access

Description

Reserved

31:8

RO

RESERVED

J FORCE PU2 HI

7

RW

J FORCE PU2 HI
1: enable resistor ecn function, see ECN Res
0: do nothing(default)

J FORCE PU2 LO

6

RW

J FORCE PU2 LO
1: disable resistor ecn function, see ECN Res
0: do nothing(default)

J FORCE DISC ON

5

RW

Whenever DPDM PULLDOWN, the system force into chirp mode
0 : Turn off
1 : Turn on(default)

DEBUG_INT4:0RW

Reserved for internal debug purpose. Access to this register may cause unexpected malfunction




149.4 CONFIG4 (cfg4)
Address: 0x9C004A90
Reset: 0x0000 0020


Field NameBitAccessDescription
Reserved31:8RORESERVED
J IPX37RWCharge Pump Current Option.
macro spec.
J IPX16RWCharge Pump Current Option.
macro spec.

J SKIP NOXTION

5

RW

J SKIP NOXTION
1: when DP/DM doesn't toggle, clock and data recovery circuit will not work(default).
0: when DP/DM doesn't toggle, clock and data recovery circuit will work.

J PGMODE

4:0

RW

Pattern Selection of bist test
0x00 : NOTHING
0x01 : High Speed EYE Pattern in High Speed
0x02 : High Speed EYE Pattern in Full Speed
0x03 : Full Speed EYE Pattern in High Speed
0x04 : Full Speed EYE Pattern in Full Speed
0x05 : High Speed data Pattern
0x06 : Full Speed data Pattern
0x07 : High Speed idle SE0
0x08 : Full Speed idle J (NODRIVE)
0x09 : High Speed J
0x0a : High Speed K
0x0b : Full Speed J (DRIVE)
0x0c : Full Speed K
0x0d : High Speed SOF with many trans
0x0e : High Speed SOF with less trans same polarity
0x0f : High Speed SOF with less trans diff polarity
0x11 : error high speed eye pattern in high speed
0x12 : error high speed eye pattern in full speed
0x13 : Full Speed SOF with many trans
0x14 : Full Speed SOF with less trans same polarity
0x15 : Full Speed SOF with less trans diff polarity
0x16 : Disconnect test for fast FT without 45ohm
0x17 : 120Mbps 400mv swint for PLL verify
0x18 : 12Mbps full swing pattern for PLL verify
0x19 : High Speed EYE Pattern in Low Speed
0x1a : Full Speed EYE Pattern in Low Speed
0x1c : Low Speed idle J (NODRIVE)
0x1d : Low Speed J (DRIVE)
0x1e : Low Speed K
0x1f : error high speed eye pattern in low speed



149.5 CONFIG5 (cfg5)
Address: 0x9C004A94
Reset: 0x0000 0000



Field Name

Bit

Access

Description

Reserved

31:8

RO

RESERVED

SUCC CNTR

7:4

RU

Bit mode success counter

When successive 15 packages success, BIST test success and done.

FAIL CNTR

3:0

RU

Bit mode fail counter

When successive 15 packages fail, BIST test fail and done.


149.6 CONFIG6 (cfg6)
Address: 0x9C004A98 

Reset: 0x0000 0000


Field NameBitAccessDescription
Reserved31:8RORESERVED
J DMN7:4RW

DM Full speed falling time select.

The larger the value, the shorter the DP falling transition time.

Default: 4'b0000

J DMP3:0RW

DM Full speed rising time select.

The larger the value, the shorter the DP rising transition time.

Default: 4'b0000



149.7 CONFIG7 (cfg7)
Address: 0x9C004A9C

Reset: 0x0000 008A


Field NameBitAccessDescription
Reserved31:8RORESERVED
J EN INR7RWInternal Rext function enable
0x0 : disable
0x1 : enable(default)
J R TRIM6:5RWLoop filter R trim table
{R TRIM1,R TRIM0}
0x0 : 80K
0x1 : 18K
0x2 : 16K
0x3 : 14K
J DISC

4:0

RW

control disconnect voltage(16.5mV/step)

0x00 : value 405mv.

0x0a : value 570mv(default).

0x1e : 900mv.

0x1f : Disable Disconnection



149.8 CONFIG8 (cfg8)

Address: 0x9C004AA0
Reset: 0x0000 0000


Field Name

Bit

Access

Description

Reserved

31:8

RO

RESERVED

J FS TX J DELAY

7:6

RW

Full speed DP delay cycle
0x0 : No delay(default).
0x1 : Delay 1 clock.
0x2 : Delay 2 clock.
0x3 : Delay 2 clock.

J FS TX K DELAY

5:4

RW

Full speed DM delay cycle
0x0 : No delay(default).
0x1 : Delay 1 clock.
0x2 : Delay 2 clock.
0x3 : Delay 2 clock.

J LS TX J DELAY

3:2

RW

Low speed DP delay cycle
0x0 : No delay(default).
0x1 : Delay 1 clock.
0x2 : Delay 2 clock.
0x3 : Delay 2 clock.

J LS TX K DELAY

1:0

RW

Low speed DM delay cycle
0x0 : No delay(default).
0x1 : Delay 1 clock.
0x2 : Delay 2 clock.
0x3 : Delay 2 clock.



149.9 CONFIG9 (cfg9)
Address: 0x9C004AA4
Reset: 0x0000 0006


Field NameBitAccessDescription
Reserved31:5RORESERVED
J FL FORCE FS4RW

Enable Config device error state

0 : enable error state(default)
1 : disable error state

J FL DP PILLUP3RW

Config device DP or MP resister pullup

0 : Full-low speed DP pull up(default)
1 : Full-low speed DM pull up

J FL SAMPLE SEL2RW

Enable Full-low speed rx linestat sample circuit

0 : disable Full-low speed rx linestat sample circuit
1 : enable Full-low speed rx linestat sample circuit(default)

J DIS FSM WAIT4MS EN1RWDisable HOSTDISC error state
0 : enable error state
1 : disable error state(default)
J FS ONLY0RWDisable UPHY AFE Low speed circuit at Low speed
0 : Low speed circuit use in Low speed(default)
1 : Full speed circuit usb in Low speed



149.10 CONFIG10 (cfg10)
Address: 0x9C004AA8
Reset: 0x0000 0000 


Field NameBitAccessDescription
Reserved31:8RORESERVED
NA7ROHigh speed disconnect signal with filter.
0 : disconnect is not happened(default)
1 : disconnect is happened

J HSDISC LPFILTER

6:4

RW

High speed disconnect filter number
0x0 : 0 time(default).
0x1 : 1 time.
0x2 : 2 time.
0x3 : 3 time.
0x4 : 4 time.
0x5 : 5 time.
0x6 : 6 time.
0x7 : 7 time.

J ALDISC OFF

3

RW

Host disconnect force 0
0 : disable force Host disconnect signal(default).
1 : enable force Host disconnect signal 0.

J ALDISC ON

2

RW

Host disconnect force 1
0 : disable Host disconnect signal(default)
1 : enable force Host disconnect signal 1

J HSDISC OFF

1

RW

High speed disconnect force 0
0 : disable high speed disconnect signal(default).
1 : enable force Host disconnect signal 0.

J HSDISC ON

0

RW

High speed disconnect force 1
0 : disable high speed disconnect signal(default).
1 : enable force Host disconnect signal 1.



149.11 CONFIG11 (cfg11)
Address: 0x9C004AAC

Reset: 0x0000 0000 


Field NameBitAccessDescription
Reserved31:8RORESERVED
LINESTATE7:6ROLinestate signal without control
0x0 : SE0 state(default).
0x1 : J state.
0x2 : K state.
0x3 : SE1 state.
Reserved5:3RORESERVED
J LINE EN2RWForce Linestate signal
0 : disable force linestate(default).
1 : force linestate.
J LINE DATA

1:0

RW

Force Linestate signal value

0x0 : SE0 state(default).

0x1 : J state.

0x2 : K state.

0x3 : SE1 state.



149.12 CONFIG12 (cfg12)
Address: 0x9C004AB0
Reset: 0x0000 0007


Field NameBitAccessDescription
Reserved31:0ROReserved for Industrial Debug Purpose



149.13 CONFIG13 (cfg13)

Address: 0x9C004AB4

Reset: 0x0000 0000


Field Name

Bit

Access

Description

DEBUG_INT

31:0

RU

Reserved for Industrial Debug Purpose



149.14 CONFIG14 (cfg14)
Address: 0x9C004AB8
Reset: 0x0000 0011


Field NameBitAccessDescription
Reserved31:5RORESERVED

PHY R CONFIG

4

RW

UPHY resume config mode
0 : disable resume send se0.
1 : enable resume send se0(default).

FS/LS RX DCP

3:2

RW

FS/LS RX data capture point
0x0 : original midpoint(default).
0x1 : original midpoint+10%.
0x2 : original midpoint-10%.
0x3 : NA

FS/LS RX SCP

1:0

RW

FS/LS RX SYNC capture point
0x0 : detect sync use 2 data bit.
0x1 : detect sync use 4 data bit(default).
0x2 : detect sync use 6 data bit.
0x3 : NA



149.15 CONFIG15 (cfg15)
Address: 0x9C004ABC

Reset: 0x0000 0000 


Field NameBitAccessDescription
Reserved31:2RORESERVED
HS DIS DG FLT1:0RWHigh speed disconnect de-glitch filter
0x0 : no de-glitch(default).
0x1 : 1 time de-glitch.
0x2 : 2 time de-glitch.
0x3 : NA



149.16 CONFIG16 (cfg16)
Address: 0x9C004AC0
Reset: 0x0000 0000  


Field NameBitAccessDescription
Reserved31:8RORESERVED

J FORCE VDM SRC

7

RW

FORCE DM voltage.
0 : disable force voltage at DM(default)
1 : force voltage at DM

J TBCWAIT[1:0]

6:5

RW

Battery charger disconnect to rework time.
REWORK TIME
0x0 : 1.1ms(default)
0x1 : 3.2ms
0x2 : 5.4ms
0x3 : 8.2ms

J TVDM SRC DIS[1:0]

4:3

RW

J Battery charger polling DP high to send dm voltage time.
Counter DP Polling Time
0x0 : 1.6ms(default)
0x1 : 3.8ms
0x2 : 6.5ms
0x3 : 8.2ms

J TVDM SRC EN[1:0]

2:1

RW

Battery charger polling DP low to disable dm voltage time.
Counter DP Polling Time
0x0 : 1.6ms(default)
0x1 : 3.8ms
0x2 : 6.5ms
0x3 : 8.2ms

J BC ENABLE

0

RW

Battery Charger CDP Function Enable.
0 : disable battery charger CDP(default)
1 : enable battery charger CDP



149.17 CONFIG17 (cfg17)
Address: 0x9C004AC4
Reset: 0x0000 0092


Field NameBitAccessDescription
Reserved31:8RORESERVED

IBG TRIM0[2:0]

7:5

RW

Current of current source in CDP mode.
{IBG TRIM1[1:0],IBG TRIM0[2:0]}

0x0f : TTNVNT (default) I=100uA

0x12 : FFHVLT

0x0a : FFHVHT

0x17 : SSHVLT

0x0c : SSLVHT

0x17 : SSLVLT

J VDATREF TRIM[3:0]

4:1

RW

Reference voltage of comparator in CDP mode.

VDATREF TRIM[3:0]

0x1 : 250mv

0x2 : 300mv

0x4 : 350mv

0x8 : 400mv

0x9 : default

J EN DCP

0

RW

Battery Charger DCP Function Enable.

0 : disable DCP(default)

1 : enable DCP



149.18 CONFIG18 (cfg18)
Address: 0x9C004AC8
Reset: 0x0000 0010


Field NameBitAccessDescription
Reserved31:8RORESERVED
BC DETECT STATUS7RWIndicate Battery Charge handshake status
0:BC handshake done(default),
1:BC handshake is in progress.
VDMSRC TRIM[4:0]6:2RWDm source voltage.
0x01 : 500mv
0x02 : 550mv
0x04 : 600mv(default)
0x08 : 650mv
0x10 : 700mv
IBG TRIM1[1:0]

1:0

RW

Current of current source in CDP mode.
{IBG TRIM1[1:0],IBG TRIM0[2:0]}

0x0f : TTNVNT (default) I=100uA

0x12 : FFHVLT

0x0a : FFHVHT

0x17 : SSHVLT

0x0c : SSLVHT

0x17 : SSLVLT


149.19 CONFIG19 (cfg19)

Address: 0x9C004ACC

Reset: 0x0000 0000


Field Name

Bit

Access

Description

Reserved

31:1

RO

RESERVED

EN HSRXACTIVE INT

0

RW

Enable UPHY Interrupt.
0 : disable UPHY Interrupt(default)
1 : Enable UPHY Interrupt

 

149.20 CONFIG20 (cfg20)
Address: 0x9C004AD0
Reset: 0x0000 0009


Field NameBitAccessDescription
Reserved31:8RORESERVED

Reserved

7

RW

RESERVED

Reserved

6

RW

RESERVED

NA

5:0

RW

NA

J AC2 0 B

5:3

RW

OTG Discharge Current Option.

0x0: 5uA

0x1: 10uA

0x2: 15uA

0x3: 20uA

0x4: 30uA (default)

0x5: 40uA

0x6: 50uA

0x7: 60uA

J AC2 0

2:0

RW

OTG Charge Current Option.

0x0: 5uA

0x1: 10uA

0x2: 15uA

0x3: 20uA

0x4: 30uA (default)

0x5: 40uA

0x6: 50uA

0x7: 60uA



149.21 CONFIG21 (cfg21)

Address: 0x9C004AD4
Reset: 0x0000 0001


Field Name

Bit

Access

Description

Reserved

31:8

RO

RESERVED

BC DETECT STS

7

RO

Battery Charge is in detect progress.

BC PRTBL STS

6

RO

Battery Charge successful detect PRTBL STS.

BC VDMSRC STS

5

RO

Battery Charge successful send VDM SRC.

BC DISC CNT

4:3

RO

Battery Charge detect disconnect counter.

BC SUCC CNT

2:1

RO

Battery Charge handshake successful counter.

J BC SUSPEND EN

0

RW

Enable Battery Charge handshake while PHY in SUSPEND MODE.
0 : Disable
1 : Enable(default)



149.22 CONFIG22 (cfg22)
Address: 0x9C004AD8
Reset:  0x0000 0077



Field Name

Bit

Access

Description

Reserved

31:8

RO

RESERVED

DCP2P7V

7:4

RW

Battery Charge DCP 2.7V control to APHY

DCP 1.2V mode dm source voltage trimming:

triming step=25mV

0x0: 1.025V

0x3: 1.1V

0x7: 1.2V

0xb: 1.3V

0xe: 1.4V

DCP1P2V

3:0

RW

Battery Charge DCP 1.2V control to APHY

DCP 2.7V mode dm source voltage trimming:

triming step=25mV

0x0: 2.525V

0x3: 2.6V

0x7: 2.7V

0xb: 2.8V

0xe: 2.9V



149.23 CONFIG23 (cfg23)
Address: 0x9C004ADC

Reset: 0x0000 0018


Field NameBitAccessDescription

Reserved

31:8

RO

RESERVED

RFU

7:6

RW

Reserved for future use

PROB

5:3

RW

APHY Probe control

0x0: 597.5mV

0x1: 617.5mV

0x2: 636.5mV

0x3: 656.5mV (default)

0x4: 675.5mV

0x5: 695.5mV

0x6: 714.5mV

0x7: 734.5mV

R TEST TIEH

2

RW

R TEST Tie High control to APHY

0: disable (default)

1: USB_R_TEST=AVDDC33

EN DCP2P7V

1

RW

Enable 2.7V DCP mode

0: disable 2.7V DCP mode (default)

1: enable 2.7V DCP mode 

EN DCP1P2V

0

RW

Enable 1.2V DCP mode

0: disable 1.2V DCP mode (default)

1: enable 1.2V DCP mode 


149.24 CONFIG24 (cfg24)
Address: 0x9C004AE0
Reset: 0x0000 0001


Field NameBitAccessDescription
Reserved31:8RORESERVED
BC AUTO RST7RWBattery Charge auto re-start enable
1'b0: Disable auto re-start.
1'b1: Enable auto re-start(Default)
TBC AUTO RST6:0RW

Battery Charge auto re-start timer

When counter equal to J_TBC_AUTO_RST, internal FSM timeout.

Real time is 606ms*J_TBC_AUTO_RST



149.25 CONFIG25 (cfg25)
Address: 0x9C004AE4
Reset: 0x0000 0004


Field NameBitAccessDescription
Reserved31:8RORESERVED
RFU7:3RWReserved for future use
SQ CT2:0RW

RX Squelch level control to APHY

0x0: 67.8mV

0x1: 84.5mV

0x2: 101.2mV

0x3: 118.1mV

0x4: 135.0mV (default)

0x5: 152.1mV

0x6: 169.2mV

0x7: 186.6mV



USB Controller System 0 (USBC0)
Group 0 USB Host Control  (UHC)

0.0 USB Host Version (UHVERSION)
Address: 0x9C102000
Reset: 0xC2120101


Field NameBitAccessDescription
UHVERSION31:0ROUSB Host Hardware Version
Read as '0xC2120101'



0.4 USB Power Control and Status (UHPOWERCS PORT)
Address: 0x9C102010
Reset: 0x00070000


Field NameBitAccessDescription

reserved 

31:19

RO

RESERVED
Read as '0'

UPHY SUSPENDM

18

RO

UPHY Suspend Signal
Current suspend signal input signal for controller.
1: Normal function. (default)
0: suspend state.

UPHY PARTIALM

17

RO

UPHY Partial Signal
Current partial signal input signal for controller.
1: Free run clock when suspend. (default)
0: Stop clock when suspend

USB CLK EN

16

RO

USB Clock Enable
This bit is set when received two USB clock domain clock, and will only be cleared when hardware reset

reserved

15:12

RO

RESERVED
Read as '0'

UPHY PAR EN

11

RW

UPHY Partial Enable
This bit is only valid when bit9 of this register is set.
1: Force Partial
0: force not partial (default)

UPHY SUSP EN

10

RW

UPHY Suspend Enable
This bit is only valid when bit8 of this register is set.
1: Force suspend
0: force not suspend (default)

UPHY PAR CTRL

9

RW

UPHY Partial Control
1: Force partial control enable
0: partial controlled by host controller (default)
When this bit is set controller output partial signal to PHY
is controlled by bit11 of this register

UPHY SUSP CTRL

8

RW

UPHY Suspend Control
1: Force suspend control enable
0: Suspend controlled by host controller (default)
When this bit is set controller output suspend signal to
PHY is controller by bit10 of this register

reserved

7:2

RO

RESERVED
Read as '0'

USBCLK SEL

1

RW

USB Clock Domain Clock Select
0: PHY 30MHz Clock(default)
1: Slow Clock
The controller will toggle this bit based on the current functional state. Driver needn't change this bit in normal case.

reserved

0

RO

RESERVED
Read as '0'



Group 1 USB Host OHCI Controller

1.0 OHCI HcRevision Register (UHO HcRevision)
Address: 0x9C102080
Reset: 0x00000010


Field Name

Bit

Access

Description

Reserved

31:8

RO

Reserved
Read as '0'

REV

7:0

RO

OHCI Revision
Read as '10', version 1.0



1.1 OHCI HcControl Register (UHO HcControl)
Address: 0x9C102084
Reset: 0x00000000


Field NameBitAccessDescription
Reserved31:11ROReserved
RWE10RORemoteWakeupEnable
This bit is used by HCD to enable or disable the remote wakeup signaling upon the detection of upstream resume. read as '0'
RWC9RORemoteWakeupConnected
This bit indicates whether HC supports remote wakeup signaling, read as '0'
IR8RWInterruptRouting
Not support.
HCFS7:6RWHostControllerFunctionalState for USB
0x0 : USBRESET (default)
0x1 : USBRESUME
0x2 : USBOPERATIONAL
0x3 : USBSUSPEND
BLE5RWBulkListEnable
Enable or disable the processing of the Bulk list in the next
frame. Default disabled

CLE

4

RW

ControlListEnable
Enable or disable the processing of the Control list in the next frame. Default disabled

IE

3

RW

IsochronousEnable
Enable or disable the processing the Isochronous EDs of the periodic list in the next frame. Default disabled

PLE

2

RW

PeriodicListEnable
Enable or disable the processing of the periodic list in the next frame. Default disabled

CBSR

1:0

RW

ControlBulkServiceRatio
Specifies the service ratio between Control and Bulk EDs
0x0: 1:1 (default)
0x1: 2:1
0x2: 3:1
0x3: 4:1



1.2 OHCI HcCommandStatus Register (UHO HcCommandStatus)
Address: 0x9C102088
Reset: 0x00000000


Field NameBitAccessDescription
Reserved31:18ROReserved
SOC17:16RO

SchedulingOverrunCount
Incremented on each scheduling overrun error and initial- ized to 00b and wraps around at 11b.

Used by HCD to monitor any persistent scheduling problems.

Reserved15:4ROReserved
OCR3ROOwnershipChangeRequest
Not support
BLF2RWBulkListFilled
Indicate whether there are any TDs on the Bulk list.
1: There is TDs on the Bulk list.
0: There is no TDs on the Bulk list (default)
CLF1RWControlListFilled
Indicate whether there are any TDs on the Control list.
1: There is TDs on the Control list.
0: There is no TDs on the Control list (default
HCR0otherHostControllerReset
Write 1, host Controller software reset, then clear this field by itself.



1.3 OHCI HcInterruptStatus Register (UHO HcInterruptStatus)
Address: 0x9C10208C

Reset: 0x00000000

Field Name

Bit

Access

Description

Reserved

31

RO

Reserved
Read as '0'

OC

30

RO

OwnershipChange
Not support

Reserved

29:7

RO

Reserved
Read as '0'

RHSC

6

RWC

RootHubStatusChange
Content of HcRhStatus or the content of any of HcRhPort- Status[NumberofDownstreamPort] change status bit

FNO

5

RWC

FrameNumberOverflow
Frame number overflow status bit

UE

4

RWC

UnrecoverableError
Un-recoverable error, host will set this bit when ITD offset is wrong

RD

3

RWC

ResumeDetected
Resume signaling detected status bit.

SF

2

RWC

StartofFrame
Each start of a frame status bit

WDH

1

RWC

WritebackDoneHead
HC has written HcDoneHead to HccaDoneHead status bit.

SO

0

RWC

SchedulingOverrun
USB schedule for the current Frame overruns status bit.



1.4 OHCI HcInterruptEnable Register (UHO HcInterruptEnable)
Address: 0x9C102090
Reset: 0x00000000


Field Name

Bit

Access

Description

MIE

31

Other

MasterInterruptEnable
Write 0: Ignore
Write 1: Enable interrupt generation due to events speci- fied in the other bits of this register.

OC

30

RO

OwnershipChange
Not support

Reserved

29:7

RO

Reserved
Read as '0'

RHSC

6

Other

RootHubStatusChange
Write 0: Ignore
Write 1: Enable interrupt generation due to Root Hub Sta- tus Change.

FNO

5

Other

FrameNumberOverflow
Write 0: Ignore
Write 1: Enable interrupt generation due to Frame Num- ber Overflow.

UE

4

Other

UnrecoverableError
Write 0: Ignore
Write 1: Enable interrupt generation due to unrecoverable error.

RD

3

Other

ResumeDetected
Write 0: Ignore
Write 1: Enable interrupt generation due to Resume De- tect.

SF

2

Other

StartofFrame
Write 0: Ignore
Write 1: Enable interrupt generation due to Start of Frame.

WDH

1

Other

WritebackDoneHead
Write 0: Ignore
Write 1: Enable interrupt generation due to HcDoneHead
Writeback.

SO

0

Other

SchedulingOverrun
Write 0: Ignore
Write 1: Enable interrupt generation due to Scheduling
Overrun.



1.5 OHCI HcInterruptDisable Register (UHO HcInterruptDisable)
Address: 0x9C102094
Reset: 0x00000000


Field Name

Bit

Access

Description

MIE

31

Other

MasterInterruptEnable
Write 0: Ignore
Write 1: Disable interrupt generation due to events speci- fied in the other bits of this register.

OC

30

RO

OwnershipChange
Not support

Reserved

29:7

RO

Reserved
Read as '0'

RHSC

6

Other

RootHubStatusChange
Write 0: Ignore
Write 1: Disable interrupt generation due to Root Hub Sta- tus Change.

FNO

5

Other

FrameNumberOverflow
Write 0: Ignore
Write 1: Disable interrupt generation due to Frame Num- ber Overflow.

UE

4

Other

UnrecoverableError
Write 0: Ignore
Write 1: Disable interrupt generation due to unrecoverable error.

RD

3

Other

ResumeDetected
Write 0: Ignore
Write 1: Disable interrupt generation due to Resume De- tect.

SF

2

Other

StartofFrame
Write 0: Ignore
Write 1: Disable interrupt generation due to Start of Frame.

WDH

1

Other

WritebackDoneHead
Write 0: Ignore
Write 1: Disable interrupt generation due to HcDoneHead
Writeback.

SO

0

Other

SchedulingOverrun
Write 0: Ignore
Write 1: Disable interrupt generation due to Scheduling
Overrun.





1.6 OHCI HcHCCA Register (UHO HcHCCA)
Address: 0x9C102098
Reset: 0x00000000


Field Name

Bit

Access

Description

HCCA

31:8

RW

Host Controller Communication Area
Base address of the Host Controller Communication Area.

Reserved

7:0

RO

Reserved
Read as '0'



1.7 OHCI HcPeriodCurrentED Register (UHO HcPeriodCurrentED)
Address: 0x9C10209C

Reset: 0x00000000


Field Name

Bit

Access

Description

PCED

31:4

RO

PeriodCurrentED
The physical address of the current Isochronous or Inter- rupt Endpoint Descriptor in the periodic list.

Reserved

3:0

RO

Reserved
Read as '0'



1.8 OHCI HcControlHeadED Register (UHO HcControlHeadED)
Address: 0x9C1020A0
Reset: 0x00000000
 

Field Name

Bit

Access

Description

CHED

31:4

RW

ControlHeadED
The physical address of the first Endpoint Descriptor of the Control list.

Reserved

3:0

RO

Reserved
Read as '0'

 
1.9 OHCI HcControlCurrentED Register (UHO HcControlCurrentED)
Address: 0x9C1020A4
Reset: 0x00000000

Field Name

Bit

Access

Description

CCED

31:4

RW

ControlCurrentED
The physical address of current Endpoint descriptor of the control list. Initially, this is set to zero to indicate the end of the Control list.

Reserved

3:0

RO

Reserved
Read as '0'



1.10 OHCI HcBulkHeadED Register (UHO HcBulkHeadED)
Address: 0x9C1020A8
Reset: 0x00000000

Field Name

Bit

Access

Description

BHED

31:4

RW

BulkHeadED
The physical address of the first Endpoint Descriptor of the Bulk list.

Reserved

3:0

RO

Reserved
Read as '0'



1.11 OHCI HcBulkCurrentED Register (UHO HcBulkCurrentED)
Address: 0x9C1020AC

Reset: 0x00000000

Field Name

Bit

Access

Description

BCED

31:4

RW

BulkCurrentED
The physical address of current Endpoint descriptor of the bulk list. This is initially set to zero to indicate the end of the Bulk list.

Reserved

3:0

RO

Reserved
Read as '0'


1.12 OHCI HcDoneHead Register (UHO HcDoneHead)
Address: 0x9C1020B0
Reset: 0x00000000

Field Name

Bit

Access

Description

DH

31:4

RO

DoneHead
The physical address of the last completed Transfer. This is set to zero whenever HC writes the content of this register to HCCA.

Reserved

3:0

RO

Reserved
Read as '0'



1.13 OHCI HcFmInterval Register (UHO HcFmInterval)
Address: 0x9C1020B4
Reset: 0x27782EDF


Field NameBitAccessDescription
FIT31RWFrameIntervalToggle
HCD toggles this bit whenever it loads a new value to
FrameInterval.
FSMPS30:16RW

FSLargestDataPacket
Specify the largest amount of data in bits which can be sent or received by the HC in a single transaction at any given time without causing scheduling overrun.

Default value is (FI-210)*6/7

Reserved15:14ROReserved
FI13:0RWFrame Interval
Specify the interval between two consecutive SOFs in
12MHz. The nominal value is set to be 11,999.



1.14 OHCI HcFmRemaining Register (UHO HcFmRemaining)
Address: 0x9C1020B8
Reset: 0x00000000


Field NameBitAccessDescription
FRT31ROFrame Remaining Toggle
This bit is loaded from the FrameIntervalToggle field of
HcFmInterval whenever FrameRemaining reaches 0.
Reserved30:15ROReserved
FR14:0RO

Frame Remaining
This counter is decremented at each 30MHz clock.

When it reaches zero, it is reset by loading the FrameInterval value specified in HcFmInterval at the next bit time boundary.



1.15 OHCI HcFmNumber Register (UHO HcFmNumber)
Address: 0x9C1020BC

Reset: 0x00000000


Field NameBitAccessDescription
Reserved

31:16

RO

Reserved
Read as '0'

FN

15:0

RO

FrameNumber
This is incremented when HcFmRemaining is re-loaded. It will be rolled over to 0h after ffffh.



1.16 OHCI HcPeriodicStart Register (UHO HcPeriodicStart)
Address: 0x9C1020C0
Reset: 0x00000000


Field NameBitAccessDescription
Reserved

31:15

RO

Reserved
Read as '0'

PS

14:0

RW

PeriodicStart
The value is calculated roughly as 1/10 off from HcFmInterval. A typical value will be 6978h.

When HcFmRemaining reaches the value specified,processing of the periodic lists will have priority over Control/Bulk pro- cessing.



1.17 OHCI HcLSThreshold Register (UHO HcLSThreshold)
Address: 0x9C1020C4
Reset: 0x00000628


Field Name

Bit

Access

Description

Reserved

31:8

RO

Reserved
Read as '0'

LST

7:0

RW

LSThreshold
The low speed transaction is started only if FrameRemain- ing >= this field.



1.18 OHCI HcRhDescriptorA Register (UHO HcRhDescriptorA)
Address: 0x9C1020C8
Reset: 0x01000101


Field NameBitAccessDescription
POTPGT31:24ROPowerOnToPowerGoodTime
Not support
Reserved23:13ROReserved
NOCP12RONoOverCurrentProtection
Read as '1', Not overcurrent protection support
OCPM11ROOverCurrentProtectionMode
Read as '0', Not support
DT10RODeviceType
Read as '0', specified that the Root Hub is not a compound device.
NPS9RONoPowerSwitching
Read as '1', ports are always powered on
PSM8ROPowerSwitchingMode
Read as '0', all ports are powered at the same time
NDP7:0RONumberDownstreamPorts
The number of downstream ports supported by the Root
Hub is 8'b1


1.19 OHCI HcRhDescriptorB Register (UHO HcRhDescriptorB)
Address: 0x9C1020CC

Reset: 0x00000000


Field NameBitAccessDescription
PPCM31:16ROPortPowerControlMask
Not support, read as 0x00
DR15:0RWDeviceRemovable
Not support, read as 0x00



1.20 OHCI HcRhStatus Register (UHO HcRhStatus)
Address: 0x9C1020D0
Reset: 0x00000000


Field NameBitAccessDescription
CRWE31Other(write) ClearRemoteWakeupEnable
Writing a '1' clears DeviceRemoveWakeupEnable. Writing a '0' has no effect.
Reserved30:18ROReserved
CCIC17ROOverCurrentIndicatorChange
Not support
LPSC16RO(read) LocalPowerStatusChange
Read as '0', the Root Hub does not support the local power status feature
(write) SetGlobalPower
Not support.
DRWE15RW(read) DeviceRemoteWakeupEnable
This bit enables a ConnectStatusChange bit as a resume event, causing a USBSUSPEND to USBRESUME state tran- sition and setting the ResumeDetected interrupt.
0 = ConnectStatusChange is not a remote wakeup event. (default)
1 = ConnectStatusChange is a remote wakeup event. (write) SetRemoteWakeupEnable Writing a '1' sets De-
viceRemoveWakeupEnable. Writing a '0' has no effect.
Reserved14:2ROReserved
OCI1ROOverCurrentIndicator
Read as '0', Not support
LPS0RO(read) LocalPowerStatus
Read as '0', the Root Hub does not support the local power status feature
(write) ClearGlobalPower
Not support



1.21 OHCI HcRhPortStatus Register (UHO HcRhPortStatus)
Address: 0x9C1020D4
Reset: 0x00000100


Field NameBitAccessDescription
Reserved31:21ROReserved
PRSC20W1CPortResetStatusChange
0 = port reset is not complete
1 = port reset is complete
OCIC19ROPortOverCurrentIndicatorChange
Read as '0', no change in PortOverCurrentIndicator
PSSC18W1CPortSuspendStatusChange
0 = resume is not completed
1 = resume completed
PESC17W1CPortEnableStatusChange
0 = no change in PortEnableStatus
1 = change in PortEnableStatus
CSC16W1CConnectStatusChange
0 = no change in CurrentConnectStatus
1 = change in CurrentConnectStatus
Reserved15:10ROReserved
LSDA9Other(read) LowSpeedDeviceAttached
Indicates the speed of the device attached to this port. This field is valid only when the CurrentConnectStatus is set.
0 = full speed device attached
1 = low speed device attached
(write) ClearPortPower
HCD clears the PortPowerStatus bit by writing a '1' to this bit.Writing a '0' has no effect.
PPS8RO(read) PortPowerStatus
Read as '1', port power is on. (write) SetPortPower
HCD writes a '1' to set the PortPowerStatus bit. Writing a
'0' has no effect.
Reserved7:5ROReserved
PRS4Other(read) PortResetStatus
0 = port reset signal is not active
1 = port reset signal is active
(write) SetPortReset
HCD sets the port reset signaling by writing a '1' to this bit.Writing a '0' has no effect.
POCI3Other(read) PortOverCurrentIndicator Read as '0', no overcurrent condition (write) ClearSuspendStatus
HCD writes a '1' to initiate a resume. Writing a '0' has no effect. A resume is initiated only if PortSuspendStatus is set.
PSS2Other(read) PortSuspendStatus
Indicate the port is suspended or in the resume sequence.
0 = port is not suspended
1 = port is suspended
(write) SetPortSuspend The HCD sets the PortSuspendSta- tus bit by writing a '1' to this bit. Writing a '0' has no effect.
PES1Other(read) PortEnableStatus
Indicate whether the port is enabled or disabled. HCD sets this bit by writing SetPortEnable and clears it by writing ClearPortEnable.
0 = port is disabled
1 = port is enabled
(write) SetPortEnable
The HCD sets PortEnableStatus by writing a '1'.Writing a
'0' has no effect.
CCS0Other(read) CurrentConnectStatus
0 = no device connected
1 = device connected
(write) ClearPortEnable
0 = Ignore
1 = clear the PortEnableStatus bit
Note: This bit is always read '1b' when the attached device is nonremovable (DeviceRemoveable[NDP]).



1.25 HcRhPortStatus Additional Register (UH PortStatusA)
Address: 0x9C1020E4
Reset: 0x00180B40


Field NameBitAccessDescription
reserved31:23RORESERVED
CLK DIV2 522:16RWClock Divider for 2.5us from Slow Clock
These bits are used to divide the slow clock to 2.5us pulse for remote wakeup use. default '24' for 10MHz clock
reserved15:12RORESERVED

SAMPLE EN

11

RW

UTMI RX Negedge Sample Enable
1'b1: Host will used a negedge DFF to sample the RX sig- nals before use (default).
1'b0: Host will use the interface signal directly.
This is used to avoid the hold time violation of UTMI Rx signals.

RXERR BLOCK EN

10

RW

PHY RXERR Signal Block Enable
1: Block RX Error signals in some condition. 0: Not Block
RX Error signals in some condition (default)

OUT TRIG

9:8

RW

OUT Transfer Trigger Level
Used to set when host will start transfer OUT packet.
0x0: host will start transfer OUT packet when read 1/4 of the data from memory.
0x1: host will start transfer OUT packet when read 1/2 of the data from memory.
0x2: host will start transfer OUT packet when read 3/4 of the data from memory.
0x3: host will start transfer OUT packet when all data has been read from memory (default).

PHY SIM MODE

7

RW

PHY Simulation Mode
1: Simulation Mode
0: Spec Mode (default)
This is used for simulation speed up.

LS TO CTRL

6:4

RW

Low Speed Timeout Control
The time out value of low speed device is counted from
TO = (75*LS TO CTRL + 65)*UTMI CYCLE, default '4' for
365 UTMI clock cycle(18 Low speed bit time) timeout

PORT PAR EN

3

RW

PHYCLK is able to stop in SUSPEND State
The partial signal to PHY will only be active when this bit si set and awake en bit in POWER CS register is 0. Default
'0'

reserved

2:1

RO

Reserved
Read as '0

SUSPEND HCFS

0

RW

Suspend when HC in suspend state
Assert the suspend signal to UPHY when HcControlReg- ister[7:6] is in suspend state(2'b11). Default '0'




Group 2 USB Host EHCI Controller

2.0 EHCI Interface Version Number (UHE HCIVERSION)
Address: 0x9C102100
Reset: 0x01100020


Field NameBitAccessDescription
HCIVERSION31:16ROInterface Version Number
The most significant byte of this register represents a major revision and the least significant byte is the minor revision. Read as '0110'
Reserved15:8ROReserved
CAPLENGTH7:0ROCapability Register Length
offset to add to register base to find the beginning of the
Operational Register Space. Read as '20'



2.1 EHCI Structural Parameters (UHE HCSPARAMS)
Address: 0x9C102104
Reset: 0x00001101


Field NameBitAccessDescription
Reserved31:24ROReserved
DPN23:20RODebug Port Number
Reserved19:17ROReserved
P INDICATOR16ROPort Indicators
Not support, read as '0'
N CC15:12RONumber of Companion Controller
Read as '1', indicates the number of companion controllers associated with this USB 2.0 host controller.
N PCC11:8RONumber of Ports per Companion Controller
Read as '1', indicates the number of ports supported per companion host controller.

PRR

7

RO

Port Routing Rules
Read as '0', The first N PCC ports are routed to the low- est numbered function companion host controller,

the next N PCC port are routed to the next lowest function com- panion controller, and so on.

Reserved

6:5

RO

Reserved
Read as '0'

PPC

4

RO

Port Power Control
Not support, read as '0'

N PORTS

3:0

RO

Number of PORTS
The number of physical downstream ports implemented on this host controller is 1



2.2 EHCI Capability Parameters (UHE HCCPARAMS)
Address: 0x9C102108
Reset: 0x000A0006


Field NameBitAccessDescription
Reserved31:20ROReserved
32FPLC19RO32-Frame Periodic List Capability
Read as '1', indicates 32-Frame Periodic List Capability is supported
PPCEC18ROPer-Port Change Event Capability
Read as '0', indicates per-port change event is not sup- ported
LPMC17ROLink Power Management Capability
Read as '1', indicates LPM is supported
HCP16ROHardware Prefetch Capability
Read as '0', indicates no pre-fetch capability
EECP15:8ROEHCI Extended Capabilities Pointer
Read as '0', indicates no extended capabilities are imple- mented.
IST7:4ROIsochronous Scheduling Threshold
Read as '0', indicated no caching data structure during pe- riodic schedule traversal per micro-frame
Reserved3ROReserved

ASPC

2

RO

Asynchronous Schedule Park Capability
Read as '1', host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule.

PFLF

1

RO

Programmable Frame List Flag
Read as '1', HCD can specify and use a smaller frame list and configure the host controller, the frame list must al- ways aligned on a 4K page boundary

AC

0

RO

64-bit Addressing Capability
Read as '0', indicated data structures using 32 bit address memory pointer



2.3 EHCI Companion Port Route (UHE HCSP PORTROUTE)
Address: 0x9C10210C

Reset: 0x00000000


Field NameBitAccessDescription
HCSP PORTROUTE31:0ROCompanion Port Route Description
Read as '0', not support



2.8 EHCI USB Command (UHE USBCMD)
Address: 0x9C102120
Reset: 0x00080B00


Field NameBitAccessDescription
Reserved31:28ROReserved
HIRD27:24RWHost-Initiated Resume Duration in LPM
ResumeK Length = 50us+75us*HIRD

ITC 

23:16

RW

Interrupt Threshold Control
Default 08h. This field is used by system software to select the maximum rate at which the host controller will issue interrupts. The only valid values are defined below.
Value Maximum Interrupt Interval

0x00 Reserved
0x01 1 micro-frame
0x02 2 micro-frames
0x04 4 micro-frames
0x08 8 micro-frames (default, equates to 1 ms)
0x10 16 micro-frames (2 ms)
0x20 32 micro-frames (4 ms)
0x40 64 micro-frames (8 ms)

PPCEE

15

RO

Per-Port Change Events Enable
Not support, read as '0'

FSP

14

RO

Fully Synchronized Prefetch
Not support, read as '0'

ASPE

13

RO

Asynchronous Schedule Prefetch Enable
Not support, read as '0'

PSPE

12

RO

Periodic Schedule Prefetch Enable
Not support, read as '0'

ASPME

11

RW

Asynchronous Schedule Park Mode Enable
Defaults 1, software uses this bit to enable or disable Park mode. When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled.

Reserved

10

RO

Reserved
Read as '0'

ASPMC

9:8

RW

Asynchronous Schedule Park Mode Count
Defaults 3h, it contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 1h to 3h. software must not write a zero to this bit when Park Mode Enable is a one.

LHCR

7

RO

Light Host Controller Reset
Read as '0', not support

IAAD

6

Other

Interrupt on Async Advance Doorbell
Used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell.

ASE

5

RW

Asynchronous Schedule Enable
Controls whether the host controller skips processing the
Asynchronous Schedule. Values mean:
0 Do not process the Asynchronous Schedule (default)
1 Use the PERIODICLISTBASE register to access the
Asynchronous Schedule.

PSE

4

RW

Periodic Schedule Enable
Controls whether the host controller skips processing the
Periodic Schedule. Values mean:
0 Do not process the Periodic Schedule (default)
1 Use the PERIODICLISTBASE register to access the Pe- riodic Schedule.

FLS

3:2

RW

Frame List Size
Specifies the size of the frame list. The size the frame list controls which bits in the Frame Index Register should be used for the Frame List Current index. Values mean:
0x0 1024 elements (4096 bytes) (default)
0x1 512 elements (2048 bytes)
0x2 256 elements (1024 bytes) for resource constrained environments
0x3 32 elements

HCRESET

1

Other

Host Controller Reset
Write 1, host Controller software reset, then clear this field to itself.

RS

0

RW

Run/Stop
1=Run. 0=Stop. When set to a 1, the Host Controller proceeds with execution of the schedule. When this bit is set to 0, the Host Controller completes the current and any actively pipelined transactions on the USB and then halts.Software must not write a 1 to this field unless it is in the Halted State. Note: If Test mode force enable bit is set to 1, this bit must be transmitted back to 1.



2.9 EHCI USB Status (UHE USBSTS)
Address: 0x9C102124
Reset: 0x00001000


Field NameBitAccessDescription
PCD31:16ROPort-n Change Detect
Not supported, Read as 0x0000

ASS

15

RU

Asynchronous Schedule Status
Report the current real status of the Asynchronous Sched- ule. If this bit is a zero then the status of the Asynchronous Schedule is disabled. If this bit is a one then the status of the Asynchronous Schedule is enabled. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0).

PSS

14

RU

Periodic Schedule Status
Report the current real status of the Periodic Schedule. If this bit is a zero then the status of the Periodic Schedule is disabled. If this bit is a one then the status of the Periodic Schedule is enabled. When this bit and the Periodic Sched- ule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0).

Reclamation

13

RU

Reclamation
Read-only status bit, which is used to detect an empty asynchronous schedule, refer to EHCI spec 4.8.6 for this bit's details.

HCH

12

RO

HCHalted
Set 0, whenever the Run/Stop bit is a one. Set 1, after host has stopped executing as a result of the Run/Stop bit being set to 0

Reserved

11:6

RO

Reserved
Read as '0'

IAA

5

W1C

Interrupt on Async Advance
indicates the assertion of Async Advance Doorbell inter- rupt

HSE

4

RO

Host System Error
Not support, read as '0'

FLR

3

W1C

Frame List Rollover
Indicate the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size.

PCD

2

W1C

Port Change Detect
Indicate any port for which the Port Owner bit is set to zero has a change bit transition from a zero to a one or a Force Port Resume bit transition from a zero to a one as a result of a J-K transition detected on a suspended port and the Connect Status Change being set to a one after system software has relinquished ownership of a connected port by writing a one to a port's Port Owner bit.

USBERRINT

1

W1C

USB Error Interrupt
Indicate completion of a USB transaction results in an error condition (e.g., error counter underflow).

USBINT

0

W1C

USB Interrupt
Indicate the completion of a USB transaction, which results in the retirement of a Transfer Descriptor that had its IOC bit set and a short packet is detected.



2.10 EHCI USB Interrupt Enable (UHE USBINTR)
Address: 0x9C102128
Reset: 0x00000000


Field NameBitAccessDescription
PCEE31:16ROPort-n Change Event Enable
Not supported, read as 0x0000
Reserved15:6ROReserved
IAAE5RWInterrupt on Async Advance Enable
Enable or disable Interrupt on Async Advance interrupt source in the USBSTS register.
HSEE4RWHost System Error Enable
Enable Host interrupt.
FLRE3RWFrame List Rollover Enable
Enable or disable Frame List Rollover interrupt source in the USBSTS register.
PCIE2RWPort Change Interrupt Enable
Enable or disable Port Change Detect interrupt source in the USBSTS register.
UEIE1RWUSB Error Interrupt Enable
Enable or disable USBERRINT interrupt source in the US- BSTS register.
UIE0RWUSB Interrupt Enable
Enable or disable USBINT interrupt source in the USBSTS
register.



2.11 EHCI USB Frame Index (UHE FRINDEX)
Address: 0x9C10212C

Reset: 0x00000000

Field Name

Bit

Access

Description

Reserved

31:14

RO

Reserved
Read as '0'

FI

13:0

Other

Frame Index
The value in this register increments at the end of each time frame (e.g. micro-frame). Bits [N:3] are used for the Frame List current index. This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register. Only when hc is halted it can modify this field.
USBCMD[Frame List Size] Number Elements N
0x0(1024)12
0x1(512)11
0x2(256)10
0x3(32)12



2.12 EHCI 4G Segment Selector (UHE CTRLDESSEGMENT)
Address: 0x9C102130
Reset: 0x00000000


Field NameBitAccessDescription
CTRLDSSEGMENT31:0ROControl Data Structure Segment
Not support, read as '0'


2.13 EHCI Frame List Base Address (UHE PERIODICLISTBASE)
Address: 0x9C102134
Reset: 0x00000000


Field NameBitAccessDescription
BA31:12RWBase Address
The beginning address of the periodic frame list in the sys- tem memory.
Reserved11:0ROReserved




2.14 EHCI Next Asynchronous List Address (UHE ASYNCLISTADDR)
Address: 0x9C102138
Reset: 0x00000000


Field Name

Bit

Access

Description

LPL

31:5

RW

Link Pointer Low
These bits correspond to memory address signals [31:5], respectively. This field may only reference a Queue Head (QH)

Reserved

4:0

RO

Reserved
Read as '0'



2.24 EHCI Configured Flag Register (UHE CONFIGFLAG)
Address: 0x9C102160
Reset: 0x00000000

Field Name

Bit

Access

Description

Reserved

31:1

RO

Reserved
Read as '0'

CF

0

RW

Configure Flag
0, route all ports to OHCI.
1, route all ports to EHCI.


2.25 EHCI Port Status and Control (UHE PORTSC)
Address: 0x9C102164
Reset: 0x00003000


Field NameBitAccessDescription
DEV Addr31:25RWAddress of Device which attached to this port
Used for LPM function only. A value of 0 indicates no de- vice is present
Suspend ST24:23ROSuspend Status(LPM)
These two bits are used by software to determine whether the most recent L1 request was successfull, specifically: Value Meaning
0x0 Success: State transition was successfull(ACK)
0x1 Not Yet: Device was unable to enter the L1 state at this time (NYET)
0x2 Not Supported: Device does not support the L1 state
(STALL)
0x3 Timeout/Error: Device failed to respond or an error occurred
WKOC E22ROWake on Over-current Enable
Read as '0', not support. 
WKDSCNNT E21ROWake on Disconnect Enable
Default = 0b. Writing this bit to a one enables the port to
be sensitive to device disconnects as wake-up events.
WKCNNT E20ROWake on Connect Enable
Default = 0b. Writing this bit to a one enables the port to
be sensitive to device connects as wake-up events.
PTC19:16RWPort Test Control
Default = 0000b. When this field is zero, the port is NOT
operating in a test mode. A non-zero value indicates that it is operating in test mode and the specific test mode is indicated by the specific value. The encoding of the test mode bits are (0110b - 1111b are reserved)
Bits Test Mode
0x0 Test mode not enabled
0x1 Test J STATE
0x2 Test K STATE
0x3 Test SE0 NAK
0x4 Test Packet
0x5 Test FORCE ENABLE

PI

15:14

RO

Port Indicator
Read as '0', port indicators are off.

PO

13

RW

Port Owner
This bit unconditionally goes to a 0b when the Configured bit in the CONFIGFLAG register makes a 0b to 1b tran- sition. This bit unconditionally goes to 1b whenever the Configured bit is zero. System software uses this field to release ownership of the port to a selected host controller (in the event that the attached device is not a high-speed device). Software writes a one to this bit when the attached device is not a high-speed device. A one in this bit means that a companion host controller owns and controls the port.

PP

12

RO

Port Power
Read as '1', Each port always power on

LS

11:10

RU

Line Status
These bits reflect the current logical levels of the D+ (bit
11) and D- (bit 10) signal lines. These bits are used for detection of low-speed USB devices prior to the port reset and enable sequence. This field is valid only when the port enable bit is zero and the current connect status bit is set to a one. The encoding of the bits are:
Bits[11:10] USB State Interpretation
00b SE0 Not Low-speed device, perform EHCI reset
10b J-state Not Low-speed device, perform EHCI
reset
01bK-stateLow-speed device, release ownership of port
11b Undefined Not Low-speed device, perform EHCI
reset.

Suspend L1

9

RW

Suspend using LPM L1
0b = Suspend using L2; 1b = Suspend using L1(LPM). When this bit is set to a one and a non-zero value is spec- ified in the Device Address field the host will generate an LPM Token to enter the L1 state whenver software writes a one to the Suspend bit.

PR

8

Other

Port Reset
1=Port is in Reset. 0=Port is not in Reset. When software writes a one to this bit (from a zero), the bus reset sequence is started. Software writes a zero to this bit to terminate the bus reset sequence only when the reset time is 10ms long enough.

Suspend

7

Other

Suspend
1=Port in suspend state. 0=Port not in suspend state. Port Enabled Bit and Suspend bit of this register define the port states as follows:
Bits [Port Enabled, Suspend] Port State
0XDisable
10Enable
11Suspend
When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction, if a transac- tion was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. A write of zero to this bit is ignored by the host controller.

FPR

6

RW

Force Port Resume
1= Resume detected/driven on port. 0=No resume (K
state) detected/driven on port. Software sets this bit to a
1 to drive resume signaling. The Host Controller sets this bit to a 1 if a J-to-K transition is detected while the port is in the Suspend state. Software Writes a zero (from one) causes the port to return to highspeed mode (forcing the bus below the port into a high-speed idle).

OCC

5

RO

Over-current Change
Not support

OCA

4

RO

Over-current Active
Not support

PEC

3

W1C

Port Enable/Disable Change
1=Port enabled/disabled status has changed. 0=No change. Default = 0. For the root hub, this bit gets set to a one only when a port is disabled due to the appropriate conditions existing at the EOF2 point. Software clears this bit by writing a 1 to it.

PE

2

Other

Port Enabled/Disabled
1=Enable. 0=Disable. Software cannot enable a port by writing a one to this field. The host controller will only set this bit to a one when the reset sequence determines that the attached device is a high-speed device. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by host software.

CSC

1

W1C

Connect Status Change
1=Change in Current Connect Status. 0=No change. Indi- cates a change has occurred in the port's Current Connect Status.

CCS

0

RO

Current Connect Status
1=Device is present on port. 0=No device is present.




Group 8 USB OTG Controller

8.0 OTG transceiver work mode select (MODE SELECT)

Address: 0x9C102400 

Reset: 0x0


Field Name

Bit

Access

Description

Reserved

31:5

RO

Reserved


SIM MODE


4


RW


simulation mode select, to reduce simulation time
0:Disbale(default)
1:Enable

ADP SUPPORT

3

RW

support or not
0: Not Support(default)
1: Support

SRP SUPPORT

2

RW

support or not
0: Not Support(default)
1: Support

WORK MODE

1:0

RW

work mode select
0x0: OTG2.0(default)
0x1: OTG1.2/1.3
0x2: HOST ONLY
0x3: DEVICE ONLY



8.1 A/B-device control reg (OTG DEVICE CTRL)
Address: 0x9C102404
Reset: 0x0

Field Name

Bit

Access

Description

Reserved

31:6

RO

Reserved

B HNP EN

5

Other

B-device has successfully accepted A-device set ture(b hnp en) cmd
0:no
1:yes

B BUS REQ

4

RW

B-device wants to use the bus or not
0:no(default)
1:yes

A CLR ERR

3

Other

to clear a vbus err due to an overcurrent condition and causes the A-device to transition to a wait vfall
1T pulse

A SET B HNP EN

2

RW

A-device has successfully set the b hnp enable bit in the
B-device,self-clean by inner FSM state
0: no(defrault)
1: yes

A BUS REQ

1

RW

A-device wants to use the bus
when it is 0, FSM will goto "a suspend". Vbus is still ON
0: no(default)
1: yes

A BUS DROP

0

Other

A-device wants to power down the bus
when it is 1, FSM will goto "a wait vfall". Vbus is OFF
when a bus drop=1 => a bus req=0



8.2 OTG transceiver interrupt enable (OTG INT EN)
Address: 0x9C102408
Reset:0 x0



Field NameBitAccessDescription
Reserved31:10ROReserved
ADP CHANGE EN9RWadp change
0: Disable(default)
1: Enable
A SRP DET EN8RWA-device has detected SRP
0: Disable(default)
1: Enable
B AIDL BDIS EN7RWB-device disconnects to A-device to start HNP
0: Disable(default)
1: Enable
A BIDL ADIS EN6RWA-device disconnects to B-device to end HNP
0: Disable(default)
1: Enable
A AIDL BDIS TMOUT EN5RWwaiting for a disconnect tmout when HNP
0: Disable(default)
1: Enable

B SRP FAIL EN

4

RW

B-Device SRP fail
0: Disable(default)
1: Enable

BDEV CONNECT TMOUT EN

3

RW

A-Device waits B-Device Connect timeout
0: Disable(default)
1: Enable

VBUS RISE TMOUT EN

2

RW

A-Device waits vbus valid timeout
0: Disable(default)
1: Enable

ID CHANGE EN

1

RW

id pin has changed
0: Disable(default)
1: Enable

OVERCURRENT EN

0

RW

an attached B-device draws more current
0: Disable(default)
1: Enable



8.3 OTG transceiver status and interrupt flag (OTG ST)
Address: 0x9C10240C

Reset: 0x0001 0000


Field NameBitAccessDescription
Reserved31:17ROReserved
ID16ROthe sampling value of the analog Id line
used in OTG mode
Default:1
Reserved15:10ROReserved
ADP CHANGE IF9Otheradp change
high active, write 1 to clear this flag
A SRP DET IF8OtherA-device has detected SRP
high active, write 1 to clear this flag
B AIDL BDIS IF7OtherB-device disconnects to A-device to start HNP
high active, write 1 to clear this flag
A BIDL ADIS IF6OtherA-device disconnects to B-device to end HNP
high active, write 1 to clear this flag
A AIDL BDIS TMOUT IF5Otherwaiting for a disconnect tmout when HNP
high active, write 1 to clear this flag

B SRP FAIL IF

4

Other

B-Device SRP fail
high active, write 1 to clear this flag

BDEV CONNECT TMOUT IF

3

Other

A-Device waits B-Device Connect timeout
high active, write 1 to clear this flag

VBUS RISE TMOUT IF

2

Other

A-Device waits vbus valid timeout
high active, write 1 to clear this flag

ID CHANGE IF

1

Other

id pin has changed
high active, write 1 to clear this flag

OVERCURRENT IF

0

Other

an attached B-device draws more current
high active, write 1 to clear this flag



8.4 Wait voltage on Vbus to go into regulation (A WAIT VRISE TMR)
Address: 0x9C102410
Reset: 0x0001 86A0


Field NameBitAccessDescription
Reserved31:17ROReserved
A WAIT VRISE TMR16:0RWused by A-device to wait for the voltage on Vbus to go into regulation
Default:0x186a0(100ms, spec max)



8.5 Session end to SRP init (B SSEND SRP TMR)
Address: 0x9C102414
Reset: 0x0016 E360


Field NameBitAccessDescription
Reserved31:21ROReserved
B SSEND SRP TMR20:0RWsession end to SRP init
Default:0x16E360(1.5s ,spec min)



8.6 SE0 time before SRP (B SE0 SRP TMR)
Address: 0x9C102418
Reset: 0x000F 4240


Field NameBitAccessDescription
Reserved31:20ROReserved
B SE0 SRP TMR19:0RWSE0 time before SRP
Default:0xF4240(1s ,spec min)



8.7 Data-line pulse time (B DATA PLS TMR)
Address: 0x9C10241C

Reset: 0x0000 1B58


Field NameBitAccessDescription
Reserved31:14ROReserved
B DATA PLS TMR13:0RWData-line pulse time
Default:0x1B58(7ms ,spec: 5ms-10ms)



8.8 SRP fail time (B SRP FAIL TMR)
Address: 0x9C102420
Reset: 0x005B 8D80


Field NameBitAccessDescription
Reserved31:23ROReserved
B SRP FAIL TMR22:0RWSRP fail time
Default:0x5B8D80(6s ,spec max)



8.9 Session valid to B-connect (B SVLD BCON TMR)
Address: 0x9C102424
Reset: 0x0001 86A0


Field NameBitAccessDescription
Reserved31:20ROReserved
B SVLD BCON TMR19:0RWSession valid to B-connect
Default:0x186A0(100ms ,spec: 1s max)



8.10 A-idle to B-disconnect time (B AIDL BDIS TMR)
Address: 0x9C102428
Reset: 0x0000 1388


Field NameBitAccessDescription
Reserved31:18ROReserved
B AIDL BDIS TMR17:0RWA-idle to B-disconnect time
Default:0x1388(5ms)



8.11 B-disconnect to A-connect time (A BDIS ACON TMR)
Address: 0x9C10242C

Reset: 0x0000 2710


Field NameBitAccessDescription
Reserved31:18ROReserved
A BDIS ACON TMR17:0RWB-disconnect to A-connect time
Default:0x2710(10ms)



8.12 Local disconnect to data line discharge time (LDIS DSCHG TMR)

Address: 0x9C102430
Reset: 0x0000 0015


Field Name

Bit

Access

Description

Reserved

31:5

RO

Reserved

LDIS DSCHG TMR

4:0

RW

Local disconnect to data line discharge time
Default:0x15(25us)



8.13 B-connect short debounce (A BCON SDB TMR)
Address: 0x9C102434
Reset: 0x0000 0003


Field NameBitAccessDescription
Reserved31:17ROReserved
A BCON SDB TMR16:0RWB-Connect short de-bounce
Default:0x00003(3us)



8.14 B-connect long debounce (A BCON LDB TMR)
Address: 0x9C102438
Reset: 0x0001 86A0


Field NameBitAccessDescription
Reserved31:17ROReserved
A BCON LDB TMR16:0RWB-connect long de-bounce
Default:0x186A0(100ms)



8.15 A-device ADP probing period (A ADP PRB TMR)
Address: 0x9C10243C

Reset:0x001A B3F0


Field NameBitAccessDescription
Reserved31:22ROReserved
A ADP PRB TMR21:0RWA-device ADP probing period
Default:0x1AB3F0(1.75s)



8.16 B-device ADP probing period (B ADP PRB TMR)
Address: 0x9C102440
Reset: 0x001E 8480

Field NameBitAccessDescription
Reserved31:22ROReserved
B ADP PRB TMR21:0RWB-device ADP probing period
Default:0x1E8480(2s)



8.17 B-device ADP detach time (B ADP DETACH TMR)
Address: 0x9C102444
Reset: 0x0030 D400


Field NameBitAccessDescription
Reserved31:22ROReserved
B ADP DETACH TMR21:0RWB-device ADP detach time
Default:0x30D400(3.2s ,spec: 3s-3.4s)



8.18 ADP change precision (ADP CHNG PRECISION)
Address: 0x9C102448
Reset: 0x0000 01FF


Field NameBitAccessDescription
Reserved31:12ROReserved
ADP CHNG PRECISION11:0RWADP change precision
Default:0x1FF(512us)



8.19 Seesion end to Votg vbus lkg (A WAIT VFALL TMR)
Address: 0x9C10244C

Reset: 0x000F 4240


Field NameBitAccessDescription
Reserved31:20ROReserved
A WAIT VFALL TMR19:0RWSeesion end to Votg vbus lkg
Default:0xF4240(1s)



8.20 Wait for B-connect time (A WAIT BCON TMR)
Address: 0x9C102450
Reset: 0x0010 C8E0


Field NameBitAccessDescription
Reserved31:25ROReserved
A WAIT BCON TMR24:0RWWait for B-connect time
Default:0x10C8E0(1.1s)



8.21 A-idle to B-disconnect time (A AIDL BDIS TMR)
Address: 0x9C102454
Reset: 0x0003 0D40


Field NameBitAccessDescription
Reserved31:18ROReserved
A AIDL BDIS TMR17:0RWA-idle to B-disconnect time
Default:0x30D40(200ms)



8.22 A-SE0 to B-reset time (B ASE0 BRST TMR)
Address: 0x9C102458
Reset: 0x0002 5D78


Field NameBitAccessDescription
Reserved31:18
Reserved
B ASE0 BRST TMR17:0
A-SE0 to B-reset time
Default:0x25D78(155ms)



8.23 B-idle to A-disconnect time (A BIDL ADIS TMR)
Address: 0x9C10245C

Reset: 0x0002 5D78


Field NameBitAccessDescription
Reserved31:18ROReserved
A BIDL ADIS TMR17:0RWB-idle to A-disconnect time
Default:0x25D78(155ms)



8.24 ADP Dis-Charge VBus time (ADP CHRG TIME)
Address: 0x9C102460
Reset: 0x0000 0898


Field NameBitAccessDescription
Reserved31:13ROReserved
ADP CHRG TIME12:0RWADP Dis-Charge VBUS time
Default:0x0898(2.2ms, This is also used as the maximum time for charge VBUS)



8.25VBUS Pulse time (VBUS PULSE TIME)
Address: 0x9C102464
Reset: 0x0000 7530


Field NameBitAccessDescription
Reserved31:15ROReserved
VBUS PULSE TIME14:0RWVBus pulse time
Default:0x7530(30ms)



8.26 A B-con SDB window time (A BCON SDB WIN)
Address: 0x9C102468
Reset: 0x0001 86A0


Field NameBitAccessDescription
Reserved31:17ROReserved
A BCON SDB WIN16:0RWA B-Con SDB window time
Default:0x186A0(100ms)



8.27 OTG Transceiver debug registers (OTG DEBUG REG)

Address: 0x9C10246C

Reset: 0x0000 0088


Field Name

Bit

Access

Description

Reserved

31:30

RO

Reserved

ADPC1

29:16

RO

A rising couner1 for debug
Default: 0x0

SEND

15:14

RO

Sessend from PHY
Default:0x0

VVLD

13:12

RO

VBUS Valid from PHY
Default:0x0

BVLD

11:10

RO

B VBUS vallid from PHY
Default:0x0

AVLD

9:8

RO

A VBUS valid from PHY
Default:0x0

FSM PS

7:4

RO

OTG FSM previous state when enter vbus error
Default:0x8

FSM CS

3:0

RO

OTG FSM current state
Default:0x8



8.28 OTG ADP rising Couner for debug (OTG ADPCNT REG)
Address: 0x9C102470
Reset: 0x0


Field NameBitAccessDescription
Reserved31:30ROReserved

ADPC0

29:16

RO

A rising couner0 for debug
Default: 0x0

Reserved

15:14

RO

Reserved

ADPC2

13:0

RO

A rising couner2 for debug
Default: 0x0



8.29 A-device ADP drive Vbus time when detect change (A ADP VBUS)
Address: 0x9C102474
Reset: 0x1A B3F0


Field NameBitAccessDescription
Reserved31:22ROReserved
ADP VBUS TIM21:0RWA-device ADP drive vubs time
This timer is started at the beginning of dis-charge vbus



 
Group 16 USB Device: DMA Control

16.0 EP12 DMA Control Status (UEP12DMACS)
Address: 0x9C102800
Reset: 0x0800 0000


Field NameBitAccessDescription
DMA EN31OtherDMA enable, it will be auto-clear to 0 when DMA fin- ishes
DMA Flush End30RWWhen dma fifo flush = 1
0: DMA fifo is flushing(default)
1: flushing DMA fifo is complete
DMA FIFO Flush29RWFlush DMA
data port: Clear fifo, master: Send/Get the last packet then clear fifo;
when dma fifo flush will be written as 1, other bits, except
dma fifo flush end, will not be writable at the same time
DMA Write28RW0: DMA Read Data from Memory/IO to USB host(default)
1: DMA Write Data to Memory/IO from USB Host
Count align27RWbulk out dma length alignment
0: 32B alignment
1:hs, 512B alignment; fs, 64B alignment (refer to
NOTE)(default)
Reserved26:22ROReserved
Default:0x0
DMA ByteCount21:0OtherDMA Transfer Length



16.1 EP12 DMA Data Address (UEP12DMADA)
Address: 0x9C102804
Reset: 0x0


Field NameBitAccessDescription
DMA ADDR31:0RWDMA address
must 32B alignment
Default:0x0



16.2 Audio DMA Control Status (UDADMAS)
Address: 0x9C102808
Reset: 0x0


Field NameBitAccessDescription
DMA EN31OtherDMA enable, it will be auto-clear to 0 when DMA finishes
DMA Flush30RWDMA flush bit, it will be set to 1 when write 1
0: DMA fifo is flushing(default)
1: flushing DMA fifo is complete
Reserved29:16ROReserved
DMA ByteCount15:0OtherDMA Transfer Length



16.3 Audio DMA Data Address (UDADMADA)
Address: 0x9C10280C

Reset: 0x0


Field NameBitAccessDescription
DMA ADDR31:0RWDMA address
must 32B alignment default:0x0



16.4 EP89 DMA Control Status (UEP89DMACS)
Address: 0x9C102810
Reset: 0x0800 0000


Field NameBitAccessDescription
DMA EN31OtherDMA enable, it will be auto-clear to 0 when DMA finishes
DMA Flush End30RWWhen dma fifo flush = 1
0: DMA fifo is flushing(default)
1: flushing DMA fifo is complete
DMA FIFO Flush29OtherFlush DMA
data port: Clear fifo, master: Send/Get the last packet then clear fifo;
when dma fifo flush will be written as 1, other bits, except
dma fifo flush end, will not be writable at the same time
DMA Write28RW0: DMA Read Data from Memory/IO to USB host(default)
1: DMA Write Data to Memory/IO from USB Host
Count align27RWbulk out dma length alignment
0: 32B alignment
1:hs, 512B alignment; fs, 64B alignment (refer to
NOTE)(default)
Reserved26:22ROReserved
DMA ByteCount21:0OtherDMA Transfer Length



16.5 EP89 DMA Data Address (UEP89DMADA)
Address: 0x9C102814
Reset: 0x0


Field NameBitAccessDescription
DMA ADDR31:0RWDMA address
must 32B alignment



16.6 EPAB DMA Control Status (UEPABDMACS)
Address: 0x9C102818
Reset: 0x0800 0000


Field NameBitAccessDescription
DMA EN31OtherDMA enable, it will be auto-clear to 0 when DMA finishes
DMA Flush End30RWWhen dma fifo flush = 1
0: DMA fifo is flushing(default)
1: flushing DMA fifo is complete
DMA FIFO Flush29RWFlush DMA
data port: Clear fifo, master: Send/Get the last packet then clear fifo;
when dma fifo flush will be written as 1, other bits, except
dma fifo flush end, will not be writable at the same time
DMA Write28RW0: DMA Read Data from Memory/IO to USB host(default)
1: DMA Write Data to Memory/IO from USB Host
Count align27RWbulk out dma length alignment
0: 32B alignment
1:hs, 512B alignment; fs, 64B alignment (refer to
NOTE)(default)
Reserved26:22ROReserved
DMA ByteCount21:0OtherDMA Transfer Length



16.7 EPAB DMA Data Address (UEPABDMADA)
Address: 0x9C10281C

Reset: 0x0


Field NameBitAccessDescription
DMA ADDR31:0RWDMA address
must 32B alignment
Default:0x0



16.8 Video DMA Control Status (UDVDMACS)
Address: 0x9C102820
Reset: 0x0


Field NameBitAccessDescription

DMA EN

31

Other

DMA enable, it will be auto-clear to 0 when DMA fin- ishes

DMA Flush

30

RW

DMA flush bit, it will be set to 1 when write 1
0: DMA fifo is flushing(default)
1: flushing DMA fifo is complete

Reserved

29:22

RW

Reserved
Default:0x0

DMA ByteCount

21:0

Other

DMA Transfer Length



16.9 Video DMA Data Address (UDADMADA)
Address: 0x9C102824
Reset: 0x0


Field NameBitAccessDescription
DMA ADDR31:0RWDMA address
must 32B alignment
Default:0x0



16.10 EPC DMA Control Status (UDEPCDMACS)
Address: 0x9C102828
Reset: 0x0


Field NameBitAccessDescription
DMA EN31OtherDMA enable, it will be auto-clear to 0 when DMA finishes
DMA Flush30RWDMA flush bit, it will be set to 1 when write 1
0: DMA fifo is flushing(default)
1: flushing DMA fifo is complete
Reserved29:22ROReserved
DMA ByteCount21:0OtherDMA Transfer Length


16.11 EPC DMA Data Address (UDEPCDMADA)
Address: 0x9C10282C

Reset: 0x0


Field NameBitAccessDescription
DMA ADDR31:0RWDMA address
must 32B alignment
Default:0x0



16.12 EP2 DMA Control Status (UDEP2DMACS)
Address: 0x9C102830
Reset: 0x0800 0000


Field NameBitAccessDescription
DMA EN31OtherDMA enable, it will be auto-clear to 0 when DMA finishes
DMA Flush End30RWWhen dma fifo flush = 1
0: DMA fifo is flushing
1: flushing DMA fifo is complete
DMA FIFO Flush29RWRWFlush DMA
data port: Clear fifo, master: Send/Get the last packet then clear fifo;
when dma fifo flush will be written as 1, other bits, except
dma fifo flush end, will not be writable at the same time
DMA Write28
0:DMA Read Data from Memory/IO to USB host(default)
1:DMA Write Data to Memory/IO from USB Host
Count align27RWbulk out dma length alignment
0: 32B alignment
1:hs, 512B alignment; fs, 64B alignment (refer to
NOTE)(default)
Reserved26:22
Reserved
DMA ByteCount21:0OtherDMA Transfer Length


16.13 EP2 DMA Data Address (UDEP2DMADA)
Address: 0x9C102834
Reset: 0x0000 0000  


Field NameBitAccessDescription
DMA ADDR31:0RWDMA address
must 32B alignment
Default:0x0



16.14 EP9 DMA Control Status (UDEP9DMACS)
Address: 0x9C102838
Reset: 0x0800 0000

Field NameBitAccessDescription
DMA EN31OtherDMA enable, it will be auto-clear to 0 when DMA finishes
DMA Flush End30RWWhen dma fifo flush = 1
0: DMA fifo is flushing
1: flushing DMA fifo is complete
DMA FIFO Flush29RWRWFlush DMA
data port: Clear fifo, master: Send/Get the last packet then clear fifo;
when dma fifo flush will be written as 1, other bits, except
dma fifo flush end, will not be writable at the same time
DMA Write28

Full Name ?

0:DMA Read Data from Memory/IO to USB host(default)
1:DMA Write Data to Memory/IO from USB Host

Count align27RWbulk out dma length alignment
0: 32B alignment
1:hs, 512B alignment; fs, 64B alignment (refer to
NOTE)(default)
Reserved26:22
Reserved
DMA ByteCount21:0OtherDMA Transfer Length



16.15 EP9 DMA Data Address (UDEP9DMADA)
Address: 0x9C10283C

Reset: 0x0000 0000  



Field NameBitAccessDescription
DMA ADDR31:0RWDMA address
must 32B alignment
Default:0x0



16.16 EPB DMA Control Status (UDEPBDMACS)
Address: 0x9C102840
Reset:0x0000 0000  

Field NameBitAccessDescription
DMA EN31OtherDMA enable, it will be auto-clear to 0 when DMA finishes
DMA Flush End30RWWhen dma fifo flush = 1
0: DMA fifo is flushing
1: flushing DMA fifo is complete
DMA FIFO Flush29RWRWFlush DMA
data port: Clear fifo, master: Send/Get the last packet then clear fifo;
when dma fifo flush will be written as 1, other bits, except
dma fifo flush end, will not be writable at the same time
DMA Write28

Full Name ?

0:DMA Read Data from Memory/IO to USB host(default)
1:DMA Write Data to Memory/IO from USB Host

Count align27RWbulk out dma length alignment
0: 32B alignment
1:hs, 512B alignment; fs, 64B alignment (refer to
NOTE)(default)
Reserved26:22
Reserved
DMA ByteCount21:0OtherDMA Transfer Length



16.17 EPB DMA Data Address (UDEPBDMADA)
Address:0x9C102844
Reset:0x0000 0000 


Field NameBitAccessDescription
DMA ADDR31:0RWDMA address
must 32B alignment
Default:0x0




Group 17 USB Device: System Domain Interrupt

17.0 Controller Control Status (UDCCS)
Address: 0x9C102880
Reset: 0xE000 0000


Field NameBitAccessDescription
USB CLK EN31ROUSB clock enable status signal
0:Disable
1:Enable(default)
PARTIAL30RWUSB PHY partial control signal
0: USB PHY clock control by suspend signal
1: USB PHY clock enable(default)
SUSPENDM29RWUSB PHY suspend control signal
Default:0x1
Issue Resume28other1:write 1(pulse) will force RESUME-K on D+D- 0:normal
Reserved27:26
Reserved
VBUS PRE25ROUSB VBUS signal sync to system domain
Default:0x0
VBUS24ROUSB VBUS
Default:0x0
Reserved23:16ROReserved
VBUS Sample Period15:0RWSet the sample period to sample USB VBUS
If set N, it will be sampled every (N+1) system clock cycles
Default:0x0



17.1 Controller Interrupt Enable (UDCIE)
Address: 0x9C102884
Reset: 0x0000 0000 


Field NameBitAccessDescription
Reserve31:16ROReserve
EPC TRB IE15RWEP12 TRB done interrupt enable
0:Disable(default)
1:Enable
VIDEO TRB IE14RWVideo TRB done interrupt enable
0:Disable(default)
1:Enable
AUDIO TRB IE13RWAudio TRB done interrupt enable
0:Disable(default)
1:Enable
EPC ERF IE12RWEP12 Event Ring Full interrupt enable
0:Disable(default)
1:Enable
VIDEO ERF IE11RWVideo Event Ring Full interrupt enable
0:Disable(default)
1:Enable
AUDIO ERF IE10RWAudio Event Ring Full interrupt enable
0:Disable(default)
1:Enable
EPB DMA IE9RWEP11 DMA finish interrupt enable
0:Disable(default)
1:Enable
EP9 DMA IE8RWEP9 DMA finish interrupt enable
0:Disable(default)
1:Enable
EP2 DMA IE7RWEP2 DMA finish interrupt enable
0:Disable(default)
1:Enable
EPC DMA IE6RWEPC DMA finish interrupt enable
0:Disable(default)
1:Enable

VIDEO DMA IE

5

RW

VIDEO DMA finish interrupt enable
0:Disable(default)
1:Enable

EPAB DMA IE

4

RW

EP10/11 DMA finish interrupt enable
0:Disable(default)
1:Enable

EP89 DMA IE

3

RW

EP89 DMA finish interrupt enable
0:Disable(default)
1:Enable

AUDIO DMA IE

2

RW

AUDIO DMA finish interrupt enable
0:Disable(default)
1:Enable

EP12 DMA IE

1

RW

EP12 DMA finish interrupt enable
0:Disable(default)
1:Enable

VBUS IE

0

RW

VBUS interrupt enable
0:Disable(default)
1:Enable



17.2 Controller Interrupt Flag (UDCIF)
Address: 0x9C102888
Reset: 0x0000 0000 


Field NameBitAccessDescription
Reserve31:16ROReserve
EPC TRB IF15W1CEP12 TRB done interrupt flag
Indicates the TRB with IOC bit set has been transfered and the status TRB has been write to Event Ring
VIDEO TRB IF14W1CVideo TRB done interrupt flag
Indicates the TRB with IOC bit set has been transfered and the status TRB has been write to Event Ring
AUDIO TRB IF13W1CAudio TRB done interrupt flag
Indicates the TRB with IOC bit set has been transfered and the status TRB has been write to Event Ring
EPC ERF IF12W1CEP12 Event Ring Full interrupt flag
VIDEO ERF IF11W1CVideo Event Ring Full interrupt flag

AUDIO ERF IF

10

W1C

Audio Event Ring Full interrupt flag


EPB DMA IF


9


W1C


EP11 DMA finish interrupt flag


EP9 DMA IF


8


W1C


EP9 DMA finish interrupt flag


EP2 DMA IF


7


W1C


EP2 DMA finish interrupt flag


EPC DMA IF


6


W1C


EPC DMA finish interrupt flag


VIDEO DMA IF


5


W1C


VIDEO DMA finish interrupt flag


EPAB DMA IF


4


W1C


EP10/11 DMA finish interrupt flag


EP89 DMA IF


3


W1C


EP89 DMA finish interrupt flag


AUDIO DMA IF


2


W1C


AUDIO DMA finish interrupt flag


EP12 DMA IF


1


W1C


EP12 DMA finish interrupt flag


VBUS IF


0


W1C


VBUS interrupt flag



17.16 Audio DMA Command Ring Control (UDADMA CRCR)
Address: 0x9C1028C0
Reset: 0x0000 0000 

Field Name

Bit

Access

Description

CRPTR

31:6

RW

Command Ring Pointer
The command ring should be 64bytes aligned
Default:0x0

Reserved

5:4

RO

Reserved

CRR

3

RO

Command Ring Running
Indicates the command ring is running, SW change the pointer when this bit is cleared Default:0x0

Reserved

2

RO

Reserved

CS

1

Other

Command Ring Stop
Write 1 to stop the command ring

RCS

0

RW

Ring Cycle State
Indicates the initial state of ring cycle bit
Default:0x0



17.17 Audio DMA Event Ring Base Address (UDADMA ERBAR)
Address: 0x9C1028C4
Reset: 0x0000 0000 

Field Name

Bit

Access

Description

ERBA

31:4

RW

Event Ring Base Address
The first TRB of the status will be write to this address
Default:0x0

Reserved

3:0

RW

Reserved
Default:0x0



17.18 Audio DMA Event Ring De-queue Pointer (UDADMA ERDPR)
Address: 0x9C1028C8
Reset: 0x0000 0000

Field Name

Bit

Access

Description

ERDP

31:4

RW

Event Ring De-queue Pointer
Indicates the TRB address of which the CPU is processing now
Default:0x0

Reserved

3:0

RW

Reserved
Default:0x0



17.19 Audio DMA Ring Control and Status (UDADMA RCSR)
Address: 0x9C1028CC

Reset: 0x0000 0000 


Field Name

Bit

Access

Description

EN

31

RW

Auto DMA enable
To enable the auto DMA feature
0:Disable(default)
1:Enable

ERF

30

Other

Event ring Full
Indicates the Event Ring has been writing full

Reserved

29:16

RO

Reserved

Size

15:0

RW

Event Ring Size
HW will write to ERBA if the size reaches this value and
ERDP != ERBA Default:0x0



17.20 Audio DMA Ring Trig (UDADMA RTR)
Address: 0x9C1028D0
Reset: 0x0000 0000 


Field Name

Bit

Access

Description

Reserved31:1ROReserved
CRT0OtherCommand Ring Trig
After SW write a '1' to this bit, HW will start transfer TRBs until the ring is empty or stopped



17.21 Video DMA Command Ring Control (UDVDMA CRCR)
Address: 0x9C1028D4
Reset: 0x0000 0000 

Field Name

Bit

Access

Description

CRPTR

31:6

RW

Command Ring Pointer
The command ring should be 64bytes aligned
Default:0x0

Reserved

5:4

RO

Reserved

CRR

3

RO

Command Ring Running
Indicates the command ring is running, SW can only change the pointer when this bit is cleared
Default:0x0

Reserved

2

RO

Reserved


CS


1


Other


Command Ring Stop
Write 1 to stop the command ring

RCS

0

RW

Ring Cycle State
Indicates the initial state of ring cycle bit
Default:0x0




17.22 Video DMA Event Ring Base Address (UDVDMA ERBAR)
Address: 0x9C1028D8
Reset: 0x0000 0000 

Field Name

Bit

Access

Description

ERBA

31:4

RW

Event Ring Base Address
The first TRB of the status will be write to this address
Default:0x0

Reserved

3:0

RW

Reserved
Default:0x0



17.23 Video DMA Event Ring De-queue Pointer (UDVDMA ERDPR)
Address: 0x9C1028DC

Reset: 0x0000 0000  

Field Name

Bit

Access

Description

ERDP

31:4

RW

Event Ring De-queue Pointer
Indicates the TRB address of which the CPU is processing now
Default:0x0

Reserved

3:0

RW

Reserved
Default:0x0


17.24 Video DMA Ring Control and Status (UDVDMA RCSR)
Address: 0x9C1028E0
Reset: 0x0000 0000  


Field Name

Bit

Access

Description

EN31RWAuto DMA enable
To enable the auto DMA feature
0:Disbale(default)
1:Enable
ERF30OtherEvent ring Full
Indicates the Event Ring has been writing full
Reserved29:16ROReserved
Size15:0RWEvent Ring Size
HW will write to ERBA if the size reaches this value and
ERDP != ERBA Default:0x0



17.25 Video DMA Ring Trig (UDVDMA RTR)
Address: 0x9C1028E4
Reset: 0x0000 0000 


Field Name

Bit

Access

Description

Reserved31:1ROReserved
CRT0OtherCommand Ring Trig
After SW write a '1' to this bit, HW will start transfer TRBs until the ring is empty or stopped



17.26 EPC DMA Command Ring Control (UDEPCDMA CRCR)
Address: 0x9C1028E8
Reset: 0x0000 0000 


Field Name

Bit

Access

Description

CRPTR

31:6

RW

Command Ring Pointer
The command ring should be 64bytes aligned
Default:0x0

Reserved

5:4

RO

Reserved

CRR

3

RO

Command Ring Running
Indicates the command ring is running, SW change the pointer when this bit is cleared Default:0x0

Reserved

2

RO

Reserved

CS


1

Other

Command Ring Stop
Write 1 to stop the command ring

RCS

0

RW

Ring Cycle State
Indicates the initial state of ring cycle bit
Default:0x0



17.27 EPC DMA Event Ring Base Address (UDEPCDMA ERBAR)
Address: 0x9C1028EC

Reset: 0x0000 0000  

Field Name

Bit

Access

Description

ERBA

31:4

RW

Event Ring Base Address
The first TRB of the status will be write to this address
Default:0x0

Reserved

3:0

RW

Reserved
Default:0x0



17.28 EPC DMA Event Ring De-queue Pointer (UDEPCDMA ERDPR)
Address :0x9C1028F0
Reset: 0x0000 0000 


Field Name

Bit

Access

Description

ERDP

31:4

RW

Event Ring De-queue Pointer

Indicates the TRB address of which the CPU is processing now

Default:0x0

Reserved

3:0

RW

Reserved



17.29 EPC DMA Ring Control and Status (UDEPCDMA RCSR)
Address: 0x9C1028F4
Reset: 0x0000 0000  


Field Name

Bit

Access

Description

EN31RWAuto DMA enable
To enable the auto DMA feature
0:Disable(default)
1:Enable
ERF30OtherEvent ring Full
Indicates the Event Ring has been writing full
Reserved29:16ROReserved
Size15:0RWEvent Ring Size
HW will write to ERBA if the size reaches this value and
ERDP != ERBA Default:0x0



17.30 EPC DMA Ring Trig (UDEPCDMA RTR)
Address: 0x9C1028F8
Reset: 0x0000 0000  


Field Name

Bit

Access

Description

Reserved31:1ROReserved
CRT0OtherCommand Ring Trig
After SW write a '1' to this bit, HW will start transfer TRBs until the ring is empty or stopped



Group 18 USB Device: EP0/1/2/3/4 Control


18.0 Linker Layer Controller Setting (UDLCSET)
Address: 0x9C102900
Reset: 0x0000 0101


Field Name

Bit

Access

Description

Reserve31:20ROReserve
CURR LINSTATE19:18ROcurrent linstate
Default:0x0
Reserve17ROReserve
CURR ALT16:13ROcurrent alternate-setting
Default:0x0
CURR INTF12:9ROcurrent interface number
Default:0x0
CURR SPEED8ROcurrent speed
0: high speed;
1: full speed(default)
Reserve7:6ROReserve
SUPP SYNCFRAME5RWsupport SYNCFRAME command or not
0: not support(default);
1: support
SUPP SETDESC4RWsupport SET DESCRIPTOR command or not
0: not support(default);
1: support
NEG SAMPLE EN3RWnegedge phyclk samples the phy output signals enable to avoid the hold time violation
Default:0x0
FORCE FULLSP2RWforce device to work at full speed
0: normal(default);
1: force full speed
SIM MODE1RWincrease simulation speed by reduce couter threshold
0: normal(default);
1: sim mode
SOFT DISC0RWsoft disconnect from host
0: connect to host;
1: soft disconnect(default)



18.1 Linker Layer Controller Stall Control (UDLCSTL)
Address: 0x9C102904
Reset: 0x0000 0000  


Field Name

Bit

Access

Description

Reserve31:27ROReserve
CLREPDSTL26OtherClear EP13 Stall
CLREPBSTL25OtherClear EP11 Stall
CLREPASTL24OtherClear EP10 Stall
CLREP9STL23OtherClear EP9 Stall
CLREP8STL22OtherClear EP8 Stall
CLREP6STL21OtherClear EP6 Stall
CLREP4STL20OtherClear EP4 Stall
CLREP3STL19OtherClear EP3 Stall
CLREP2STL18OtherClear EP2 Stall
CLREP1STL17OtherClear EP1 Stall
CLREP0STL16OtherClear EP0 Stall
Reserve15:11ROReserve
SETEPDSTL10OtherSet EP13 Stall
SETEPBSTL9OtherSet EP11 Stall
SETEPASTL8OtherSet EP10 Stall

SETEP9STL

7

Other

Set EP9 Stall


SETEP8STL


6


Other


Set EP8 Stall


SETEP6STL


5


Other


Set EP6 Stall


SETEP4STL


4


Other


Set EP4 Stall


SETEP3STL


3


Other


Set EP3 Stall


SETEP2STL


2


Other


Set EP2 Stall


SETEP1STL


1


Other


Set EP1 Stall


SETEP0STL


0


Other


Set EP0 Stall



18.3 Device address (UDLCADDR)
Address: 0x9C10290C

Reset: 0x0000 0000 


Field Name

Bit

Access

Description

Reserve

31:8

RO

Reserve


ADDR VLD


7


RO


Address valid flag
Default:0x0

DEV ADDR

6:0

RO

Device address
Default:0x0


18.4 Endpoint0 Setup Data Port (UDEP0SDP)
Address: 0x9C102910
Reset: 0x0000 0000  


Field Name

Bit

Access

Description

EP0 Setup Data31:0RO8 bytes setup packet data port
Default:0x0


18.5 Endpoint0 Control Status (UDEP0CS)
Address: 0x9C102914
Reset: 0x0000 0001


Field Name

Bit

Access

Description

Reserve31:6ROReserve
EP0 OUT EMPTY5ROWhen EP0 OUT VLD is 1
0: CTRL OUT packet is not an zero length packet(default)
1: CTRL OUT packet is a zero length packet this port must check EP0 DOUT VLD first
EP0 OVLD4ROEP0 OUT Buffer Valid Flag Status
0: No data in EP0 DATA FIFO(default)
1: A Valid data in EP0 DATA FIFO CLR
EP0 OUT VLD3W1CWrite 1 to clear EP0 DOUT VLD
EP0 IVLD2ROEP0 IN Buffer Valid Flag Status
0:Data in EP0 DATA FIFO had been received by
Host(default)
1: Data in EP0 DATA FIFO is still Valid and has not been read by host
SET EP0 IN VLD1OtherWrite 1 to set EP0 DIN VLD when data in FIFO is valid
EP0 DIR0RWwhen direction is changed, the EP0 FIFO address pointer will auto reset to 0
0: CTRL OUT;
1: CTRL IN(default)



18.6 Endpoint0 Data Count (UDEP0DC)
Address: 0x9C102918
Reset: 0x0000 0000  


Field Name

Bit

Access

Description

Reserve31:7ROReserve
EP0 DATA CNTR

6:0

RW

EP0 Data Counter

Write can direct move the address pointer Read during OUT = valid byte count Read

during IN after IN VLD = valid byte count Read during IN before IN VLD = write pointer address 

What does it mean ?

Default:0x0



18.7 Endpoint0 Data Port (UDEP0DP)
Address: 0x9C10291C

Reset: 0x0000 0000  


Field Name

Bit

Access

Description

EP0 DATA PORT31:0RW64 bytes EP0 data port
co-work with 0x120 when write or read
Default:0x0



18.8 Endpoint0 data port vld byte (UDEP0VB)
Address:0x9C102920
Reset:0x0000 0000  


Field Name

Bit

Access

Description

UDEP0VB3:0RWUSB device endpoint0 data port vld byte co-work with
0x11C when write and read
Default:0x0



18.9 Endpoint0 OUT NAK Count (UDEP0ONAKCN)
Address: 0x9C102924
Reset: 0x0000 0000  


Field Name

Bit

Access

Description

Reserve31:8ROReserve
EP0 OUT NAK CNT

7:0

Other

Write to set IRQ threshold point and clear the counter at the same time

set 0 -> limit is 1; set n -> limit is n*64

Read to get high portion of counter[13:6] NAK counter is 14bits



18.10 Endpoint0 IN NAK Count (UDEP0INAKCN)
Address: 0x9C102928
Reset: 0x0000 0000  


Field Name

Bit

Access

Description

Reserve31:8ROReserve
EP0 IN NAK CNT7:0OtherWrite to set IRQ threshold point and clear the counter at the same time
set 0 -> limit is 1; set n -> limit is n*64
Read to get high portion of counter[13:6] NAK counter is
14bits



18.12 Mass Storage Tag Copy (UDCMSTC)
Address: 0x9C102930
Reset: 0x0000 0000   


Field Name

Bit

Access

Description

Reserve31:8
Reserve
CP CBW TAG7:0OtherWrite any value will copy current FIFO byte4 byte7 to
EP1S FIFO byte0 byte3
when read this register, the return value is always 0



18.13 Endpoint1/2 Control (UDEP12C)
Address: 0x9C102934
Reset: 0x0000 0000   


Field Name

Bit

Access

Description

Reserve31:5ROReserve
SET EP1 IVLD4OtherSet Current EP1 IN Buffer Valid Flag
CLR EP2 OVLD3OtherClear Current EP2 OUT Buffer Valid Flag
RESET PIPO FIFO2OtherWrite 1 to Reset Current and Next EP1/2 FIFO
EP12 ENA1RW0: disable bulk in and bulk out(default);
1: enable bulk in and bulk out
EP12 DIR0RW0: BULK OUT(default);
1: BULK IN



18.14 Endpoint1/2 Ping-Pong FIFO Control (UDEP12PPC)
Address: 0x9C102938
Reset: 0x0000 0001


Field Name

Bit

Access

Description

Reserve31:3ROReserve
Current Buff2RO

Full Name ?

1: Buffer0 (PING) buffer is controllable for CPU/DMA;
0: Buffer1 (PONG) buffer is controllable for CPU/DMA

Switch Buffer1OtherWrite 1 to switch Buffer0/Buff1
Auto Switch En0RW

Full name ?

0: ping pong will NOT auto switch;
1: ping pong will auto switch(default)



18.15 Endpoint1/2 FIFO Status (UDEP12FS)
Address: 0x9C10293C

Reset: 0x0000 0000   


Field NameBitAccessDescription

Field Name

Bit

Access

Description

Reserve31:8ROReserve

N MSDC CMD

7

RO

Data in Next Buffer match the MSDC Command format

0: Not match MSDC CMD pattern(default)
1: Match MSDC CMD pattern

A FIFO EMPTY

6

RO

Another Buffer (CPU can't access now) Status
0: Not Empty(default)
1: Empty

A EP2 OVLD

5

RO

Another EP2 OUT Buffer Valid Flag Status
Which buffer is the another buffer depends on 0x334[2]
0x334[2]=1 -> Pong buffer
0x334[2]=0 -> Ping buffer

A EP1 IVLD

4

RO

Another EP1 IN Buffer Valid Flag Status
Which buffer is the another buffer depends on 0x334[2]
0x334[2]=1 -> Pong buffer
0x334[2]=0 -> Ping buffer

MSDC CMD VLD

3

RO

Data in Current EP2 Out Buffer (CPU can access now)
match the MSDC Command format
0: Not match MSDC CMD pattern(default)
1: Match MSDC CMD pattern

FIFO EMPTY

2

RO

Data in Current Buffer (CPU can access now) Status
0: Not Empty(default)
1: Empty

EP2 OVLD

1

RO

Current EP2 OUT Buffer Valid Flag Status Which buffer is the cur vld buffer depends on 0x334[2]
0x334[2]=1 -> Ping buffer
0x334[2]=0 -> Pong buffer

EP1 IVLD

0

RU

Current EP1 IN Buffer Valid Flag Status Which buffer is the cur buffer depends on 0x334[2]
0x334[2]=1 -> Ping buffer
0x334[2]=0 -> Pong buffer



18.16 Endpoint1/2 PING FIFO Data Count (UDEP12PIC)
Address:0x9C102940
Reset: 0x0000 0000   


Field Name

Bit

Access

Description

Reserve31:13ROReserve

RESET EP12 PING CNTR

12

Other

write 1: BULK OUT=move r ptr to 0; BULK IN=move w ptr to 0

Reserve

11:10

RO

Reserve

EP12 PING CNTRL

9:0

Other

Write : modify read or write pointer; Read : BULK OUT
= valid byte count BULK IN before SET IN VLD= write pointer BULK IN after SET IN VLD= valid byte count NOTE: But mostly when EP1 IVLD is set or EP2 OVLD is clear, another IN-UnValid or Out-Valid buffer will be switch to CPU domain. So After EP1 IVLD is set or EP2 OVLD is clear, you have to make sure the result be- long to what you want to know



18.17 Endpoint1/2 PONG FIFO Data Count (UDEP12POC)
Address: 0x9C102944
Reset: 0x0000 0000   


Field Name

Bit

Access

Description

Reserve31:13ROReserve
RESET EP12 PONG CNTR12Otherwrite 1: BULK OUT=move r ptr to 0; BULK IN=move w ptr to 0
Reserve11:10ROReserve
EP12 PONG CNTRL9:0OtherWrite: modify read or write pointer; Read:
BULK OUT = valid byte count
BULK IN before SET IN VLD= write pointer
BULK IN after SET IN VLD= valid byte count



18.18 Endpoint1/2 FIFO Data Port (UDEP12FDP)
Address: 0x9C102948
Reset: 0x0000 0000   


Field Name

Bit

Access

Description

EP12 DATA PORT31:0OtherRead/write data from/to ping or pong buffer according to UDEP12PPC[2]
co-work with 0x14C when write and read
For more detail,refer to NOTE



18.19 Endpoint1/2 FIFO Data Port vld byte (UDEP12VB)
Address: 0x9C10294C

Reset: 0x0000 0000   


Field Name

Bit

Access

Description

Reserve31:4ROReserve
UDEP12VB3:0RORead/write data from/to ping or pong buffer according to UDEP12PPC[2]
co-work with 0x148 when write and read
For more detail,refer to NOTE



18.20 Endpoint1 Special Control Status (UDEP1SCS)
Address: 0x9C102950
Reset: 0x0000 0000   


Field Name

Bit

Access

Description

Reserve31:10ROReserve
EP1S EN9RWEP1S enable
0: Disable(default)
1:Enable
EP1S FIFO PRI8RWEP1S fifo priority
0: EP1S FIFO < EP1 FIFO(default);
1: EP1S FIFO > EP1 FIFO
EP1S FIFO CNTR7:4RWWrite a value 0 8 to direct point the write pointer of EP1S DATA FIFO to a specific position; Read will read back current pointing address
Default:0x0
CLR EP1S IN VALID3OtherWrite 1 to clear EP1S IN VLD

RESET EP1S FIFO

2

Other

Write 1 to reset the EP1S write pointer


EP1S IN VALID


1


RO


EP1 Special IN Buffer Valid Flag Status
0:Data in EP1S DATA FIFO had been received by
Host(default)
1: Data in EP1S DATA FIFO is still Valid and has not been read by host

SET EP1S IN VALID

0

Other

Write 1 to set when EP1S DATA FIFO valid to IN



18.21 Endpoint1 Special Data Port (UDEP1SDP)

Address: 0x9C102954

Reset: 0x0000 0000  



Field Name

Bit

Access

Description

Reserve31:8ROReserve

EP1S DATA PORT

7:0

Other

9 bytes EP1S data port



18.22 Endpoint1 IN NAK Count (UDEP1INAKCN)
Address: 0x9C102958
Reset: 0x0000 0000   


Field Name

Bit

Access

Description

Reserve31:8ROReserve
EP1 NAK CNT7:0OtherWrite to set IRQ threshold point and clear the counter at the same time (set 0->limit is 1,set n -> limit is *n*64); Read* to get high portion of counter[13:6]
NAK counter is 14bits

 

18.23 Endpoint2 OUT NAK Count (UDEP2ONAKCN)
Address: 0x9C10295C

Reset: 0x0000 0000  

Field Name

Bit

Access

Description

Reserve

31:8

RO

Reserve


EP2 NAK CNT


7:0


Other


Write to set IRQ threshold point and clear the counter at the same time (set 0->limit is 1,set n -> limit is *n*64) Read* to get high portion of counter[13:6]
NAK counter is 14bits



18.24 Endpoint3 FIFO Data Port vld byte (UDEP3VB)

Address: 0x9C102960

Reset: 0x0000 0000  


Field Name

Bit

Access

Description

Reserve

31:4

RO

Reserve


UDEP3VB


3:0


Other


USB Device Endpoint3 FIFO Data Port vld byte
co-work with 0x16C when write and read



18.25 USB Device Endpoint3 control (UDEP3CTRL)

Address: 0x9C102964 

Reset: 0x0000 0001


Field Name

Bit

Access

Description

Reserve

31:4

RO

Reserve


EP3 VLD


3


W1C


EP3 valid bit


Reserve


2:1


RO


Reserve


EP3 DIR


0


RW


EP3 enable bit
Default:1


18.26 Endpoint3 FIFO write pointer (UDEP3PTR)

Address: 0x9C102968

Reset: 0x0000 0000  



Field Name

Bit

Access

Description

Reserve31:8ROReserve

UDEP3PTR

7:0

 Other

USB device endpoint3 FIFO write pointer



18.27 Endpoint3 FIFO Data Port (UDEP3DATA)
Address: 0x9C10296C

Reset: 0x0000 0000   


Field Name

Bit

Access

Description

UDEP3DATA31:0ROUSB Device Endpoint3 FIFO Data Port



18.28 USB Device Endpoint4 control (UDEP4CTRL)

Address: 0x9C102970 

Reset: 0x0000 0001


Field Name

Bit

Access

Description

Reserve

31:4

RO

Reserve


EP4 VLD


3


RU


EP4 valid bit


Reserve


2:1


RO


Reserve


EP4 DIR


0


RW


EP4 enable bit
Default:1


18.29 Endpoint4 FIFO write pointer (UDEP4PTR)

Address: 0x9C102974

Reset: 0x0000 0000  



Field Name

Bit

Access

Description

Reserve31:8ROReserve

UDEP4PTR

7:0

 Other

USB device endpoint4 FIFO write pointer



18.30 Endpoint4 FIFO Data Port (UDEP4DATA)
Address:0x9C102978
Reset: 0x0000 0000   


Field Name

Bit

Access

Description

UDEP4DATA31:0RWUSB Device Endpoint4 FIFO Data Port



18.31 Endpoint4 data port vld byte (UDEP4VB)
Address: 0x9C10297C

Reset: 0x0000 0000  


Field Name

Bit

Access

Description

UDEP4VB31:0
USB device endpoint4 data port vld byte co-work with
0x178 when write and read
Default:0x0




Group 19 USB Device: EP5/6/7 Control


19.0 Endpoint5 control (UDEP5CTRL)
Address: 0x9C102980
Reset: 0x0000 0000  

Field Name

Bit

Access

Description

Reserve

31:3

RO

Reserve

UDEP5FLUSH

2

RW

USB Device Endpoint5 FIFO flush bit
can not self clean, write 0 to pull this bit down
Default:0

UDEP5HDEN

1

RW

Header packet enable bit
Default:0

UDEP5EN

0

RW

ep5 enable bit
Default:0



19.1 Endpoint5 video class header data length (UDEP5HDLEN)

Address: 0x9C102984

Reset: 0x0000 0000 


Field Name

Bit

Access

Description

Reserve

31:8

RO

Reserve

UDEP5HDLEN

7:0

RW

Header data length
Default:0



19.2 Endpoint5 video class frame control (UDEP5FRAME)
Address: 0x9C102988
Reset: 0x0000 0080


Field Name

Bit

Access

Description

Reserve31:8ROReserve
EP5CTRLEMPTY7ROEP5 buffer empty
when head en=1, head cnt=0 and data buffer empty=1, this bit can be 1
when head en=0, data buffer empty=1, this bit can be 1
Default:1
EP5CTRLFULL6ROEP5 buffer full
not include hear cnt
Default:0

Reserve

5:3

RO

Reserve

UDEP5ENDFR

2:1

Other

Header data end frame control

UDEP5FRAMEID

0

Other

Header data frame ID, write 1 toggle



19.3 Endpoint5 video class header data control (UDEP5HDCTRL)

Address: 0x9C10298C

Reset: 0x0000 0000


Field Name

Bit

Access

Description

Reserve

31:5

RO

Reserve

UDEP5ERROR

4

W1C

Header data error flag

UDEP5FRAMEND

3

RW

Header data end flag
Default:0

UDEP5FRAMESTILL

2

RW

Header data still image flag
Default:0

UDEP5FRAMESRC

1

RW

Header data SCR flag
Default:0

UDEP5FRAMEPT

0

RW

Header data prime time
Default:0



19.4 Endpoint5 FIFO read pointer (UDEP5RPT)
Address: 0x9C102990
Reset: 0x0000 0000 


Field Name

Bit

Access

Description

Reserve31:13ROReserve
UDEP5RPT12:0ROUSB device endpoint5 FIFO read pointer



19.5  Endpoint5 FIFO write pointer (UDEP5WPT)
Address: 0x9C102994
Reset: 0x0000 0000 

Field Name

Bit

Access

Description

Reserve31:13ROReserve

UDEP5WPT

12:0

 Other

USB device endpoint5 FIFO write pointer



19.6 Endpoint5 FIFO data port (UDEP5DATA)
Address: 0x9C102998
Reset: 0x0000 0000 


Field Name

Bit

Access

Description

UDEP5DATA31:0ROUSB device endpoint5 FIFO data port co-work with
0x1A4 when write or read For more detail, refer to NOTE
Default:0x0




19.7 SOF recovery enable (UDSRE)
Address: 0x9C10299C

Reset: 0x0000 0000 


Field Name

Bit

Access

Description

Reserve31:1ROReserve
UDSRE0RWUSB device sof recovery enable
0: bypass sof org(default)
1: sof recovery enable



19.8 Frame time (UDFT)
Address: 0x9C1029A0
Reset: 0x0000 0EA6

Field Name

Bit

Access

Description

Reserve31:16ROReserve
UDFT15:0RWUSB device frame time
default value for phyclk 30Mand deviceHS
125us/33/33ns = 0xEA6



19.9 Endpoint5 data port vld byte (UDEP5VB)
Address: 0x9C1029A4
Reset: 0x0000 0000 


Field Name

Bit

Access

Description

Reserve31:4ROReserve
UDEP5VB3:0RWUSB device endpoint5 data port vld byte co-work with
0x198 when write or read
Default:0x0



19.10 Video class reference clock divisor (UDSTCDIV)
Address: 0x9C1029A8
Reset: 0x0000 001D


Field Name

Bit

Access

Description

Reserve31:16ROReserve
UDSTCDIV15:0RWUSB device video class reference clock divisor
Default:0x1d




19.16 Endpoint6 control (UDEP6CTRL)
Address: 0x9C1029C0
Reset: 0x0000 0001


Field Name

Bit

Access

Description

Reserve 

31:4

RO 

Reserve

EP6 VLD3ROEP6 valid bit
Reserve2:1ROReserve

EP6 DIR

0

RW

EP6 enable bit

Description ?

Default:1



19.17 Endpoint6 FIFO write pointer (UDEP6PTR)
Address: 0x9C1029C4 

Reset: 0x0000 0000


Field Name

Bit

Access

Description

Reserve

31:8

RO

Reserve

UDEP6PTR

7:0

Other

USB device endpoint6 FIFO write pointer


19.18 Endpoint6 FIFO Data Port (UDEP6DATA)
Address: 0x9C1029C8
Reset: 0x0000 0000 


Field Name

Bit

Access

Description

UDEP6DATA31:0RWUSB Device Endpoint6 FIFO Data Port



19.19 Endpoint6 data port vld byte (UDEP6VB)
Address: 0x9C1029CC

Reset: 0x0000 0000


Field Name

Bit

Access

Description

UDEP6VB3:0RWUSB device endpoint6 data port vld byte co-work with
0x1C8 when write and read
Default:0x0



19.24 Endpoint7 control (UDEP7CTRL)
Address:  0x9C1029E0
Reset: 0x0000 0001


Field Name

Bit

Access

Description

Reserve31:8ROReserve
EP7BUF FLUSH7RWEP7 buffer flush
can not self clean, write 0 to pull this bit down
Default:0
Reserve6:4ROReserve
EP7 VLD3RWEP7 valid bit
Default:0
Reserve2:1ROReserve
EP7 DIR0RWEP7 enable bit
Default:1



19.25 Endpoint7 FIFO read pointer (UDEP7RPTR)

Address: 0x9C1029E4

Reset: 0x0000 0000


Field Name

Bit

Access

Description

Reserve31:9ROReserve

UDEP7RPTR

8:0

RO

USB device endpoint7 FIFO read pointer



19.26 Endpoint7 FIFO write pointer (UDEP7WPTR)
Address: 0x9C1029E8
Reset: 0x0000 0000 


Field Name

Bit

Access

Description

Reserve31:9ROReserve
UDEP7WPTR8:0OtherUSB device endpoint7 FIFO write pointer



19.27 Endpoint7 FIFO Data Port (UDEP7DATA)
Address: 0x9C1029EC

Reset: 0x0000 0000


Field Name

Bit

Access

Description

UDEP7DATA31:0ROUSB Device Endpoint7 FIFO Data Port



19.28 Endpoint7 data port vld byte (UDEP7VB)
Address: 0x9C1029F0
Reset: 0x0000 0000


Field Name

Bit

Access

Description

UDEP7VB3:0RWUSB device endpoint7 data port vld byte co-work with
0x1EC when write and read
Default:0x0




Group 20 USB Device: EP8/9/A/B Control

20.0 Endpoint8/9 Control (UDEP89C)
Address: 0x9C102A00
Reset: 0x0000 0000 


Field Name

Bit

Access

Description

Reserve31:5ROReserve
SET EP8 IVLD4OtherSet Current EP8 IN Buffer Valid Flag
CLR EP9 OVLD3OtherClear Current EP9 OUT Buffer Valid Flag
EP89 RESET PIPO FIFO2OtherWrite 1 to Reset Current and Next EP8/9 FIFO
EP89 ENA1RW0: disable bulk in and bulk out(default)
1: enable bulk in and bulk out
EP89 DIR0RW0: BULK OUT(default);
1: BULK IN



20.1 Endpoint8/9 Ping Pong FIFO Control (UDEP89PPC)
Address: 0x9C102A04
Reset: 0x0000 0001


Field Name

Bit

Access

Description

Reserve31:3ROReserve
EP89 Current Buff2RO1: Buffer0 (PING) buffer is controllable for CPU/DMA;
0:Buffer1(PONG)buffer iscontrollable for
CPU/DMA(defualt)
EP89 Switch Buffer1OtherWrite 1 to switch Buffer0/Buff1
EP89 Auto Switch En0Other0: ping pong will NOT auto switch;
1: ping pong will auto switch(default)



20.2 Endpoint8/9 FIFO Status (UDEP89FS)

Address: 0x9C102A08
Reset: 0x0000 0000


Field Name

Bit

Access

Description

Reserve

31:7

RO

Reserve

EP89 A FIFO EMPTY

6

RO

Another Buffer (CPU can't access now) Status
0: Not Empty(default)
1: Empty

A EP9 OVLD

5

RO

Another EP9 OUT Buffer Valid Flag Status
Which buffer is the another buffer depends on 0x504[2]
0x504[2]=1 -> Pong buffer
0x504[2]=0 -> Ping buffer

A EP8 IVLD

4

RO

Another EP8 IN Buffer Valid Flag Status
Which buffer is the another buffer depends on 0x504[2]
0x504[2]=1 -> Pong buffer
0x504[2]=0 -> Ping buffer

Reserve

3

RO

Reserve

EP89 FIFO EMPTY

2

RO

Data in Current Buffer (CPU can access now) Status 0 = Not Empty 1 = Empty
Which buffer is the another buffer depends on 0x504[2]
0x504[2]=1 -> Pong buffer
0x504[2]=0 -> Ping buffer

EP9 OVLD 0

1

RO

Current EP9 OUT Buffer Valid Flag Status
Which buffer is the another buffer depends on 0x504[2]
0x504[2]=1 -> Pong buffer
0x504[2]=0 -> Ping buffer

EP8 IVLD 0

0

RU

Current EP8 IN Buffer Valid Flag Status
Which buffer is the another buffer depends on 0x504[2]
0x504[2]=1 -> Pong buffer
0x504[2]=0 -> Ping buffer




20.3 Endpoint8/9 PING FIFO Data Count (UDEP89PIC)
Address: 0x9C102A0C

Reset: 0x0000 0000 


Field Name

Bit

Access

Description

Reserve31:13ROReserve
Reset EP89 PING CNTR12RUwrite 1: BULK OUT=move r ptr to 0; BULK IN=move w ptr to 0
Reserve11:10ROReserve
EP89 PING CNTR9:0RUWrite: modify read or write pointer; Read: BULK OUT
= valid byte count BULK IN before SET IN VLD= write pointer BULK IN after SET IN VLD= valid byte count



20.4 Endpoint8/9 PONG FIFO Data Count (UDEP89POC)
Address: 0x9C102A10
Reset: 0x0000 0000 


Field Name

Bit

Access

Description

Reserve31:13ROReserve
Reset EP89 PONG CNTR12RUwrite 1: BULK OUT=move r ptr to 0; BULK IN=move w ptr to 0
Reserve11:10ROReserve
EP89 PONG CNTRL9:0RUWrite: modify read or write pointer; Read : BULK OUT
= valid byte count; BULK IN before SET IN VLD= write pointer; BULK IN after SET IN VLD= valid byte count



20.5 Endpoint8/9 FIFO Data Port (UDEP89FDP)
Address: 0x9C102A14
Reset: 0x0000 0000 


Field Name

Bit

Access

Description

EP89 DATA PORT

31:0

RU

Read/write data from/to ping or pong buffer according to 0x504[2]

co-work with 0x218 when write and read For more detail, refer to NOTE



20.6 Endpoint8/9 FIFO Data Port vld byte (UDEP89VB)
Address: 0x9C102A18
Reset: 0x0000 0000 


Field Name

Bit

Access

Description

Reserve31:4ROReserve
UDEP89VB

3:0

RW

Read/write data from/to ping or pong buffer according to 0x504[2]

co-work with 0x214 when write and read For more detail, refer to NOTE Default:0x0



20.7 Endpoint8 IN NAK Count (UDEP8INAKCN)
Address: 0x9C102A1C

Reset: 0x0000 0000 


Field Name

Bit

Access

Description

Reserve31:8ROReserve
EP8 NAK CNT7:0Other

Write to set IRQ threshold point and clear the counter at the same time (set 0->limit is 1, set n -> limit is *n*64);

Read* to get high portion of counter[13:6]
NAK counter is 14bits



20.8 Endpoint9 OUT NAK Count (UDEP9ONAKCN)
Address: 0x9C102A20
Reset: 0x0000 0000 


Field Name

Bit

Access

Description

Reserve31:8ROReserve
EP9 NAK CNT7:0OtherWrite to set IRQ threshold point and clear the counter at the same time (set 0->limit is 1, set n -> limit is *n*64); Read* to get high portion of counter[13:6]
NAK counter is 14bits



20.9 Endpoint89 setting (UDEP89S)
Address: 0x9C102A24
Reset: 0x0000 0000 


Field Name

Bit

Access

Description

Reserve 92

31:8

RO

Reserve

EP89ALT SET

7:4

RW

EP89 alternate setting
Default:0x0

EP89INTF SET

3:0

RW

EP89 interface number
Default:0x0



20.16 Endpoint10/11 Control (UDEPABC)
Address: 0x9C102A40
Reset: 0x0000 0000 


Field Name

Bit

Access

Description

Reserve31:5ROReserve
SET EP10 IVLD4OtherSet Current EP10 IN Buffer Valid Flag
CLR EP11 OVLD3OtherClear Current EP11 OUT Buffer Valid Flag
EPAB RESET PIPO FIFO2OtherWrite 1 to Reset Current and Next EP8/9 FIFO
EPAB ENA1RW0: disable bulk in and bulk out(default);
1: enable bulk in and bulk out 
EPAB DIR0RW0: BULK OUT(default);
1: BULK IN



20.17 Endpoint10/11 Ping-Pong FIFO Control (UDEPABPPC)
Address: 0x9C102A44
Reset: 0x0000 0001


Field Name

Bit

Access

Description

Reserve31:4ROReserve
EPAB DIR R3RO0: BULK OUT(default);
1: BULK IN
EPAB Current Buff2RO1: Buffer0 (PING) buffer is controllable for CPU/DMA;
0:Buffer1(PONG)buffer iscontrollable for
CPU/DMA(default)
EPAB Switch Buffer1OtherWrite 1 to switch Buffer0/Buff1
EPAB Auto Switch En0Other0: ping pong will NOT auto switch;
1: ping pong will auto switch(default)



20.18 Endpoint10/11 FIFO Status (UDEPABFS)

Address: 0x9C102A48
Reset: 0x0000 0000


Field Name

Bit

Access

Description

Reserve

31:7

RO

Reserve

EPAB A FIFO EMPTY

6

RO

Another Buffer (CPU can't access now) Status
0: Not Empty(default)
1: Empty

A EPB OVLD

5

RO

Another EP11 OUT Buffer Valid Flag Status
Which buffer is the another buffer depends on 0x554[2]
0x554[2]=1 -> Pong buffer
0x554[2]=0 -> Ping buffer

A EPA IVLD

4

RO

Another EP10 IN Buffer Valid Flag Status
Which buffer is the another buffer depends on 0x554[2]
0x554[2]=1 -> Pong buffer
0x554[2]=0 -> Ping buffer

Reserve

3

RO

Reserve

EPAB FIFO EMPTY

2

RO

Data in Current Buffer (CPU can access now) Status
0: Not Empty(default)
1: Empty

EPB OVLD

1

RO

Current EP11 OUT Buffer Valid Flag Status
Which buffer is the another buffer depends on 0x554[2]
0x554[2]=1 -> Pong buffer
0x554[2]=0 -> Ping buffer

EPA IVLD

0

RU

Current EP10 IN Buffer Valid Flag Status
Which buffer is the another buffer depends on 0x554[2]
0x554[2]=1 -> Pong buffer
0x554[2]=0 -> Ping buffer


20.19 Endpoint10/11 PING FIFO Data Count (UDEPABPIC)
Address: 0x9C102A4C

Reset: 0x0000 0000 


Field Name

Bit

Access

Description

Reserve31:13ROReserve
Reset EPAB PING CNTR12RUwrite 1: BULK OUT=move r ptr to 0; BULK IN=move w ptr to 0
Reserve11:10ROReserve
EPAB PING CNTRL9:0RUWrite : modify read or write pointer; Read : BULK OUT
= valid byte count; BULK IN before SET IN VLD= write pointer; BULK IN after SET IN VLD= valid byte count



20.20 Endpoint10/11 PONG FIFO Data Count (UDEPABPOC)
Address: 0x9C102A50
Reset: 0x0000 0000 


Field Name

Bit

Access

Description

Reserve31:13ROReserve
Reset EPAB PONG CNTR12RUwrite 1: BULK OUT=move r ptr to 0; BULK IN=move w ptr to 0
Reserve11:10ROReserve
EPAB PONG CNTRL9:0RUWrite : modify read or write pointer; Read : BULK OUT
= valid byte count; BULK IN before SET IN VLD= write pointer; BULK IN after SET IN VLD= valid byte count



20.21 Endpoint10/11 FIFO Data Port (UDEPABFDP)
Address: 0x9C102A54
Reset: 0x0000 0000 


Field NameBitAccessDescription

Field Name

Bit

Access

Description

EPAB DATA PORT

31:0

RU

Read/write data from/to ping or pong buffer according to 0x554[2]

co-work with 0x258 when write and read For more detail, refer to NOTE



20.22 Endpoint10/11 FIFO Data Port vld byte (UDEPABVB)
Address: 0x9C102A58
Reset: 0x0000 0000


Field Name

Bit

Access

Description

Reserve31:4ROReserve
UDEPABVB3:0RWRead/write data from/to ping or pong buffer according to 0x554[2]
co-work with 0x254 when write and read
For more detail, refer to NOTE Default:0x0



20.23 Endpoint10 IN NAK Count (UDEPAINAKCN)
Address: 0x9C102A5C

Reset: 0x0000 0000


Field Name

Bit

Access

Description

Reserve31:8ROReserve
EPA NAK CNT

7:0

Other

Write to set IRQ threshold point and clear the counter

at the same time (set 0->limit is 1, set n -> limit is *n*64);*

Read to get high portion of counter[13:6]

NAK counter is 14bits



20.24 Endpoint11 OUT NAK Count (UDEPBONAKCN)
Address: 0x9C102A60
Reset: 0x0000 0000 


Field Name

Bit

Access

Description

Reserve31:8ROReserve
EPB NAK CNT7:0Other

Write to set IRQ threshold point and clear the counter at the same time (set 0->limit is 1, set n -> limit is *n*64);

Read* to get high portion of counter[13:6]
NAK counter is 14bits



20.25 EndpointAB setting (UDEPABS)

Address: 0x9C102A64 

Reset: 0x0000 0000


Field Name

Bit

Access

Description

Reserve

31:8

RO

Reserve

EPABALT SET

7:4

RW

EPAB alternate setting
Default:0x0

EPABINTF SET

3:0

RW

EPAB interface number
Default:0x0



Group 21 USB Device: EPC/D Control

21.0 EPC control (UDEPCCTRL)
Address: 0x9C102A80
Reset: 0x0000 0008

Field Name

Bit

Access

Description

Reserve

31:4

RO

Reserve

UDEPCEMPTY

3

RO

EPC buffer empty
Default:1

UDEPCFULL

2

RO

EPC buffer full
Default:0

UDEPCFLUSH

1

RW

USB Device EPC FIFO flush bit
can not self clean, write 0 to pull this bit down
Default:0

UDEPCEN

0

RW

EPC enable bit
Default:0



21.1 EPC FIFO read pointer (UDEPCRPT)
Address: 0x9C102A84
Reset: 0x0000 0000


Field Name

Bit

Access

Description

Reserve31:13ROReserve
UDEPCRPT12:0RWUSB device EPC FIFO read pointer
Default:0x0



21.2 EPC FIFO write pointer (UDEPCWPT)
Address: 0x9C102A88
Reset: 0x0000 0000 

Field Name

Bit

Access

Description

Reserve31:13ROReserve

UDEPCWPT

12:0

12:0 Other

USB device EPC FIFO write pointer


21.3 EPC FIFO data port (UDEPCDATA)
Address: 0x9C102A8C

Reset: 0x0000 0000 

Field Name

Bit

Access

Description

UDEPCDATA

31:0

RU

USB device EPC FIFO data



21.4 EPC setting (UDEPCS)

Address: 0x9C102A90

Reset: 0x0000 0000


Field Name

Bit

Access

Description

Reserve

31:8

RO

Reserve

EPCALT SET

7:4

RW

EPC alternate setting
Default:0x0

EPCINTF SET

3:0

RW

EPC interface number
Default:0x0



21.5 EPC buffer data cnt (UDEPCBDC)
Address: 0x9C102A94
Reset: 0x0000 0000 


Field Name

Bit

Access

Description

Reserve31:12ROReserve
EPCINTF SET11:0ROEPC buffer data cnt
Default:0x0



21.6 EPD Control register (UDEPDCTRL)
Address: 0x9C102A98
Reset: 0x0000 0000



Field Name

Bit

Access

Description

Reserve

31:1

RO

Reserved

EN

0

RW

Enable
enable endpoint 13
Default:0x0



21.7 EPD Status register (UDEPDST)
Address: 0x9C102A9C

Reset: 0x0000 0000


Field Name

Bit

Access

Description

Reserve31:9ROReserved
UDEPD FAIL8RWEP13 out transfer failed
When SW write to this register, all bits will be cleared, in- cluding transfer failed, buffer overflow and buffer counter Default:0
UDEPD OVER7RWEP13 buffer overflow
Indicates the output data is larger than MPS Default:0
UDEPD CNT6:0RWEP13 buffer counter
This indicates the data bytes received from host
Default:0



21.8 EPD FIFO data port (UDEPDDATA)
Address: 0x9C102AA0
Reset: 0x0000 0000 


Field Name

Bit

Access

Description

UDEPDDATA31:0RUUSB device EPD FIFO data



Group 22 USB Device: Phyclk Domain Interrupt

22.0 Linker Layer Interrupt flag (UDCLIF)
Address: 0x9C102B00
Reset: 0x0000 0000 



Field Name

Bit

Access

Description

UDLC EPC SUCC IF31W1CUDLC EPC OUT success interrupt flag
UDLC EPC FAIL IF30W1CUDLC EPC OUT fail interrupt flag
UDLC EPC OFLOW IF29W1CUDLC EPC data overflow interrupt flag
UDLC EP6 FAIL IF27W1CUDLC EP6 IN fail interrupt flag
UDLC EP3 FAIL IF26W1CUDLC EP3 IN fail interrupt flag
UDLC EP7 DMA IF25W1CUDLC EP7 DMA IN data finish interrupt flag
UDLC EP5 DMA IF24W1CUDLC EP5 DMA IN data finish interrupt flag
UDLC EP7I IF23W1CUDLC EP7 IN Transaction Interrupt flag
UDLC EP6I IF22W1CUDLC EP6 IN Transaction Interrupt flag
UDLC EP5I IF21W1CUDLC EP5 IN Transaction Interrupt flag
UDLC EP4I IF20W1CUDLC EP4 IN Transaction Interrupt flag
UDLC URES IF19W1CUDLC USB RESET release Interrupt flag
UDLC EP4 FAIL IF18W1CUDLC EP4 IN fail interrupt flag
UDLC RESU IF17W1CUDLC resume interrupt flag
UDLC SUS IF16W1CUDLC suspend interrupt flag
UDLC EP1 DMA IF15W1CUDLC EP12 DMA IN data finish interrupt flag
UDLC EP3I IF14W1CUDLC EP3 IN Transaction Interrupt Flag

UDLC PIPO IF

13

W1C

UDLC EP12 PING-PONG FIFO SWAP Interrupt Flag

UDLC TEST IF

12

W1C

UDLC USB SET TEST MODE interrupt flag

UDLC EP2N IF

11

W1C

UDLC EP2 NAK Interrupt Flag

UDLC EP1N IF

10

W1C

UDLC EP1 NAK Interrupt Flag

UDLC EP0N IF

9

W1C

UDLC EP0 NAK Interrupt Flag

UDLC ADDR IF

8

W1C

UDCL USB SET ADDR interrupt flag

UDLC EP2O IF

7

W1C

UDLC EP2 OUT Transaction Interrupt Flag

UDLC EP1I IF

6

W1C

UDLC EP1 IN Transaction Interrupt Flag

UDLC EP1SI IF

5

W1C

UDLC EP1S IN Transaction Interrupt Flag

UDLC EP0I IF

4

W1C

UDLC EP0 IN Transaction Interrupt Flag

UDLC EP0O IF

3

W1C

UDLC EP0 OUT Transaction Interrupt Flag

UDLC EP0S IF

2

W1C

UDLC EP0 SETUP Transaction Interrupt Flag

UDLC SUSP IF

1

W1C

UDLC USB SUSPEND DIFF Interrupt Flag

UDLC RESET IF

0

W1C

UDLC USB RESET Interrupt Flag



22.1 Linker Layer Interrupt enable (UDCIE)
Address: 0x9C102B04
Reset: 0x0000 0000 


Field Name

Bit

Access

Description

UDLC EPC SUCC IE31RWUDLC EPC OUT success interrupt enable
0:Disbale(default)
1:Enable
UDLC EPC FAIL IE30RWUDLC EPC OUT fail interrupt enable
0:Disbale(default)
1:Enable

UDLC EPC OFLOW IE

29

RW

UDLC EPC data overflow interrupt enable
0:Disbale(default)
1:Enable

UDLC EPC DERR IE

28

RW

UDLC EPC data error during a uSOF interrupt enable
0:Disbale(default)
1:Enable

UDLC EP6 FAIL IE

27

RW

UDLC EP6 IN fail interrupt enable
0:Disbale(default)
1:Enable

UDLC EP3 FAIL IE

26

RW

UDLC EP3 IN fail interrupt enable
0:Disbale(default)
1:Enable

UDLC EP7 DMA IE

25

RW

UDLC EP7 DMA IN data finish interrupt enable
0:Disbale(default)
1:Enable

UDLC EP5 DMA IE

24

RW

UDLC EP5 DMA IN data finish interrupt enable
0:Disbale(default)
1:Enable

UDLC EP7I IE

23

RW

UDLC EP7 IN Transaction Interrupt Enable
0:Disbale(default)
1:Enable

UDLC EP6I IE

22

RW

UDLC EP6 IN Transaction Interrupt Enable
0:Disbale(default)
1:Enable

UDLC EP5I IE

21

RW

UDLC EP5 IN Transaction Interrupt Enable
0:Disbale(default)
1:Enable

UDLC EP4I IE

20

RW

UDLC EP4 IN Transaction Interrupt Enable
0:Disbale(default)
1:Enable

UDLC URES IE

19

RW

UDLC USB RESET release Interrupt Enable
0:Disbale(default)
1:Enable

UDLC EP4 FAIL IE

18

RW

UDLC EP4 IN fail interrupt enable
0:Disbale(default)
1:Enable

UDLC RESU IE

17

RW

UDLC resume interrupt enable
0:Disbale(default)
1:Enable

UDLC SUS IE

16

RW

UDLC suspend interrupt enable
0:Disbale(default)
1:Enable

UDLC DMA IE

15

RW

UDLC EP12 DMA IN data finish interrupt enable
0:Disbale(default)
1:Enable

UDLC EP3I IE

14

RW

UDLC EP3 IN Transaction Interrupt Enable
0:Disbale(default)
1:Enable

UDLC PIPO IE

13

RW

UDLC EP12 PING-PONG FIFO SWAP Interrupt En- able
0:Disbale(default)
1:Enable

UDLC TEST IE

12

RW

UDLC USB SET TEST MODE interrupt enable
0:Disbale(default)
1:Enable

UDLC EP2N IE

11

RW

UDLC EP2 NAK Interrupt Enable
0:Disbale(default)
1:Enable

UDLC EP1N IE

10

RW

UDLC EP1 NAK Interrupt Enable
0:Disbale(default)
1:Enable

UDLC EP0N IE

9

RW

UDLC EP0 NAK Interrupt Enable
0:Disbale(default)
1:Enable

UDLC ADDR IE

8

RW

UDCL USB SET ADDR interrupt Enable
0:Disbale(default)
1:Enable

UDLC EP2O IE

7

RW

UDLC EP2 OUT Transaction Interrupt Enable
0:Disbale(default)
1:Enable

UDLC EP1I IE

6

RW

UDLC EP1 IN Transaction Interrupt Enable
0:Disbale(default)
1:Enable

UDLC EP1SI IE

5

RW

UDLC EP1S IN Transaction Interrupt Enable
0:Disbale(default)
1:Enable

UDLC EP0I IE

4

RW

UDLC EP0 IN Transaction Interrupt Enable
0:Disbale(default)
1:Enable

UDLC EP0O IE

3

RW

UDLC EP0 OUT Transaction Interrupt Enable
0:Disbale(default)
1:Enable

UDLC EP0S IE

2

RW

UDLC EP0 SETUP Transaction Interrupt Enable
0:Disbale(default)
1:Enable

UDLC SUSP IE

1

RW

UDLC USB SUSPEND DIFF Interrupt Enable
0:Disbale(default)
1:Enable

UDLC RESET IE

0

RW

UDLC USB RESET Interrupt Enable
0:Disbale(default)
1:Enable



22.2 New Bulk EP Interrupt flag (UDNBIF)
Address: 0x9C102B08
Reset: 0x0000 0000 


Field Name

Bit

Access

Description

Reserve31:17ROReserve
UDLC EPDOVLD IF16W1CEP13 Out data valid interrupt flag
Indicates the epd fifo has data for read
UDLC SOF IF15W1CSOF interrupt flag
Indicates the link has receives a SOF packet
UDLC PIPOEPB IF14W1CEP11 PING-PONG FIFO SWAP Interrupt Flag
UDLC PIPOEP9 IF13W1CEP9 PING-PONG FIFO SWAP Interrupt Flag
UDLC PIPOEP2 IF12W1CEP2 PING-PONG FIFO SWAP Interrupt Flag
UDLC EP11O IF11W1CEP11 OUT Transaction Intr Flag
UDLC EP10I IF10W1CEP10 IN Transaction Intr Flag
UDLC EP11N IF9W1CEP11 NAK Interrupt Flag
UDLC EP10N IF8W1CEP10 NAK Interrupt Flag
UDLC PIPOEPAB IF7W1CEP10/11 PING-PONG FIFO SWAP Interrupt Flag

UDLC EPADMA IF

6

W1C

UDLC EP10 DMA IN data finish intr flag

UDLC EP9O IF

5

W1C

EP9 OUT Transaction Interrupt Flag

UDLC EP8I IF

4

W1C

EP8 IN Transaction Interrupt Flag

UDLC EP9N IF

3

W1C

EP9 NAK Interrupt Flag

UDLC EP8N IF

2

W1C

EP8 NAK Interrupt Flag

UDLC EP89PIPO IF

1

W1C

EP89 PING-PONG FIFO SWAP Interrupt Flag

UDLC EP8DMA IF

0

W1C

UDLC EP8 DMA IN data finish inter flag



22.3New Bulk EP Interrupt enable (UDNBIE)
Address: 0x9C102B0C

Reset: 0x0000 0000 



Field Name

Bit

Access

Description

Reserve31:17ROReserve
UDLC EPDOVLD IE16RWEP13 Out data valid interrupt enable
0:Disbale(default)
1:Enable
UDLC SOF IE15RWSOF interrupt enable
0:Disbale(default)
1:Enable
UDLC EPBPIPO IE14RWEP11 PING-PONG FIFO SWAP Interrupt enable
0:Disbale(default)
1:Enable
UDLC EP9PIPO IE13RWEP9 PING-PONG FIFO SWAP Interrupt enable
0:Disbale(default)
1:Enable
UDLC EP2PIPO IE12RWEP2 PING-PONG FIFO SWAP Interrupt enable
0:Disbale(default)
1:Enable
UDLC EP11O IE11RWEP11 OUT Transaction Intr enable
0:Disbale(default)
1:Enable

UDLC EP10I IE

10

RW

EP10 IN Transaction Intr enable
0:Disbale(default)
1:Enable

UDLC EP11N IE

9

RW

EP11 NAK Interrupt enable
0:Disbale(default)
1:Enable

UDLC EP10N IE

8

RW

EP10 NAK Interrupt enable
0:Disbale(default)
1:Enable

UDLC PIPOEPAB IE

7

RW

EP10/11 PING-PONG FIFO SWAP Interrupt enable
0:Disbale(default)
1:Enable

UDLC EPADMA IE

6

RW

UDLC EP10 DMA IN data finish intr enable
0:Disbale(default)
1:Enable

UDLC EP9O IE

5

RW

EP9 OUT Transaction Intr enable
0:Disbale(default)
1:Enable

UDLC EP8I IE

4

RW

EP8 IN Transaction Intr enable
0:Disbale(default)
1:Enable

UDLC EP9N IE

3

RW

EP9 NAK Interrupt enable
0:Disbale(default)
1:Enable

UDLC EP8N IE

2

RW

EP8 NAK Interrupt enable
0:Disbale(default)
1:Enable

UDLC EP89PIPO IE

1

RW

EP89 PING-PONG FIFO SWAP Interrupt enable
0:Disbale(default)
1:Enable

UDLC EP8DMA IE

0

RW

EP8 DMA IN data finish interrupt enable
0:Disbale(default)
1:Enable



22.4 Frame Number (UDFRNUM)
Address: 0x9C102B10
Reset: 0x0000 0000


Field NameBitAccessDescription

Field Name

Bit

Access

Description

SOFCNT

31:16

RO

SOF counter

The received SOF packet after bus reset, will roll over after reach the largest value

Default:0x0

Reserved

15:11

RO

Reserved

FRNUM

10:0

RW

Frame Number

The current frame number from SOF packet, updated
when SOF interrupt
Default:0x0 



22.30 IP Name ( IP Name)
Address: 0x9C102B78
Reset: 0x5332 3232

Field Name

Bit

Access

Description

IP REG Name

31:0

RO

the usb device ip REG Name ->S222
ASCII in this register
Default:0x53323232



22.31 IP Version (VERSION)
Address: 0x9C102B7C

Reset: 0x2015 0818

Field Name

Bit

Access

Description

VERSION

31:0

RO

the date of version
Default:0x20150818



Group 23 USB Device: Bulk Out FIFO Control

23.0 Endpoint2 Ping-Pong FIFO Control (UDEP2PPC)
Address: 0x9C102B80
Reset: 0x0000 0001



Field Name

Bit

Access

Description

Reserve

31:3

RO

Reserved

Current Buff

2

RO

Current Buffer
1: Buffer0 (PING) buffer is controllable for CPU/DMA;
0:Buffer1(PONG)buffer iscontrollable for
CPU/DMA(default)

Switch Buffer

1

Other

Switch Buffer
Write 1 to switch Buffer0/Buff1

Auto Switch En

0

RW

buffer auto switch enable
0: ping pong will NOT auto switch;
1: ping pong will auto switch(default)



23.1 Endpoint2 FIFO Status (UDEP2FS)

Address: 0x9C102B84
Reset: 0x0000 0044


Field Name

Bit

Access

Description

Reserve

31:8

RO

Reserve

N MSDC CMD

7

RO

Data in Next Buffer match the MSDC Command format
0: Not match MSDC CMD pattern(default)
1: Match MSDC CMD pattern

A FIFO EMPTY

6

RO

Another Buffer (CPU can't access now) Status
0: Not Empty
1: Empty(default)

A EP2 OVLD

5

RO

Another EP2 OUT Buffer Valid Flag Status
Which buffer is the another buffer depends on 0x334[2]
0x334[2]=1 -> Pong buffer
0x334[2]=0 -> Ping buffer

A EP1 IVLD

4

RO

Another EP1 IN Buffer Valid Flag Status
Which buffer is the another buffer depends on 0x334[2]
0x334[2]=1 -> Pong buffer
0x334[2]=0 -> Ping buffer

MSDC CMD VLD

3

RO

Data in Current EP2 Out Buffer (CPU can access now)
match the MSDC Command format
0: Not match MSDC CMD pattern(default)
1: Match MSDC CMD pattern

FIFO EMPTY2ROData in Current Buffer (CPU can access now) Status
0: Not Empty
1: Empty(default)
EP2 OVLD1ROCurrent EP2 OUT Buffer Valid Flag Status Which buffer is the cur vld buffer depends on 0x334[2]
0x334[2]=1 -> Ping buffer
0x334[2]=0 -> Pong buffer
EP1 IVLD0ROCurrent EP1 IN Buffer Valid Flag Status Which buffer is the cur buffer depends on 0x334[2]
0x334[2]=1 -> Ping buffer
0x334[2]=0 -> Pong buffer



23.2 Endpoint2 PING FIFO Data Count (UDEP2PIC)
Address: 0x9C102B88
Reset: 0x0000 0000 


Field Name

Bit

Access

Description

Reserve31:13ROReserve
RESET EP12 PING CNTR12RUwrite 1: BULK OUT=move r ptr to 0; BULK IN=move w ptr to 0
Reserve11:10ROReserve
EP12 PING CNTRL9:0RUWrite : modify read or write pointer; Read : BULK OUT
= valid byte count BULK IN before SET IN VLD= write pointer BULK IN after SET IN VLD= valid byte count NOTE: But mostly when EP1 IVLD is set or EP2 OVLD is clear, another IN-UnValid or Out-Valid buffer will be switch to CPU domain. So After EP1 IVLD is set or EP2 OVLD is clear, you have to make sure the result be- long to what you want to know



23.3 Endpoint2 PONG FIFO Data Count (UDEP2POC)
Address: 0x9C102B8C

Reset: 0x0000 0000


Field Name

Bit

Access

Description

Reserve31:13ROReserve
RESET EP12 PONG CNTR12RUwrite 1: BULK OUT=move r ptr to 0; BULK IN=move w ptr to 0
Reserve11:10ROReserve
EP12 PONG CNTRL9:0RUWrite: modify read or write pointer; Read:
BULK OUT = valid byte count
BULK IN before SET IN VLD= write pointer
BULK IN after SET IN VLD= valid byte count



23.4 Endpoint2 FIFO Data Port (UDEP2FDP)
Address: 0x9C102B90
Reset: 0x0000 0000


Field Name

Bit

Access

Description

EP12 DATA PORT

31:0

RU

Read/write data from/to ping or pong buffer according to UDEP12PPC[2]

co-work with 0x394 when write and read For more detail,refer to NOTE



23.5 Endpoint2 FIFO Data Port vld byte (UDEP2VB)
Address: 0x9C102B94
Reset: 0x0000 0000 


Field Name

Bit

Access

Description

Reserve31:4ROReserve
UDEP12VB3:0RWRead/write data from/to ping or pong buffer according to UDEP12PPC[2]
co-work with 0x390 when write and read For more detail,refer to NOTE Default:0x0



23.8 Endpoint9 Ping-Pong FIFO Control (UDEP9PPC)
Address: 0x9C102BA0
Reset: 0x0000 0001


Field Name

Bit

Access

Description

Reserve31:3ROReserved
Current Buff2ROCurrent Buffer
1: Buffer0 (PING) buffer is controllable for CPU/DMA;
0:Buffer1(PONG)buffer iscontrollable for
CPU/DMA(default)
Switch Buffer1OtherSwitch Buffer
Write 1 to switch Buffer0/Buff1
Auto Switch En0RWbuffer auto switch enable
0: ping pong will NOT auto switch;
1: ping pong will auto switch(default)



23.9 Endpoint9 FIFO Status (UDEP9FS)

Address: 0x9C102BA4 

Reset: 0x0000 0044


Field Name

Bit

Access

Description

Reserve

31:8

RO

Reserve

N MSDC CMD

7

RO

Data in Next Buffer match the MSDC Command format
0: Not match MSDC CMD pattern(default)
1: Match MSDC CMD pattern

A FIFO EMPTY

6

RO

Another Buffer (CPU can't access now) Status
0: Not Empty
1: Empty(default)

A EP2 OVLD

5

RO

Another EP2 OUT Buffer Valid Flag Status
Which buffer is the another buffer depends on 0x334[2]
0x334[2]=1 -> Pong buffer
0x334[2]=0 -> Ping buffer

A EP1 IVLD

4

RO

Another EP1 IN Buffer Valid Flag Status
Which buffer is the another buffer depends on 0x334[2]
0x334[2]=1 -> Pong buffer
0x334[2]=0 -> Ping buffer

MSDC CMD VLD

3

RO

Data in Current EP2 Out Buffer (CPU can access now)
match the MSDC Command format
0: Not match MSDC CMD pattern(default)
1: Match MSDC CMD pattern

FIFO EMPTY

2

RO

Data in Current Buffer (CPU can access now) Status
0: Not Empty
1: Empty(default)

EP2 OVLD

1

RO

Current EP2 OUT Buffer Valid Flag Status Which buffer is the cur vld buffer depends on 0x334[2]
0x334[2]=1 -> Ping buffer
0x334[2]=0 -> Pong buffer

EP1 IVLD

0

RO

Current EP1 IN Buffer Valid Flag Status Which buffer is the cur buffer depends on 0x334[2]
0x334[2]=1 -> Ping buffer
0x334[2]=0 -> Pong buffer



23.10 Endpoint9 PING FIFO Data Count (UDEP9PIC)
Address: 0x9C102BA8
Reset: 0x0000 0000 


Field Name

Bit

Access

Description

Reserve31:13ROReserve
RESET EP12 PING CNTR12RU

Full Name ?

write 1:

BULK OUT=move r ptr to 0;

BULK IN=move w ptr to 0

Reserve11:10ROReserve
EP12 PING CNTRL9:0RUWrite : modify read or write pointer; Read : BULK OUT
= valid byte count BULK IN before SET IN VLD= write pointer BULK IN after SET IN VLD= valid byte count NOTE: But mostly when EP1 IVLD is set or EP2 OVLD is clear, another IN-UnValid or Out-Valid buffer will be switch to CPU domain. So After EP1 IVLD is set or EP2 OVLD is clear, you have to make sure the result be- long to what you want to know



23.11 Endpoint9 PONG FIFO Data Count (UDEP9POC)
Address: 0x9C102BAC

Reset: 0x0000 0000

Field Name

Bit

Access

Description

Reserve31:13ROReserve
RESET EP12 PONG CNTR12RU

Full Name ?

write 1:

BULK OUT=move r ptr to 0;

BULK IN=move w ptr to 0

Reserve11:10ROReserve
EP12 PONG CNTRL9:0RUWrite : modify read or write pointer; Read : BULK OUT
= valid byte count BULK IN before SET IN VLD= write pointer BULK IN after SET IN VLD= valid byte count NOTE: But mostly when EP1 IVLD is set or EP2 OVLD is clear, another IN-UnValid or Out-Valid buffer will be switch to CPU domain. So After EP1 IVLD is set or EP2 OVLD is clear, you have to make sure the result be- long to what you want to know



23.12 Endpoint9 FIFO Data Port (UDEP9FDP)
Address: 0x9C102BB0
Reset: 0x0000 0000


Field Name

Bit

Access

Description

EP12 DATA PORT

31:0

RU

Read/write data from/to ping or pong buffer according to UDEP12PPC[2]

co-work with 0x3B4 when write and read For more detail,refer to NOTE



23.13 Endpoint9 FIFO Data Port vld byte (UDEP9VB)
Address: 0x9C102BB4
Reset: 0x0000 0000 


Field Name

Bit

Access

Description

Reserve31:4ROReserve
UDEP12VB

3:0

RW

Read/write data from/to ping or pong buffer according to UDEP12PPC[2]

co-work with 0x3B0 when write and read For more detail,refer to NOTE Default:0x0



23.16 Endpoint11 Ping-Pong FIFO Control (UDEPBPPC)
Address: 0x9C102BC0
Reset: 0x0000 0001


Field Name

Bit

Access

Description

Reserve31:3ROReserved
Current Buff2ROCurrent Buffer
1: Buffer0 (PING) buffer is controllable for CPU/DMA;
0:Buffer1(PONG)buffer iscontrollable for CPU/DMA(default)
Switch Buffer1OtherSwitch Buffer
Write 1 to switch Buffer0/Buff1
Auto Switch En0RWbuffer auto switch enable
0: ping pong will NOT auto switch;
1: ping pong will auto switch(default)



23.17 Endpoint11 FIFO Status (UDEPBFS)
Address: 0x9C102BC4
Reset: 0x0000 0044


Field Name

Bit

Access

Description

Reserve31:8ROReserve
N MSDC CMD7ROData in Next Buffer match the MSDC Command format
0: Not match MSDC CMD pattern(default)
1: Match MSDC CMD pattern
A FIFO EMPTY6ROAnother Buffer (CPU can't access now) Status
0: Not Empty
1: Empty(default)

A EP2 OVLD

5

RO

Another EP2 OUT Buffer Valid Flag Status
Which buffer is the another buffer depends on 0x334[2]
0x334[2]=1 -> Pong buffer
0x334[2]=0 -> Ping buffer

A EP1 IVLD

4

RO

Another EP1 IN Buffer Valid Flag Status
Which buffer is the another buffer depends on 0x334[2]
0x334[2]=1 -> Pong buffer
0x334[2]=0 -> Ping buffer

MSDC CMD VLD

3

RO

Data in Current EP2 Out Buffer (CPU can access now)
match the MSDC Command format
0: Not match MSDC CMD pattern(default)
1: Match MSDC CMD pattern(default)

FIFO EMPTY

2

RO

Data in Current Buffer (CPU can access now) Status
0: Not Empty
1: Empty(default)

EP2 OVLD

1

RO

Current EP2 OUT Buffer Valid Flag Status Which buffer is the cur vld buffer depends on 0x334[2]
0x334[2]=1 -> Ping buffer
0x334[2]=0 -> Pong buffer

EP1 IVLD

0

RO

Current EP1 IN Buffer Valid Flag Status Which buffer is the cur buffer depends on 0x334[2]
0x334[2]=1 -> Ping buffer
0x334[2]=0 -> Pong buffer



23.18 Endpoint11 PING FIFO Data Count (UDEPBPIC)
Address: 0x9C102BC8
Reset: 0x0000 0000 


Field Name

Bit

Access

Description

Reserve31:13
Reserve
RESET EP12 PING CNT12RUROR
ROwrite 1: BULK OUT=move r ptr to 0; BULK IN=move w ptr to 0
Reserve11:10
Reserve

EP12 PING CNTRL

9:0

RU

Write : modify read or write pointer;

Read : BULK OUT = valid byte count BULK IN before SET IN VLD= write pointer BULK IN after SET IN VLD= valid byte count (What does it mean?)

NOTE:  But mostly when EP1 IVLD is set or EP2 OVLD is clear, another IN-UnValid or Out-Valid buffer will be switch to CPU domain. So After EP1 IVLD is set or EP2 OVLD is clear, you have to make sure the result belong to what you want to know



23.19 Endpoint11 PONG FIFO Data Count (UDEPBPOC)
Address: 0x9C102BCC

Reset: 0x0000 0000 


Field Name

Bit

Access

Description

Reserve31:13ROReserve
RESET EP12 PO12NG CNTR12RUwrite 1: BULK OUT=move r ptr to 0; BULK IN=move w ptr to 0
Reserve11:10ROReserve
EP12 PONG CNTRL9:0RUWrite: modify read or write pointer; Read:
BULK OUT = valid byte count
BULK IN before SET IN VLD= write pointer
BULK IN after SET IN VLD= valid byte count



23.20 Endpoint11 FIFO Data Port (UDEPBFDP)
Address: 0x9C102BD0
Reset: 0x0000 0000 

Field Name

Bit

Access

Description

EP12 DATA PORT

31:0

RU

Read/write data from/to ping or pong buffer according to UDEP12PPC[2]

co-work with 0x3D4 when write and read For more detail,refer to NOTE



23.21 Endpoint11 FIFO Data Port vld byte (UDEPBVB)
Address: 0x9C102BD4
Reset: 0x0000 0000 


Field Name

Bit

Access

Description

Reserve31:4ROReserve
UDEP12VB3:0RWRead/write data from/to ping or pong buffer according to UDEP12PPC[2]
co-work with 0x3D0 when write and read
For more detail,refer to NOTE(default)



USB Controller 1 (USBC1) please refer to USB Controller 0 (USBC0) corresponding register group description.  Register Group base address please refer to USBC1 register memory map.