14. Universal Serial Bus (USB)

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Last updated: Dec 16, 2019

14.1 Introduction

The USB is specified to be an industry-standard extension to the PC architecture. It provides an USB compliant connection between the host PC and the function implemented by the microcontroller. It also supports USB-OTG (On-The-Go) function to connect with peripheral USB devices. Data transfer between the host PC and the system memory occurs through a dedicated packet buffer memory accessed directly by the USB peripheral. The size of this dedicated buffer memory must be according to the number of endpoints used and maximum packet size. The dedicated memory is sized to 512bytes and up to 16 mono-directional endpoints can be used. This USB supports 4 kind endpoint transactions, they are Control, Bulk, Interrupt and Isochronous transfer mode.
A USB system is described by three definitional areas, USB PHY (UPHY) , USB Controller System (USBC) and On-The-Go (OTG) Controller. Where USB Controller system includes two major parts: USB host controller(UHC) and USB device controller(UDC). The USB transfer signals and power over a four-wire cable, the signaling occurs over wires on each point-to-point segment.
The USB HOST IP (UHC) is a USB2.0 Host Controller,  Support both Enhanced Host Controller Interface (EHCI) and Open Host Controller Interface (OHCI), 32bit AHB/AXI configure bus, 64bit AXI data bus. The USB DEVICE IP (UDC) is a standard USB Device Controller  which supports USB2.0 High Speed and Full speed, AXI Master bus, AXI Master1 bus (used for ISO auto DMA), AHB slave bus and UTMI (USB2.0 Transceiver Macrocell Interface) interface. The USB PHY module supports working in Host or Device mode and can dynamic switch.
The USB control registers located in the memory map address range of 9c102000h~9c103fffh. The USB PHY control registers located in the 9c004a80h~9c004b7fh. SP7021 totally supports two USB2.0 modules, the features list as below.

  • UTMI+ level3 compatible with OTG
  • 27MHz crystal input to support Battery Charger and sync signals
  • Integrated Phase-Locked Loop (PLL) oscillator generate 120M CLK to DPHY
  • Supports various power down modes include Operating, Partial and Suspend modes
  • Supports high-speed (HS, 480 Mbps), full-speed (FS, 12Mbps) and low-speed (LS, 1.5Mbps) data transfer rates
  • OTG supports Attach Detection Protocol (ADP), Session Request Protocol (SRP) and Host Negotiation Protocol (HNP)
  • Support boot from each USB port
  • Support USB video class (UVC)

14.2 Function Diagram

A generalized function diagram of USB is shown in Figure 14-1.

Figure 14-1 USB Functional Blocks

  • AHB_IF: Advanced High-performance Bus (AHB) Interface block, used as AHB bus master data and configure register
  • AXI_IF: Advanced Extensible Interface (AXI) block, used for high performance read, write and address access.
  • Enhanced Host Controller Block(EHCI): Standard Enhanced Host Controller Interface IP.
  • Open Host Controller Block(OHCI): Standard Open Host Controller Interface IP.
  • USB Device Controller Block(UDC): SUNPLUS USB Device Controller IP.
  • Hub Configure registers(RHREG): Root Hub Configure registers block
  • PORT Routing & Control Logic: Generate PHY Control signals (UTMI).
  • UPHY: Convert parallel data of UTMI into serial data, and output to the outside of the chip through differential data lines.


14.2.1 OHCI Block Diagram

The EHCI has the same structure as OHCI, so below description will focus on OHCI block. Figure 14-2 shows generic OHCI Block Diagram.


Figure 14-2 OHCI Block Diagram

  • ohci_reg: This is OHCI register control block. Use the AHB master to read/write the OHCI register which generate control signal to OHCI.
  • ohci_td: This is OHCI data structure process block. The TD is Transfer Descriptor of OHCI.
  • ohci_core: This is OHCI main block, used to R/W ED (Endpoint Descriptor) and TD, and control USB Transfers.
  • ohci_pie: This block is used to control USB port state, such as reset、suspend and resume, generate port control signals.


14.2.2 USB Device Controller (UDC) Block Diagram

Figure 14-3 shows a generic UDC Block Diagram.

Figure 14-3 UDC Block Diagram

  • AXI master1:
    • Receive the command from USB and issue AXI transition
    • It contains 1*audio DMA, 1*video DMA and 3*bulk DMA
    • It contains the DMA arbitration mechanism
  • AXI master2:
    • Including AXI transition control for ISO auto DMA mode
  • AHB slave:
    • receive the command from system and issue AHB transition
    • It contains the configure registers, CPU can write or read these registers by AHB bus
  • DMA: DMA logic, issue data transition
  • ISO DMA: ISO auto DMA block
    • Including ISO IN and ISO OUT DMA control for TRB and Data Read/Write
    • Including DMA arbitration mechanism
  • SYNC: Sync logic between SYS clock domain and PHY clock domain
  • Async FIFO: Sync data between the two clock domain
  • Buffer: data buffer
  • EPx: EPx (Endpoint x) control logic
  • Device IP Link-layer: USB link layer transition logic
  • EP5 DMA: ISO IN DMA for Endpoint5
  • EP7 DMA: ISO IN DMA for Endpoint7
  • EPC DMA: ISO OUT DMA for EndpointC
  • DMA ARB: DMA Arbiter for ISO Endpoints


14.2.3 OTG Transceiver Block Diagram

Figure 14-4 shows a generic OTG Transceiver Block Diagram.

Figure 14-4 OTG Transceiver Block Diagram

  • REG: Receive the command from system and issue AHB transition. It contains the configure registers and CPU can read or write these registers by AHB bus.
  • OTG ctrl: Provide flags to deal with OTG functions (SRP/HNP/ADP). It also provides select signal to MUX module.
  • MUX: Select UTMI data to host controller or device controller.

14.2.4 UPHY Block Diagram

Figure 14-5 shows a generic UPHY Block Diagram

Figure 14-5 UPHY Block Diagram

  • FS_TX_ALL/HS_TX_ALL : Receive signals from the UTMI interface in full-speed, low-speed and high-speed mode, through bit stuffer and encode, then pass the buffer to the APHY
  • FS_RX_ALL : Receive data from the APHY in full-speed or low-speed mode. After Decode and bit unstuffing, the data is converted to UTMI and output to Host or Device.
  • HS_RX_ALL : In high-speed mode, 20bit data is accepted from the APHY, and the data is separated from the clock according to the CDR, and 5 bit data is sampled. After Decode and bit unstuffing, the data is output from the UTMI interface to Host or Device.
  • PATTERNGEN: Generate test-related patterns through I2C or BIST mode
  • CTRL_TOP :
    • The TX/RX enable signal of HS/FS/LS is generated based on the UTMI signal.
    • Output line state signal on UTMI interface
    • Control pull-up and pull-down resistors on the DP/DM line
    • In HS mode, generate HOST_DISC signal, HOST_DISC=0, device connection, HOST_DISC=1, device disconnected
  • SERIAL_CTRL: Write or read register values to UPHY internally via I2C or RGST BUS mode
  • CLOCK_MANAGER: Generate L120_CLK and UTMI_CLK. When suspend, generate PLL_OFF to turn off the PLL.
  • RXCHECKER_PHY: Check if the data during transmission is correct


14.3 USB Host Controller

When insert a USB device, the USB host controller will trigger EHCI/OHCI interrupt to tell software that there is a USB device inserted.

14.3.1 OHCI Controller

Figure 14-6 shows four main areas of a Universal Serial Bus system. These areas are the Client Software/USB Driver, Host Controller Driver (HCD), Host Controller (HC) and USB Device. OHCI specifies the interface between the Host Controller Driver and the Host Controller and the fundamental operation of each.

Figure 14-6 OHCI controller
There are two communication channels between the Host Controller and the Host Controller Driver (Please refer to figure 14-7). The first channel uses a set of operational registers located on the HC. The Host Controller is the target for all communication on this channel. The operational registers contain control, status, and list pointer registers. Within the operational register set is a pointer to a location in shared memory named the Host Controller Communications Area (HCCA). The HCCA is the second communication channel. The Host Controller is the master for all communication on this channel. The HCCA contains the head pointers to the interrupt Endpoint Descriptor lists, the head pointer to the done queue, and status information associated with start-of-frame processing.

Figure 14-7 OHCI communication channel

14.3.2 EHCI Controller

A USB Host System is composed of a number of hardware and software layers. The Figure 14-8 illustrates a conceptual block diagram of the building block layers in a host system that work in concert to support USB2.0.

Figure 14-8 EHCI controller
This architecture allows the USB 2.0 host controller to provide USB functionality as long as there is at least USB 1.1 software support in the resident operating system. Full USB 2.0 functionality is delivered when both USB 1.1 and EHCI software is available in the operating system. The port transceiver routing logic is key to delivering this flexible operating environment. The state of the routing logic initially depends on whether software has configured the EHCI controller. Once the EHCD driver has configured the EHCI controller, it can specifically release the transceiver to the companion host controller port register if the attached device is not a high-speed device. When the operating system does not include support for the EHCI controller, the ports are default-routed to the companion host controllers and existing USB support for Full- and Low-speed devices remains.

Figure 14-9 Companion Host Controller
The Companion Host Controller (CHC) may be any USB 1.1 host controller (e.g. OHCI or UHCI). The Companion Host Controllers always manage Full- and Low-speed USB devices connected to the root ports. The CHCs have no knowledge of the high-speed-mode host controller. They can possibly be integrated into a USB 2.0 host controller with no modification.
The EHCI interface defines three interface spaces:

  1. PCI Configuration Space: If the implementation includes PCI registers, they are used for system component enumeration and PCI power management.
  2. Register Space: Implementation-specific parameters and capabilities, plus operational control and status registers. This space, normally referred to as I/O space, must be implemented as memory-mapped I/O space.
  3. Schedule Interface Space: This is typically memory allocated and managed by the EHC Driver for the periodic and asynchronous schedules.


Figure 14-10 EHCI interface

14.3.3 OTG Controller

OTG driver used to control OTG controller work normally. OTG driver mainly maintain a OTG state machine and reflect platform USB state. When OTG is in the different OTG state, OTG driver will control OTG controller to do different things. For example, when OTG state become A-device, OTG driver configure registers to raise VBUS signal and control OTG controller to switch platform to USB host mode. When OTG state become B-device, OTG driver will configure registers to drop VBUS signal and control OTG controller to switch platform to USB device mode to wait host enumerate itself. And so on.

14.4 Data Transfer Types

There are four data transfer types defined in USB. Each type is optimized to match the service requirements between the client software and the USB device. The four types are:

  • Control Transfers: Nonperiodic data transfers used to communicate configuration/command/status type information between client software and the USB device. It must be through Endpoint 0, and there can only be one device, and it must be supported. The maximum data size that can be transmitted at one time is 64 bytes and is bidirectional. Basically, when a USB device is plugged into the computer, the computer will ask for some information through Endpoint 0. According to the USB 2.0 specification, Host must reserve 10% of the bandwidth for Control transmission.
  • Bulk Transfers: Nonperiodic data transfers used to communicate large amounts of information between client software and the USB device. The maximum size of data that can be transmitted at one time is 512 bytes (HS). It does not guarantee the bandwidth, it is usually HOST that the BUS has a bandwidth to choose to transmit Bulk data. In contrast, if the bandwidth is very idle, the amount of data that can be transmitted per second is large.
  • Interrupt Transfers: Small data transfers used to communicate information from the USB device to the client software. The Host Controller Driver polls the USB device by issuing tokens to the device at a periodic interval sufficient for the requirements of the device. The maximum data size that can be transmitted at one time is 1024 bytes (HS), and it is transmitted periodically. The device side needs to declare how long this period is. In HS, it is in micro-second. It requires HOST to guarantee the bandwidth. If HOST cannot meet the bandwidth requirements of this device, HOST can refuse to start the device.
  • Isochronous Transfers: Periodic data transfers with a constant data rate. Data transfers are correlated in time between the sender and receiver. It is very similar to Interrupt transmission, but it has no mechanism for error retransmission. All above three mode have a mechanism of error retransmission, and this mechanism is based on the premise that each transmission will have an ACK packet. Isochronous transmission does not require ACK packets, so it naturally can't detect errors.

In OHCI the data transfer types are classified into two categories: periodic and nonperiodic. Periodic transfers are interrupt and isochronous since they are scheduled to run at periodic intervals. Nonperiodic transfers are control and bulk since they are not scheduled to run at any
specific time, but rather on a time-available basis.

14.5 Data Structure

14.5.1 OHCI Data Structure

The basic building blocks for communication across the interface are the Endpoint Descriptor(ED) and Transfer Descriptor (TD). Each data transfer type has its own linked list of Endpoint Descriptors to be processed. Figure 14-10, Typical List Structure, is a representation of the data structure relationships.

Figure 14-11 OHCI data structure
Endpoint Descriptors
The Host Controller Driver assigns an Endpoint Descriptor to each endpoint in the system. The Endpoint Descriptor contains the information necessary for the Host Controller to communicate with the endpoint. The fields include the maximum packet size, the endpoint address, the speed of the endpoint, and the direction of data flow. Endpoint Descriptors are linked in a list.
An Endpoint Descriptor (ED) is a 16-byte, memory resident structure that must be aligned to a 16-byte boundary. The Host Controller traverses lists of EDs and if there are TDs linked to an ED, the Host Controller performs the indicated transfer.
Figure 14-11 shows Endpoint Descriptor Format.

Figure 14-12 Endpoint Descriptor Format
Notes:
1. Fields containing '—' are not interpreted or modified by the Host Controller and are available for use by the Host Controller Driver for any purpose.
2. Fields containing '0' must be written to 0 by the Host Controller Driver before queued for Host Controller processing. If Host Controller has write access to the field, it will always write the field to 0.
Transfer Descriptors
A queue of Transfer Descriptors is linked to the Endpoint Descriptor for the specific endpoint. The Transfer Descriptor contains the information necessary to describe the data packets to be transferred. The fields include data toggle information, shared memory buffer location and completion status codes. Each Transfer Descriptor contains information that describes one or more data packets. The data buffer for each Transfer Descriptor ranges in size from 0 to 8192 bytes with a maximum of one physical page crossing. Transfer Descriptors are linked in a queue, the first one queued is the first one processed.
A Transfer Descriptor (TD) is a system memory data structure that is used by the Host Controller to define a buffer of data that will be moved to or from an endpoint. TDs come in two types: general and isochronous. The General TD is used for Interrupt, Control, and Bulk Endpoints and an Isochronous TD is used to deal with the unique requirements of isochronous transfers. Two TD types are supported because the nature of isochronous transfers does not lend itself to the standard DMA buffer format and the packetizing of the buffer required for isochronous transfers is too restrictive for general transfer types.
General Transfer Descriptor
Transfers for control, bulk, and interrupt all use the same format for their Transfer Descriptor (TD). This General TD is a 16-byte, host memory structure that must be aligned to a 16-byte boundary.
Figure 14-12 shows General Transfer Descriptor Format.

Figure 14-13 General Transfer Descriptor Format
Isochronous Transfer Descriptor
An Isochronous TD is used exclusively for isochronous endpoints. All TDs linked to an ED with F = 1 must use this format. This 32-byte structure must be aligned to a 32-byte boundary in system memory.
Figure 14-13 shows General Transfer Descriptor Format.

Figure 14-14 Isochronous Transfer Descriptor Format

14.5.2 EHCI Data Structure

The data structure definitions in this chapter support a 32-bit memory buffer address space. The interface consists of a Periodic Schedule, Periodic Frame List, Asynchronous Schedule, Isochronous Transaction Descriptors, Split-transaction Isochronous Transfer Descriptors, Queue Heads and Queue Element Transfer Descriptors.
Periodic Frame List
This schedule is for all periodic transfers (isochronous and interrupt). The periodic schedule is referenced from the operational registers space using the PeriodicListBase address register and the FRINDEX register. The periodic schedule is based on an array of pointers called the Periodic Frame List. The PeriodicListBase address register is combined with the FRINDEX register to produce a memory pointer into the frame list. The Periodic Frame List implements a sliding window of work over time.

Figure 14-15 Periodic Frame List
Asynchronous List Queue Head Pointer
The Asynchronous Transfer List (based at the AsyncListAddr register), is where all the control and bulk transfers are managed. Host controllers use this list only when it reaches the end of the periodic list, the periodic list is disabled, or the periodic list is empty.

Figure 14-16 Asynchronous Transfer List

14.6 UTM Interface Timing Diagram


Figure 14-17 TX odd byte data

Figure 14-18 TX even byte data

Figure 14-19 RX odd byte data

Figure 14-20 RX even byte data

14.7 OHCI USB States

The Host Controller has four USB states visible to the Host Controller Driver via the Operational Registers: USBOPERATIONAL, USBRESET, USBSUSPEND, and USBRESUME. These states define the Host Controller responsibilities relating to USB signaling and bus states.

Figure 14-21 USB states

14.7.1 USBOPERATIONAL

When in the USBOPERATIONAL state, the Host Controller may process lists and will generate SOF Tokens. The USBOPERATIONAL state may be entered from the USBRESUME or USBRESET states. It may be exited to the USBRESET or USBSUSPEND states. When transitioning from USBRESET or USBRESUME to USBOPERATIONAL, the Host Controller is responsible for terminating the USB reset or resume signaling as defined in the USB Specification prior to sending a token.

14.7.2 USBRESET

When in the USBRESET state, the Host Controller forces reset signaling on the bus. The Host Controller's list processing and SOF Token generation are disabled while in USBRESET. The USBRESET state can be entered from any state at any time. The Host Controller defaults to the USBRESET state following a hardware reset. The Host Controller Driver is responsible for satisfying USB Reset signaling timing defined by the USB Specification.

14.7.3 USBSUSPEND

The USBSUSPEND state defines the USB Suspend state. The Host Controller's list processing and SOF Token generation are disabled. However, the Host Controller's remote wakeup logic must monitor USB wakeup activity. USBSUSPEND is entered following a software reset or from the USBOPERATIONAL state on command from the Host Controller Driver. While in USBSUSPEND, the Host Controller may force
a transition to the USBRESUME state due to a remote wakeup condition. This transition may conflict with the Host Controller Driver initiating a transition to the USBRESET state. If this situation occurs, the HCD-initiated transition to USBRESET has priority. The Host Controller Driver must wait 5 ms after transitioning to USBSUSPEND before transitioning to the USBRESUME state. Likewise, the Root Hub must wait 5 ms after the Host Controller enters USBSUSPEND before generating a local wakeup event and forcing a transition to USBRESUME. Following a software reset, the Host Controller Driver may cause a transition to USBOPERATIONAL if the transition occurs no more than 1 ms from the transition into USBSUSPEND. If the 1-ms period is violated, it is possible that devices on the bus will go into Suspend.

14.7.4 USBRESUME

When in the USBRESUME state, the Host Controller forces resume signaling on the bus. While in USBRESUME, the Root Hub is responsible for propagating the USB Resume signal to downstream ports as specified in the USB Specification. The Host Controller's list processing and SOF Token generation are disabled while in USBRESUME. USBRESUME is only entered from USBSUSPEND. The transition to USBRESUME can be initiated by the Host Controller Driver or by a USB remote wakeup signaled by the Root Hub. The Host
Controller is responsible for resolving state transition conflicts between the hardware wakeup and Host Controller Driver initiated state transitions. Legal state transitions from USBRESUME are to USBRESET and to USBOPERATIONAL. The Host Controller Driver is responsible for USB Resume signal timing as defined by the USB Specification.

14.8 USB OPERATION

14.8.1 OHCI Initialization

Initialize the open host controller, software should perform the following steps:

  • Set software reset in Group1.1 UHO_HcControl register bit[7:6]=0.
  • Configure OHCI command in Group1.1 UHO_HcControl register.
  • Select routed all ports to OHCI by set 0 to bit0 of Group2.24 UHE_CONFIGFLAG register.

Note: Due to some devices on the USB that may take a long time to reset, it is desirable that the Host Controller Driver startup process not transition to the USBRESET state if possible.

14.8.2 EHCI Initialization

In order to initialize the enhanced host controller, software should perform the following steps:

  • Set software reset in Group2.8 UHE_USBCMD register bit[1]=1.
  • Program the Group2.12 UHE_CTRLDESSEGMENT register with 4-Gigabyte segment where all of the interface data structures are allocated.
  • Write the appropriate value to the Group2.10 UHE_USBINTR register to enable the appropriate interrupts.
  • Write the base address of the Periodic Frame List to the Group2.13 UHE_PERIODICLISTBASE register. Write the base address of the Asynchronous Frame List to the Group2.14 UHE_ASYNCLISTBASE register.
  • Enable Periodic schedule in Gruop2.8 UHE_USBCMD register bit4, enable Asynchronous schedule in Gruop2.8 UHE_USBCMD register bit5.
  • Write the Group2.8 UHE_USBCMD register to set the desired interrupt threshold, frame list size (if applicable).
  • Write 1 to bit0 of Group2.24 UHE_CONFIGFLAG register to route all ports to the EHCI controller.
  • Wait device connect by check Group2.25 UHE_PORTSC register bit0=1.
  • Issue port reset by set Group2.25 UHE_PORTSC register bit8=1.
  • Turn the host controller ON via setting the Run/Stop bit in Gruop2.8 UHE_USBCMD register bit0.


14.8.3 OTG Initialization

  • Select work mode in Group8.0 MODE_SELECT register bit[1:0]. Default as 0 with OTG2.0.
  • Confirm work role by read Group8.0 MODE_SELECT register bit[1:0] after "ID_CHANGE_IF" interrupt is assert. The ID_CHANGE_IF flag is in Group8.3 OTG_ST register bit1.
  • Depend on work mode, set initial of OTG CTRL in Group8.1 OTG_DEVICE_CTRL register. Set SRP/ADP_SUPPORT in Group8.0 MODE_SELECT bit2 and bit3
  • Set SRP/HNP/ADP related timers in Group8.4~8.29 registers.


14.9 Pattern of come to USB2.0

Define the line state J, K, SE0 of USB, that is, D+, D-, as shown in the following table.


J

K

SE0

D+

1

0

0

D-

0

1

0


USB 2.0 is made under the existing architecture that does not destroy USB1.1. Unless host and device are both 2.0, they are all transmitted with 1.1. The method of recognition is chirp, which is described as follows. The yellow line is D+ and the blue line is D-. The timing is as follows:

Figure 14-22 USB2.0 chirp pattern

  • D+ pull up to 3.3V after device plug in
  • Host drive bus reset (se0, both D+,D- = 0)
  • Device chirp K 1ms-7ms. (D- = 800mV)
  • Host chirp KJKJKJ sequence pattern
  • Device recognizes 6 groups of kj and enters USB2.0 mode, turn on 45 Ohm pull down to GND at the same time, it make 800mV level become 400mV.



14.10 USB Interrupts

14.10.1 OHCI Interrupts

OHCI interrupt is from OHCI block with level signals. The detail interrupt information refer to the USBC0 Group1.3 bit[6:0] UHO_HcInterruptStatus Register. The enable register is USBC0 Group1.4 bit[6:0] UHO_HcInterruptEnable. Figure 14-23 shows the OHCI interrupt tree.

Figure 14-23 OHCI interrupt tree

  • RHSC: Root Hub content change status bit
  • FNO: Frame number overflow status bit
  • UE: Un-recoverable error
  • RD: Resume signaling detected status bit
  • SF: Each start of a frame status bit
  • WDH: HC has written HcDoneHead to HccaDoneHead status bit
  • SO: USB schedule for the current Frame overruns status bit


14.10.2 EHCI Interrupts

EHCI interrupt is from EHCI block with level signals. The detail interrupt information refer to the USBC0 Group2.9 bit[5:0] UHE_USBSTS register. The enable register is USBC0 Group2.10 bit[5:0] UHE_USBINTR. Figure 14-24 shows the EHCI interrupt tree.

Figure 14-24 EHCI interrupt tree

  • IAA: Indicates the assertion of Async Advance interrupt
  • HSE: Host system error
  • FLR: Indicate the Frame List Index rolls over from its maximum value to zero
  • PCD: Indicate any port of the port owner bit is set to zero or from zero to a one
  • USBERRINT: Indicate completion of a USB transaction results in an error condition
  • USBINT: Indicate the completion of a USB transaction


14.10.3 OTG Interrupts

The detail OTG interrupt information refer to the USBC0 Group8.3 bit[9:0] OTG_ST register. The enable register is USBC0 Group8.2 bit[9:0] OTG_INT_EN. Figure 14-25 shows the OTG interrupt tree.

Figure 14-25 OTG interrupt tree

  • ADP_CHANGE_IF: Indicate the ADP changed
  • A_SRP_DET_IF: Indicate A-device(Host side) have detected SRP
  • B_AIDL_BDIS_IF: Indicate B-device(Device side) disconnects to A-device(Host side) to start HNP
  • A_BIDL_ADIS_IF: Indicate A-device(Host side) disconnects to B-device(Device side) to start HNP
  • A_AIDL_BDIS_TMOUT_IF: Waiting for a disconnect timeout when HNP
  • B_SRP_FAIL_IF: B-device SRP fail
  • BDEV_CONNECT_TMOUT_IF: A-device waits B-device connect timeout
  • VBUS_RISE_TMOUT_IF: A-device waits vbus valid timeout
  • ID_CHANGE_IF: ID pin has changed
  • OVERCURRENT_IF: An attached B-device draws more current



14.11 Registers Map

14.11.1 Registers Memory Map

Memory Map Start Address

Data Width

Group No.

Module

0x9C004A80

32

149

UPHY0 (USB PHY 0)

0x9C004B00

32

150

UPHY1 (USB PHY1)

Table 14-1 USB PHY registers group list of RGST table

Both USB PHY registers have the same offset in corresponding register group. Only USB PHY0 (UPHY0) registers are described in following register description, for USB PHY1 please refer to UPHY0 description for more detail.

Memory Map Start Address

Data Width

Group No.

Module

0x9C102000

32

USBC0 Group 0

USB0 HOST

0x9C102080

32

USBC0 Group 1

USB0 OHCI

0x9C102100

32

USBC0 Group 2

USB0 EHCI

0x9C102400

32

USBC0 Group 8

USB0 OTG

0x9C102800

32

USBC0 Group 16

USB0 DMA

0x9C102880

32

USBC0 Group 17

USB0 INTERRUPT

0x9C102900

32

USBC0 Group 18

USB0 EP0~4

0x9C102980

32

USBC0 Group 19

USB0 EP5/6/7

0x9C102A00

32

USBC0 Group 20

USB0 EP8/9/A/B

0x9C102A80

32

USBC0 Group 21

USB0 EPC/D

0x9C102B00

32

USBC0 Group 22

USB0 Phyclk Domain Interrupt

0x9C102B80

32

USBC0 Group 23

USB0 Bulk Out FIFO

0x9C103000

32

USBC1 Group 0

USB1 HOST

0x9C103080

32

USBC1 Group 1

USB1 OHCI

0x9C103100

32

USBC1 Group 2

USB1 EHCI

0x9C103400

32

USBC1 Group 8

USB1 OTG

0x9C103800

32

USBC1 Group 16

USB1 DMA

0x9C103880

32

USBC1 Group 17

USB1 INTERRUPT

0x9C103900

32

USBC1 Group 18

USB1 EP0~4

0x9C103980

32

USBC1 Group 19

USB1 EP5/6/7

0x9C103A00

32

USBC1 Group 20

USB1 EP8/9/A/B

0x9C103A80

32

USBC1 Group 21

USB1 EPC/D

0x9C103B00

32

USBC1 Group 22

USB1 Phyclk Domain Interrupt

0x9C103B80

32

USBC1 Group 23

USB1 Bulk Out FIFO

Table 14-2 USB control registers group list of AMBA table

Only USB0 relative register group will be described in register description, for USB1, please refer to USB0 corresponding group description for more detail


14.11.2 Registers Description

RGST Table Group 149 UPHY0

149.0 CONFIG0 (cfg0)
Address: 0x9C004A80
Reset: 0x0000 0080


Field NameBitAccessDescription
Reserved31:8RORESERVED
J WAKE SEL7:5RWJ WAKE SEL controls wake up time.
0x0 : 0.54ms ˜ 1.09ms
0x1 : 1.09ms ˜ 1.68ms
0x2 : 1.68ms ˜ 2.18ms
0x3 : 2.18ms ˜ 2.73ms
0x4 : 2.73ms ˜ 3.27ms(default)
0x5 : 3.27ms ˜ 3.82ms
0x6 : 4.36ms ˜ 4.91ms
0x7 : 4.91ms ˜ 5.46ms
J ANG LB4RWAnalog Loopback mode.
0x0 : turn off analog loopback(default).
0x1 : turn on analog loopback.
J DIG LB3RWDigital Loopback mode.
0x0 : turn off digital loopback(default).
0x1 : turn on digital loopback.

J IPX2

2

RW

Charge Pump Current Option.
macro spec.

J ENABLE CNTR

1

RW

Bist mode counter enable of succcess and fail.
0 : Disable(default).
1 : Enable.

J CLEAR CNTR

0

RW

Bist mode counter clear of succcess and fail.
0 : Unclear(default).
1 : Clear.



149.1 CONFIG1 (cfg1)
Address: 0x9C004A84
Reset: 0x0000 0021


Field NameBitAccessDescription
Reserved31:8RORESERVED
J HS TX DELAY7:6RWFine tune TX Delay
0x0 : No delay(default).
0x1 : Delay 1 clock.
0x2 : Delay 2 clock.
0x3 : No delay.
J HS TX PWRSAV5RW

High Speed TX power saving. When this item actives, it means TX driver will turn on with TXValid.

When this item is low, it means TX driver will always turn on.
0x0 : Turn off power saving.
0x1 : Turn on power saving(default)

J HS RX DROP24RW

Set the EOP receive condition sensitive

If DEV_DET fall very quickly, this may cause some valid EOP bit lose and cause correct packet become RXERROR,

so this register set medium EOP detection.

0x0: do nothing(default)
0x1: set the EOP receive condition to be sensitive

J HS RX DROP43RW

Set the EOP receive condition very sensitive

If DEV_DET fall very quickly, this may cause some valid EOP bit lose and cause correct packet become RXERROR,

so this register set very sensitive EOP detection.

0: do nothing(default)
1: set the EOP receive condition to be very sensitive. In this case the setting will replace J HS RX DROP2

J HS RX LPFIL2:1RW

CDR data channel phase shift precision

0x0: shift precision is very high

0x1: shift precision is high

0x2: shift precision is medium

0x3: shift precision is slow

J FS TX PREDR IDLE0RWFor 1st cross over point perfection
0: Disable(default)
1 : Enable


149.2 CONFIG2 (cfg2)
Address: 0x9C004A88
Reset: 0x0000 0000 


Field NameBitAccessDescription
Reserved31:8RORESERVED
J DPN7:4RW

DP Full speed falling time select.

The larger the value, the shorter the DP falling transition time.

Default: 4'b0000

J DPP3:0RW

DP Full speed rising time select.

The larger the value, the shorter the DP rising transition time.

Default: 4'b0000



149.3 CONFIG3 (cfg3)

Address: 0x9C004A8C

Reset: 0x0000 0021


Field Name

Bit

Access

Description

Reserved

31:8

RO

RESERVED

J FORCE PU2 HI

7

RW

J FORCE PU2 HI
1: enable resistor ecn function, see ECN Res
0: do nothing(default)

J FORCE PU2 LO

6

RW

J FORCE PU2 LO
1: disable resistor ecn function, see ECN Res
0: do nothing(default)

J FORCE DISC ON

5

RW

Whenever DPDM PULLDOWN, the system force into chirp mode
0 : Turn off
1 : Turn on(default)

DEBUG_INT4:0RW

Reserved for internal debug purpose. Access to this register may cause unexpected malfunction




149.4 CONFIG4 (cfg4)
Address: 0x9C004A90
Reset: 0x0000 0020


Field NameBitAccessDescription
Reserved31:8RORESERVED
J IPX37RWCharge Pump Current Option.
macro spec.
J IPX16RWCharge Pump Current Option.
macro spec.

J SKIP NOXTION

5

RW

J SKIP NOXTION
1: when DP/DM doesn't toggle, clock and data recovery circuit will not work(default).
0: when DP/DM doesn't toggle, clock and data recovery circuit will work.

J PGMODE

4:0

RW

Pattern Selection of bist test
0x00 : NOTHING
0x01 : High Speed EYE Pattern in High Speed
0x02 : High Speed EYE Pattern in Full Speed
0x03 : Full Speed EYE Pattern in High Speed
0x04 : Full Speed EYE Pattern in Full Speed
0x05 : High Speed data Pattern
0x06 : Full Speed data Pattern
0x07 : High Speed idle SE0
0x08 : Full Speed idle J (NODRIVE)
0x09 : High Speed J
0x0a : High Speed K
0x0b : Full Speed J (DRIVE)
0x0c : Full Speed K
0x0d : High Speed SOF with many trans
0x0e : High Speed SOF with less trans same polarity
0x0f : High Speed SOF with less trans diff polarity
0x11 : error high speed eye pattern in high speed
0x12 : error high speed eye pattern in full speed
0x13 : Full Speed SOF with many trans
0x14 : Full Speed SOF with less trans same polarity
0x15 : Full Speed SOF with less trans diff polarity
0x16 : Disconnect test for fast FT without 45ohm
0x17 : 120Mbps 400mv swint for PLL verify
0x18 : 12Mbps full swing pattern for PLL verify
0x19 : High Speed EYE Pattern in Low Speed
0x1a : Full Speed EYE Pattern in Low Speed
0x1c : Low Speed idle J (NODRIVE)
0x1d : Low Speed J (DRIVE)
0x1e : Low Speed K
0x1f : error high speed eye pattern in low speed



149.5 CONFIG5 (cfg5)
Address: 0x9C004A94
Reset: 0x0000 0000



Field Name

Bit

Access

Description

Reserved

31:8

RO

RESERVED

SUCC CNTR

7:4

RU

Bit mode success counter

When successive 15 packages success, BIST test success and done.

FAIL CNTR

3:0

RU

Bit mode fail counter

When successive 15 packages fail, BIST test fail and done.


149.6 CONFIG6 (cfg6)
Address: 0x9C004A98 

Reset: 0x0000 0000


Field NameBitAccessDescription
Reserved31:8RORESERVED
J DMN7:4RW

DM Full speed falling time select.

The larger the value, the shorter the DP falling transition time.

Default: 4'b0000

J DMP3:0RW

DM Full speed rising time select.

The larger the value, the shorter the DP rising transition time.

Default: 4'b0000



149.7 CONFIG7 (cfg7)
Address: 0x9C004A9C

Reset: 0x0000 008A


Field NameBitAccessDescription
Reserved31:8RORESERVED
J EN INR7RWInternal Rext function enable
0x0 : disable
0x1 : enable(default)
J R TRIM6:5RWLoop filter R trim table
{R TRIM1,R TRIM0}
0x0 : 80K
0x1 : 18K
0x2 : 16K
0x3 : 14K
J DISC

4:0

RW

control disconnect voltage(16.5mV/step)

0x00 : value 405mv.

0x0a : value 570mv(default).

0x1e : 900mv.

0x1f : Disable Disconnection



149.8 CONFIG8 (cfg8)

Address: 0x9C004AA0
Reset: 0x0000 0000


Field Name

Bit

Access

Description

Reserved

31:8

RO

RESERVED

J FS TX J DELAY

7:6

RW

Full speed DP delay cycle
0x0 : No delay(default).
0x1 : Delay 1 clock.
0x2 : Delay 2 clock.
0x3 : Delay 2 clock.

J FS TX K DELAY

5:4

RW

Full speed DM delay cycle
0x0 : No delay(default).
0x1 : Delay 1 clock.
0x2 : Delay 2 clock.
0x3 : Delay 2 clock.

J LS TX J DELAY

3:2

RW

Low speed DP delay cycle
0x0 : No delay(default).
0x1 : Delay 1 clock.
0x2 : Delay 2 clock.
0x3 : Delay 2 clock.

J LS TX K DELAY

1:0

RW

Low speed DM delay cycle
0x0 : No delay(default).
0x1 : Delay 1 clock.
0x2 : Delay 2 clock.
0x3 : Delay 2 clock.



149.9 CONFIG9 (cfg9)
Address: 0x9C004AA4
Reset: 0x0000 0006


Field NameBitAccessDescription
Reserved31:5RORESERVED
J FL FORCE FS4RW

Enable Config device error state

0 : enable error state(default)
1 : disable error state

J FL DP PILLUP3RW

Config device DP or MP resister pullup

0 : Full-low speed DP pull up(default)
1 : Full-low speed DM pull up

J FL SAMPLE SEL2RW

Enable Full-low speed rx linestat sample circuit

0 : disable Full-low speed rx linestat sample circuit
1 : enable Full-low speed rx linestat sample circuit(default)

J DIS FSM WAIT4MS EN1RWDisable HOSTDISC error state
0 : enable error state
1 : disable error state(default)
J FS ONLY0RWDisable UPHY AFE Low speed circuit at Low speed
0 : Low speed circuit use in Low speed(default)
1 : Full speed circuit usb in Low speed



149.10 CONFIG10 (cfg10)
Address: 0x9C004AA8
Reset: 0x0000 0000 


Field NameBitAccessDescription
Reserved31:8RORESERVED
NA7ROHigh speed disconnect signal with filter.
0 : disconnect is not happened(default)
1 : disconnect is happened

J HSDISC LPFILTER

6:4

RW

High speed disconnect filter number
0x0 : 0 time(default).
0x1 : 1 time.
0x2 : 2 time.
0x3 : 3 time.
0x4 : 4 time.
0x5 : 5 time.
0x6 : 6 time.
0x7 : 7 time.

J ALDISC OFF

3

RW

Host disconnect force 0
0 : disable force Host disconnect signal(default).
1 : enable force Host disconnect signal 0.

J ALDISC ON

2

RW

Host disconnect force 1
0 : disable Host disconnect signal(default)
1 : enable force Host disconnect signal 1

J HSDISC OFF

1

RW

High speed disconnect force 0
0 : disable high speed disconnect signal(default).
1 : enable force Host disconnect signal 0.

J HSDISC ON

0

RW

High speed disconnect force 1
0 : disable high speed disconnect signal(default).
1 : enable force Host disconnect signal 1.



149.11 CONFIG11 (cfg11)
Address: 0x9C004AAC

Reset: 0x0000 0000 


Field NameBitAccessDescription
Reserved31:8RORESERVED
LINESTATE7:6ROLinestate signal without control
0x0 : SE0 state(default).
0x1 : J state.
0x2 : K state.
0x3 : SE1 state.
Reserved5:3RORESERVED
J LINE EN2RWForce Linestate signal
0 : disable force linestate(default).
1 : force linestate.
J LINE DATA

1:0

RW

Force Linestate signal value

0x0 : SE0 state(default).

0x1 : J state.

0x2 : K state.

0x3 : SE1 state.



149.12 CONFIG12 (cfg12)
Address: 0x9C004AB0
Reset: 0x0000 0007


Field NameBitAccessDescription
Reserved31:0ROReserved for Industrial Debug Purpose



149.13 CONFIG13 (cfg13)

Address: 0x9C004AB4

Reset: 0x0000 0000


Field Name

Bit

Access

Description

DEBUG_INT

31:0

RU

Reserved for Industrial Debug Purpose



149.14 CONFIG14 (cfg14)
Address: 0x9C004AB8
Reset: 0x0000 0011


Field NameBitAccessDescription
Reserved31:5RORESERVED

PHY R CONFIG

4

RW

UPHY resume config mode
0 : disable resume send se0.
1 : enable resume send se0(default).

FS/LS RX DCP

3:2

RW

FS/LS RX data capture point
0x0 : original midpoint(default).
0x1 : original midpoint+10%.
0x2 : original midpoint-10%.
0x3 : NA

FS/LS RX SCP

1:0

RW

FS/LS RX SYNC capture point
0x0 : detect sync use 2 data bit.
0x1 : detect sync use 4 data bit(default).
0x2 : detect sync use 6 data bit.
0x3 : NA



149.15 CONFIG15 (cfg15)
Address: 0x9C004ABC

Reset: 0x0000 0000 


Field NameBitAccessDescription
Reserved31:2RORESERVED
HS DIS DG FLT1:0RWHigh speed disconnect de-glitch filter
0x0 : no de-glitch(default).
0x1 : 1 time de-glitch.
0x2 : 2 time de-glitch.
0x3 : NA



149.16 CONFIG16 (cfg16)
Address: 0x9C004AC0
Reset: 0x0000 0000  


Field NameBitAccessDescription
Reserved31:8RORESERVED

J FORCE VDM SRC

7

RW

FORCE DM voltage.
0 : disable force voltage at DM(default)
1 : force voltage at DM

J TBCWAIT[1:0]

6:5

RW

Battery charger disconnect to rework time.
REWORK TIME
0x0 : 1.1ms(default)
0x1 : 3.2ms
0x2 : 5.4ms
0x3 : 8.2ms

J TVDM SRC DIS[1:0]

4:3

RW

J Battery charger polling DP high to send dm voltage time.
Counter DP Polling Time
0x0 : 1.6ms(default)
0x1 : 3.8ms
0x2 : 6.5ms
0x3 : 8.2ms

J TVDM SRC EN[1:0]

2:1

RW

Battery charger polling DP low to disable dm voltage time.
Counter DP Polling Time
0x0 : 1.6ms(default)
0x1 : 3.8ms
0x2 : 6.5ms
0x3 : 8.2ms

J BC ENABLE

0

RW

Battery Charger CDP Function Enable.
0 : disable battery charger CDP(default)
1 : enable battery charger CDP



149.17 CONFIG17 (cfg17)
Address: 0x9C004AC4
Reset: 0x0000 0092


Field NameBitAccessDescription
Reserved31:8RORESERVED

IBG TRIM0[2:0]

7:5

RW

Current of current source in CDP mode.
{IBG TRIM1[1:0],IBG TRIM0[2:0]}

0x0f : TTNVNT (default) I=100uA

0x12 : FFHVLT

0x0a : FFHVHT

0x17 : SSHVLT

0x0c : SSLVHT

0x17 : SSLVLT

J VDATREF TRIM[3:0]

4:1

RW

Reference voltage of comparator in CDP mode.

VDATREF TRIM[3:0]

0x1 : 250mv

0x2 : 300mv

0x4 : 350mv

0x8 : 400mv

0x9 : default

J EN DCP

0

RW

Battery Charger DCP Function Enable.

0 : disable DCP(default)

1 : enable DCP



149.18 CONFIG18 (cfg18)
Address: 0x9C004AC8
Reset: 0x0000 0010


Field NameBitAccessDescription
Reserved31:8RORESERVED
BC DETECT STATUS7RWIndicate Battery Charge handshake status
0:BC handshake done(default),
1:BC handshake is in progress.
VDMSRC TRIM[4:0]6:2RWDm source voltage.
0x01 : 500mv
0x02 : 550mv
0x04 : 600mv(default)
0x08 : 650mv
0x10 : 700mv
IBG TRIM1[1:0]

1:0

RW

Current of current source in CDP mode.
{IBG TRIM1[1:0],IBG TRIM0[2:0]}

0x0f : TTNVNT (default) I=100uA

0x12 : FFHVLT

0x0a : FFHVHT

0x17 : SSHVLT

0x0c : SSLVHT

0x17 : SSLVLT


149.19 CONFIG19 (cfg19)

Address: 0x9C004ACC

Reset: 0x0000 0000


Field Name

Bit

Access

Description

Reserved

31:1

RO

RESERVED

EN HSRXACTIVE INT

0

RW

Enable UPHY Interrupt.
0 : disable UPHY Interrupt(default)
1 : Enable UPHY Interrupt

 

149.20 CONFIG20 (cfg20)
Address: 0x9C004AD0
Reset: 0x0000 0009


Field NameBitAccessDescription
Reserved31:8RORESERVED

Reserved

7

RW

RESERVED

Reserved

6

RW

RESERVED

NA

5:0

RW

NA

J AC2 0 B

5:3

RW

OTG Discharge Current Option.

0x0: 5uA

0x1: 10uA

0x2: 15uA

0x3: 20uA

0x4: 30uA (default)

0x5: 40uA

0x6: 50uA

0x7: 60uA

J AC2 0

2:0

RW

OTG Charge Current Option.

0x0: 5uA

0x1: 10uA

0x2: 15uA

0x3: 20uA

0x4: 30uA (default)

0x5: 40uA

0x6: 50uA

0x7: 60uA



149.21 CONFIG21 (cfg21)

Address: 0x9C004AD4
Reset: 0x0000 0001


Field Name

Bit

Access

Description

Reserved

31:8

RO

RESERVED

BC DETECT STS

7

RO

Battery Charge is in detect progress.

BC PRTBL STS

6

RO

Battery Charge successful detect PRTBL STS.

BC VDMSRC STS

5

RO

Battery Charge successful send VDM SRC.

BC DISC CNT

4:3

RO

Battery Charge detect disconnect counter.

BC SUCC CNT

2:1

RO

Battery Charge handshake successful counter.

J BC SUSPEND EN

0

RW

Enable Battery Charge handshake while PHY in SUSPEND MODE.
0 : Disable
1 : Enable(default)



149.22 CONFIG22 (cfg22)
Address: 0x9C004AD8
Reset:  0x0000 0077



Field Name

Bit

Access

Description

Reserved

31:8

RO

RESERVED

DCP2P7V

7:4

RW

Battery Charge DCP 2.7V control to APHY

DCP 1.2V mode dm source voltage trimming:

triming step=25mV

0x0: 1.025V

0x3: 1.1V

0x7: 1.2V

0xb: 1.3V

0xe: 1.4V

DCP1P2V

3:0

RW

Battery Charge DCP 1.2V control to APHY

DCP 2.7V mode dm source voltage trimming:

triming step=25mV

0x0: 2.525V

0x3: 2.6V

0x7: 2.7V

0xb: 2.8V

0xe: 2.9V



149.23 CONFIG23 (cfg23)
Address: 0x9C004ADC

Reset: 0x0000 0018


Field NameBitAccessDescription

Reserved

31:8

RO

RESERVED

RFU

7:6

RW

Reserved for future use

PROB

5:3

RW

APHY Probe control

0x0: 597.5mV

0x1: 617.5mV

0x2: 636.5mV

0x3: 656.5mV (default)

0x4: 675.5mV

0x5: 695.5mV

0x6: 714.5mV

0x7: 734.5mV

R TEST TIEH

2

RW

R TEST Tie High control to APHY

0: disable (default)

1: USB_R_TEST=AVDDC33

EN DCP2P7V

1

RW

Enable 2.7V DCP mode

0: disable 2.7V DCP mode (default)

1: enable 2.7V DCP mode 

EN DCP1P2V

0

RW

Enable 1.2V DCP mode

0: disable 1.2V DCP mode (default)

1: enable 1.2V DCP mode 


149.24 CONFIG24 (cfg24)
Address: 0x9C004AE0
Reset: 0x0000 0001


Field NameBitAccessDescription
Reserved31:8RORESERVED
BC AUTO RST7RWBattery Charge auto re-start enable
1'b0: Disable auto re-start.
1'b1: Enable auto re-start(Default)
TBC AUTO RST6:0RW

Battery Charge auto re-start timer

When counter equal to J_TBC_AUTO_RST, internal FSM timeout.

Real time is 606ms*J_TBC_AUTO_RST



149.25 CONFIG25 (cfg25)
Address: 0x9C004AE4
Reset: 0x0000 0004


Field NameBitAccessDescription
Reserved31:8RORESERVED
RFU7:3RWReserved for future use
SQ CT2:0RW

RX Squelch level control to APHY

0x0: 67.8mV

0x1: 84.5mV

0x2: 101.2mV

0x3: 118.1mV

0x4: 135.0mV (default)

0x5: 152.1mV

0x6: 169.2mV

0x7: 186.6mV



USB Controller System 0 (USBC0)
Group 0 USB Host Control  (UHC)

0.0 USB Host Version (UHVERSION)
Address: 0x9C102000
Reset: 0xC2120101


Field NameBitAccessDescription
UHVERSION31:0ROUSB Host Hardware Version
Read as '0xC2120101'



0.4 USB Power Control and Status (UHPOWERCS PORT)
Address: 0x9C102010
Reset: 0x00070000


Field NameBitAccessDescription

reserved 

31:19

RO

RESERVED
Read as '0'

UPHY SUSPENDM

18

RO

UPHY Suspend Signal
Current suspend signal input signal for controller.
1: Normal function. (default)
0: suspend state.

UPHY PARTIALM

17

RO

UPHY Partial Signal
Current partial signal input signal for controller.
1: Free run clock when suspend. (default)
0: Stop clock when suspend

USB CLK EN

16

RO

USB Clock Enable
This bit is set when received two USB clock domain clock, and will only be cleared when hardware reset

reserved

15:12

RO

RESERVED
Read as '0'

UPHY PAR EN

11

RW

UPHY Partial Enable
This bit is only valid when bit9 of this register is set.
1: Force Partial
0: force not partial (default)

UPHY SUSP EN

10

RW

UPHY Suspend Enable
This bit is only valid when bit8 of this register is set.
1: Force suspend
0: force not suspend (default)

UPHY PAR CTRL

9

RW

UPHY Partial Control
1: Force partial control enable
0: partial controlled by host controller (default)
When this bit is set controller output partial signal to PHY
is controlled by bit11 of this register

UPHY SUSP CTRL

8

RW

UPHY Suspend Control
1: Force suspend control enable
0: Suspend controlled by host controller (default)
When this bit is set controller output suspend signal to
PHY is controller by bit10 of this register

reserved

7:2

RO

RESERVED
Read as '0'

USBCLK SEL

1

RW

USB Clock Domain Clock Select
0: PHY 30MHz Clock(default)
1: Slow Clock
The controller will toggle this bit based on the current functional state. Driver needn't change this bit in normal case.

reserved

0

RO

RESERVED
Read as '0'



Group 1 USB Host OHCI Controller

1.0 OHCI HcRevision Register (UHO HcRevision)
Address: 0x9C102080
Reset: 0x00000010


Field Name

Bit

Access

Description

Reserved

31:8

RO

Reserved
Read as '0'

REV

7:0

RO

OHCI Revision
Read as '10', version 1.0



1.1 OHCI HcControl Register (UHO HcControl)
Address: 0x9C102084
Reset: 0x00000000


Field NameBitAccessDescription
Reserved31:11ROReserved
RWE10RORemoteWakeupEnable
This bit is used by HCD to enable or disable the remote wakeup signaling upon the detection of upstream resume. read as '0'
RWC9RORemoteWakeupConnected
This bit indicates whether HC supports remote wakeup signaling, read as '0'
IR8RWInterruptRouting
Not support.
HCFS7:6RWHostControllerFunctionalState for USB
0x0 : USBRESET (default)
0x1 : USBRESUME
0x2 : USBOPERATIONAL
0x3 : USBSUSPEND
BLE5RWBulkListEnable
Enable or disable the processing of the Bulk list in the next
frame. Default disabled

CLE

4

RW

ControlListEnable
Enable or disable the processing of the Control list in the next frame. Default disabled

IE

3

RW

IsochronousEnable
Enable or disable the processing the Isochronous EDs of the periodic list in the next frame. Default disabled

PLE

2

RW

PeriodicListEnable
Enable or disable the processing of the periodic list in the next frame. Default disabled

CBSR

1:0

RW

ControlBulkServiceRatio
Specifies the service ratio between Control and Bulk EDs
0x0: 1:1 (default)
0x1: 2:1
0x2: 3:1
0x3: 4:1



1.2 OHCI HcCommandStatus Register (UHO HcCommandStatus)
Address: 0x9C102088
Reset: 0x00000000


Field NameBitAccessDescription
Reserved31:18ROReserved
SOC17:16RO

SchedulingOverrunCount
Incremented on each scheduling overrun error and initial- ized to 00b and wraps around at 11b.

Used by HCD to monitor any persistent scheduling problems.

Reserved15:4ROReserved
OCR3ROOwnershipChangeRequest
Not support
BLF2RWBulkListFilled
Indicate whether there are any TDs on the Bulk list.
1: There is TDs on the Bulk list.
0: There is no TDs on the Bulk list (default)
CLF1RWControlListFilled
Indicate whether there are any TDs on the Control list.
1: There is TDs on the Control list.
0: There is no TDs on the Control list (default
HCR0otherHostControllerReset
Write 1, host Controller software reset, then clear this field by itself.



1.3 OHCI HcInterruptStatus Register (UHO HcInterruptStatus)
Address: 0x9C10208C

Reset: 0x00000000

Field Name

Bit

Access

Description

Reserved

31

RO

Reserved
Read as '0'

OC

30

RO

OwnershipChange
Not support

Reserved

29:7

RO

Reserved
Read as '0'

RHSC

6

RWC

RootHubStatusChange
Content of HcRhStatus or the content of any of HcRhPort- Status[NumberofDownstreamPort] change status bit

FNO

5

RWC

FrameNumberOverflow
Frame number overflow status bit

UE

4

RWC

UnrecoverableError
Un-recoverable error, host will set this bit when ITD offset is wrong

RD

3

RWC

ResumeDetected
Resume signaling detected status bit.

SF

2

RWC

StartofFrame
Each start of a frame status bit

WDH

1

RWC

WritebackDoneHead
HC has written HcDoneHead to HccaDoneHead status bit.

SO

0

RWC

SchedulingOverrun
USB schedule for the current Frame overruns status bit.



1.4 OHCI HcInterruptEnable Register (UHO HcInterruptEnable)
Address: 0x9C102090
Reset: 0x00000000


Field Name

Bit

Access

Description

MIE

31

Other

MasterInterruptEnable
Write 0: Ignore
Write 1: Enable interrupt generation due to events speci- fied in the other bits of this register.

OC

30

RO

OwnershipChange
Not support

Reserved

29:7

RO

Reserved
Read as '0'

RHSC

6

Other

RootHubStatusChange
Write 0: Ignore
Write 1: Enable interrupt generation due to Root Hub Sta- tus Change.

FNO

5

Other

FrameNumberOverflow
Write 0: Ignore
Write 1: Enable interrupt generation due to Frame Num- ber Overflow.

UE

4

Other

UnrecoverableError
Write 0: Ignore
Write 1: Enable interrupt generation due to unrecoverable error.

RD

3

Other

ResumeDetected
Write 0: Ignore
Write 1: Enable interrupt generation due to Resume De- tect.

SF

2

Other

StartofFrame
Write 0: Ignore
Write 1: Enable interrupt generation due to Start of Frame.

WDH

1

Other

WritebackDoneHead
Write 0: Ignore
Write 1: Enable interrupt generation due to HcDoneHead
Writeback.

SO

0

Other

SchedulingOverrun
Write 0: Ignore
Write 1: Enable interrupt generation due to Scheduling
Overrun.



1.5 OHCI HcInterruptDisable Register (UHO HcInterruptDisable)
Address: 0x9C102094
Reset: 0x00000000


Field Name

Bit

Access

Description

MIE

31

Other

MasterInterruptEnable
Write 0: Ignore
Write 1: Disable interrupt generation due to events speci- fied in the other bits of this register.

OC

30

RO

OwnershipChange
Not support

Reserved

29:7

RO

Reserved
Read as '0'