30. Serial Peripheral Interface (SPI)

30.1 Introduction

Serial Peripheral Interface (SPI) is a 4 wire serial interface bus that is commonly used for data communication between CPU and small peripherals such as portable device, sensors, and SD cards. The registers space locate to address 0x9C002D80~0x9C002E7F and 0x9C00F480~0x9C00F87F. The SPI is a synchronous-based full-duplex master-slave interface. Data from the master or slave is synchronized on the rising or falling edge of the clock. Both master and slave can transfer data simultaneously. SP7021 provides 4 sets of SPI master and 4 sets of SPI slave. They can be assigned to output to any of multiplex pins. The features are shown as below.

• SPI buffer depth FIFO 8 of RX and TX registers

• Each set with independent TX/RX DMA function

• SPI output clock frequency configuration

• SPI interface configuration

The following descriptions are based on SPI0. The other SPI blocks have the same structure and features.

30.2 Function Diagram

A generalized function diagram of SPI Master Full Duplex Function Block is shown in Figure 30-1.

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Figure 30-1 SPI Master Full Duplex Function Block

• SPI MISO: Master In/Slave Out data. In the general case, this pin is used to transmit data in slave mode and receive data in the master mode.

• SPI MOSI: Master Out/Slave In data. In the general case, this pin is used to transmit data in master mode and receive data in the slave mode.

• SPI CLK: Serial clock output pin for SPI master and input pin for SPI slave.

• SPI SS: Chip select pin. Controlled by master. The slave will only react to the master's operation command if the /SS signal is low.

• SPI MASTER FD: SPI master full duplex interface.

• RXFIFO: SPI_RXFIFO supports 16-byte received data FIFO. Users can read data from RXFIFO through accessing Group91.9~12 (rx_data3_2_1_0~ rx_data15_14_13_12) registers and check FIFO status through read Group91.14 (spi_status) register bit6~2.

• TXFIFO: SPI_TXFIFO supports 16-byte is used to store the data written by user through Group91.1~4 (tx_data3_2_1_0~ tx_data15_14_13_12) registers and check FIFO status through read Group91.14 (spi_status) register bit6~2.

• SPI MASTER REG: The SPI MASTER control registers bus.

SPI with DMA function blocks are shown in Figure 30-2, Figure 30-3 & Figure 30-4.

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Figure 30-2 SPI DMA Function Block

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Figure 30-3 SPI Master DMA Function Block

• MST_CORE: Receive or transmit data from or to SPI_SLAVE

• DMA_CTRL_W: Receive DATA from MST_CORE and produce WDATA_REQ with transmit 4-byte data to DMA_LINK_W

• DMA_CTRL_R: Transmit DATA to MST_CORE and produce RDATA_REQ with receive 4-byte data from DMA_LINK_R

• DMA_LINK_R/W: Communicate with DMA_CTRL via proprietary System Bus (SBUS) protocol

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Figure 30-4 SPI Slave DMA Function Block

• SLV_CORE: Receive or transmit from or to SPI_MASTER

• DMA_CTRL_W/R, DMA_LINK_W/R: Function same as above description

• ADDR_BUF: Indicate which RX_DATA is being transmitted through SPI protocol

• CORE_CurrentState[4]: DMA state or not

30.3 SPI Timing Chart

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Figure 30-5 SPI Timing Chart

According slave device work timing, the SP7021 SPI master have 4 kinds work mode. User can select SCK polarity and latch data edge to get expected work mode. The register Group91.17 (spi_ctrl_clk_sel) bit3 can be select SCK polarity, "CPOL=0" is SCK stay in low level when stop work, "CPOL=1" is stay in high level. The register Group91.17 (spi_ctrl_clk_sel) bit6 can be select latch data edge during write, "CPHA=0" is latch data in SCK rising edge, "CPHA=1" is latch data in SCK falling edge. The register Group91.17 (spi_ctrl_clk_sel) bit5 can be select latch data edge during read.

30.4 Baud Rate Generation

The SPI output clock frequency can be configured by below formula. SYSCLK/(2(CLK_SEL+1))*CLK_SEL can be selected in register Group91.17 (spi_ctrl_clk_sel) bit29~16.If system clock is 304MHz, the CLK_SEL with the data transfer rate excludes 12-bit address relationship shows as below.

30.5 Addition Delay In Read Operation

There has an addition delay R_DLY can be set in read action. The range is 0~1.5*SPI_CLK_CYCLE. R_DLY can be set in bit[31:30] of Group91.17 spi_ctrl_clt_sel register.

30.6 Address Bit Number

The transfer address bit number can be set as 8/12/16/20bits by ADDR_BIT_NUM which is bit[8:7] of group19.17 spi_ctrl_clt_sel register.

30.7 Slave Enable Polarity

The slave enable pin polarity can be selected by EN_POLARITY. Default set 0 as low active. The EN_POLARITY locate in bit4 of Group91.17 spi_ctrl_clt_sel register.

30.8 RW Position

Chip default set 0 to RW_POSITION, it means Addr[0] is R/W bit, otherwise Addr[7] is R/W bit. The RW_POSITION locate in bit2 of Group91.17 spi_ctrl_clt_sel register.

30.9 LSB Select

Chip default set 0 to LSB_SELECT, it means that data begin at bit0, otherwise at bit7. The LSB_SELECT locate in bit1 of Group91.17 spi_ctrl_clt_sel register.

30.10 SPI Start

SPI master begin write or read action when SPI_START set to 1. It will return to 0 automatically when SPI transmission finish. The SPI_START locate in bit0 of Group91.17 spi_ctrl_clt_sel register.

30.11 Communication between one master and one slave

The SPI support full-duplex communication. In this configuration, the shift registers of master and slave are linked using two unidirectional lines between the MOSI and the MISO pins. During SPI communication, data is shifted synchronously on the SCK clock edges provided by the master. The master transmits the data to be sent to the slave via the MOSI line and receives data from the slave via the MISO line. When the data frame transfer is complete the information between the master and slave is exchanged. Figure 30-6 shows one master and one slave device connected status.

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Figure 30-6 One master and one slave communication

30.12 Multi-slave communication

In a configuration with two or more independent slaves, the master uses GPIO pins to manage the chip select lines for each slave (refer to Figure 30-7). The master must select one of the slaves individually by pulling low the GPIO connected to the slave SS input. When this is done, a standard master and dedicated slave communication is established.

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Figure 30-7 Master and two independent slaves

30.13 SPI Operation Mode

30.13.1 SPI-MASTER Write and Read Trigger Flow

• Setup transfer setting (transfer frequency, data byte……………)

• Set data count and transfer data

• Clear SPI status and set interrupt mask

• Set write mode or read mode

• Enable interrupt

• Start transfer

• Wait timer-out or transfer finish

• Reset SPI-MASTER

30.13.2 SPI DMA Read Mode Flow

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Figure 30-8 SPI DMA Read Mode Flow

• CPU moves data to DRAM in IC1

• Set up slave START via RGST bus

• Issue interrupt to master

• Receive interrupt from slave

• Set up master START via RGST bus

• SPI transmission

• When finished moving data to DRAM, DMA controller issues interrupt to CPU in IC2

• CPU read data from DRAM

30.13.3 SPI DMA Write Mode Flow

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Figure 30-9 SPI DMA Write Mode Flow

• CPU moves data to DRAM in IC2

• Set up master DMA preparing data via RGST bus

• DMA data ready and issue interrupt to master

• Master receives interrupt from DMA

• Set up master START via RGST bus

• SPI transmission

• When finished moving data to DRAM, DMA controller issues interrupt to CPU in IC1

• CPU read data from DRAM

30.14 SPI Interrupts

TX and RX FIFO have full and empty interrupt that can be used in burst mode for full duplex master. When tx fifo empty and rx fifo full interrupt received and transfer have not completed, IRQ handler should move data to or fetch data from tx/rx fifo to continue transfer until it complete.Finish int means SPI Transmission done for full duplex master. IRQ handler can handle the data transferred and start a new transmission for full duplex master.SPI_MASTER_RISC_INT (Group91.19 bit7) is generated from SPI_MST_INT_I and MST_DMA_INT. Set INT_EDGE (Group91.19 bit5) register or INT_BYPASS (Group91.19 bit3) register to configure interrupt. SPI_MST_INT_I Interrupt is issued when incoming SPI interrupt to SPI MASTER. MST_DMA_INT interrupt is issued when DMA data is ready (MST_DMA_DATA_RDY). IRQ handler will immediately set up master START via RGST bus and start SPI transmission.

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Figure 30-10 SPI MASTER RISC INT

SPI_ SLAVE_INT (Group92.17 bit9) interrupt is issued when SPI slave is not busy. IRQ handler can get data transferred and start a new transmission.

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Figure 30-11 SPI SLAVE INT

SPI_DMA_W_INT (Group91.20 bit8) interrupt is issued when SPI DMA data transfer is done. IRQ handler can read data from DRAM.

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Figure 30-12 SPI DMA W INT

30.15 Registers Map

30.15.1  Register Memory Map

SPI Register Memory Map

Table 30-1 SPI Register Memory Map

All SPIs' registers have the same offset (address - base address)  in corresponding SPI register group. Only SPI0 Master and Slave registers are described in following register description, for other SPIs (SPI1, 2, 3) please refer to SPI0 description for more detail.

30.15.2  Registers Description

SPI Register Description

RGST Table Group 91 SPI MASTER 0

91.0 Transmit register1 (tx data addr)

Address: 0x9C002D80
Reset: 0x0000 0000

91.1 Transmit register2 (tx data3 2 1 0)
Address: 0x9C002D84 
Reset: 0x0000 0000

91.2 Transmit register3 (tx data7 6 5 4)

Address: 0x9C002D88
Reset: 0x0000 0000

91.3 Transmit register4 (tx data11 10 9 8)
Address: 0x9C002D8C
Reset: 0x0000 0000

91.4 Transmit register5 (tx data15 14 13 12)Address: 0x9C002D90Reset: 0x0000 0000