13. Universal Asynchronous Receiver Transmitter (UART)

13.1 Universal Asynchronous Receiver Transmitter (UART)

13.1.1 Introduction

The UART is a Universal Asynchronous Receiver/Transmitter, the interface is EIA RS-232C DB-9 industry standard. The registers space locate to address 0x9C000800~0x9C0009FF and 0x9C008780~0x9C0087FF. The UART block is used to serially receive and transmit data to a peripheral device. It contains registers to control the character length, baud rate, parity check and interrupt generation. It is also equipped with FIFO controls to buffer the receive and transmit data, and to enable/disable the FIFOs. Both receive and transmit FIFO's depth are 128byte. There are UART0~4 that supported in SP7021, the features list as below.

• Support Full-duplex communication.

• Support data packet length configurable.

• Support stop bit number configurable.

• Support force break condition.

• Support baud rate configurable.

• Support error detection and report.

• Support RXD Noise Rejection Vote configurable.

The following descriptions are based on UART0. The other UART blocks have the same structure and features.

13.1.2 Function Diagram

A generalized function diagram of UART is shown in Figure 13-1.

Figure 13-1 UART Functional Blocks

• UART_DATA: Used to let the CPU read and write to the FIFO through RGST.

• RXFIFO: UART_RXFIFO supports 128 byte receive data FIFOs and FIFO status, such as not empty. Users can read data from RXFIFO through accessing Group18.0 uart0_data register and check FIFO status through read Group18.1 uart0_lsr register bit1.

• TXFIFO: UART TXFIFO supports 128 byte is used to store the data written by user through Group18.0 uart0_data register, and also provides FULL and empty status and empty interrupt to user through Group18.1 uart0_lsr register, which is convenient for TXFIFO operation.

• RSR_RXST: UART's receiver state machine include the following state: IDLE_ST, START_ST, DATA0_ST, DATA1_ST, DATA2_ST, DATA3_ST, DATA4_ST, DATA5_ST, DATA6_ST, DATA7_ST, PARITY_ST, STOP0_ST, FAIL_ST. UART transform serial UA_RXD data into parallel through RSR register under the control of RXST. Then it will write the parallel RSR data into RXFIFO.

• TSR_TXST: UART's transmit state machine include the following state: IDLE_ST, START_ST, DATA0_ST, DATA1_ST, DATA2_ST, DATA3_ST, DATA4_ST, DATA5_ST, DATA6_ST, DATA7_ST, PARITY_ST, STOP0_ST, STOP1_ST. Data is transferred from TXFIFO to TSR register. TSR can transform the parallel data into serial data under the control of TXST.

• Noise Reduce: For UA_RXD, there are two levels of noise reduction. The first one is 3 times sampled with SYSCLK, only three consecutive ones will change their value to one, and for their value to be zero, three consecutive zeros must be received. This first level of noise reduction can't be disabled. The second level of noise reduction is the majority vote logic; by default this second level of noise reduction is disabled. Software can set it to 3VOTE, 5VOTE or 7VOTE. If the VOTE_SEL is set to 3VOTE, the majority for three consecutive RXD values (sampling clock is 16 x baud rate) are selected as the received RXD value. If it is set to 5VOTE, the majority for five consecutive RXD values (sampling clock is 16 x baud rate) are selected as the received RXD value. If it is set to 7VOTE, the majority for seven consecutive RXD values (sampling clock is 16 x baud rate) are selected as the received RXD value. User can control sample vote through (Group18.3 uart0_lcr[7:6]).

• Flow Control: Flow Control Block is composed on AUTO_CTS mode and AUTO_RTS mode. They can be enabled and disabled independently by programming bit6 and bit5 of Modem Control Register (Group18.4 uart0_mcr). If the AUTO_CTS mode is enabled, the TX function is disabled as long as the UA_CTS_B is high (inactive). Transmission will resume when the CTS pin return to logic 0. If the AUTO_RTS mode is enabled, the UA_RTS_B goes high (inactive) when there is only one space left in the Rx FIFO, and it returns to low (active) when the data in the Rx FIFO is less than fifteen. The Flow Control Block work with Modem mode only and the flow controlled by hardware. In the Line mode, the data transaction is only through UA_TXD and UA_RXD.

13.1.3 Serial Data Format

The UART serial data format is shown in Figure 13-2. The data sampling chart is shown in Figure 13-3. 

Figure 13-2 Serial Data Format

Figure 13-3 Data Sampling Chart
The data length can be selected by programming the bit [1:0] in the Group18.3 uart0_lcr register for UART0.The number of stop bits can be selected by programming the bit [2] in the Group18.3 uart0_lcr register for UART0.The parity bit enable function can be selected by programming the bit [3] in the Group18.3 uart0_lcr register for UART0.The parity bit polarity can be selected by programming the bit [4] in the Group18.3 uart0_lcr register for UART0.

13.1.4 Baud Rate Generation

The baud rate for receiver and transmitter are both set to the same value as programed in the uart0_div_l and uart0_div_h registers for UART0. The divisor0_ext [3:0] is in the bit [15:12] of Group18.5 uart0_div_l register. The divisor [7:0] is in the bit [7:0] of Group18.5 uart0_div_l register. The divisor [15:8] is in the bit [7:0] of Group18.6 uart0_div_h register. The baud rate calculation formula is shown as below.

The SYSCLK can be changed fixed 27MHz by set CLK_BAUD to 1. The CLK_BAUD is bit0 of register Group18.11 uart0_clk_baud_sel.

• TXCLK Generation: When TXFIFO is not empty, UART will start data transfer. When TXST jumps into START_ST from IDLE, it will load data to TX_DIV_EXT from DIVISOR_EXT. TX_DIV_EXT will be change from the loaded value to 0, then load data from DIVISOR to TXCNT. (TXCNT will count from loaded data to 0, and then do the same countering for 15 times). Time duration of all the process is equal to baud rate time, which is programmed by the users. The TXCLK will pull up one cycle (a UART_CLK cycle) at this time. For the generation mechanism of TXCLK, please refer to the figure 13-4.

Figure 13-4 TXCLK Generation Mechanism

• RXCLK Generation: UART transform serial UA_RXD data into RXFIFO through RSR register under the control of RXST. When RXST jumps into START_ST from IDLE, it will write data to RX_DIV_EXT from DIVISOR_EXT. RX_DIV_EXT will be change from the loaded value to 0, then load data from DIVISOR to RXCNT. (RXCNT will count from loaded data to 0, and then do the same countering for 15 times). Time duration of all the process is equal to baud rate time, which is programmed by the users. The RXCLK will pull up one cycle (a UART_CLK cycle) at this time. For the generation mechanism of RXCLK, please refer to the figure 13-5.

Figure 13-5 RXCLK Generation Mechanism

• Error calculation for programmed baud rates at SYSTEMCLK=202MHz and oversampling by 16: Please refer to table 13-1

  Table 13-1 Error calculation with baud rate

Figure 13-6 Error calculation with baud rate

Please notice that Error rate should under 3% when programmed baud rate.

• Tolerance of the UART receiver to clock deviation

The UART receiver must match Fe₇ ≦9% ,Fe_p≦10%且Be ≦4.5% condition. Please refer to figure 13-7&13-8. Fe₇ is Frame error of the data bit7 (D7). Fe_p is Frame error of the STOP bit. Be is Bit error. Ts is the bit clock time difference between idea baud rate and slower baud rate. Tf is the bit clock time difference between idea baud rate and faster baud rate. Ti is idea baud rate bit clock time. Ideal means standard UART pulse. Slower means clock slower case UART pulse. Faster means clock faster case UART pulse.

• The Fe₇ & Fe_p calculation: T_i7 and T_ip is equal in the Ideal UART pulse case.

Figure 13-7 Frame error calculation

• The Be calculation: Bx include Start, Data and Stop bit.

Figure 13-8 Bit error calculation

13.1.5 Parity Control

The parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by set the PE bit to 1 in the bit3 of Group18.3 uart0_lcr register.

• Even parity: Even parity can be selected by set the PR bit to 1 in the bit4 of Group18.3 uart0_lcr register. The parity bit is calculated to obtain an even number of "1s" inside the frame and the parity bit. For example, data=00111111; 6 bits set  parity bit will be 0 if even parity is selected.

• Odd parity: Odd parity can be selected by set the PR bit to 0 in the bit4 of Group18.3 uart0_lcr register. The parity bit is calculated to obtain an odd number of "1s" inside the frame and the parity bit. For example, data=00111111; 6 bits set  parity bit will be 1 if odd parity is selected.

• Parity checking in reception: If the parity check fails, the PE flag is set in the bit2 of Group18.1 uart0_lsr register and an interrupt is generated if LSM is set to 1 in the bit6 of Group18.7 uart0_isc. An interrupt flag LS can be got in the bit2 of Group18.7 uart0_isc.

13.1.6 UART Interrupts

The UART interrupt events are connected to the same interrupt vector, please refer to figure 13-6. These events generate an interrupt if the corresponding "Enable Control Bit" is set. !worddavcc8ac9771c793b4db11c7e8d5897cc96.png|height=250,width=490!Figure 13-6 UART Interrupt Tree
The following descriptions are based on UART0.

• Modem Status IRQ: When modem status interrupt is enabled (Group18.7 uart0_isc[7]=1) and modem control signals TERI, DDCD, DCTS, DDSR (Group18.2 uart0_msr[7:4]) are set to 1, the modem status interrupt will occur. User can confirm the interrupt type through the register (Group18.7 uart0_isc[3] ). When read modem status register (Group18.2 uart0_msr[7:4]), modem status register will be cleared to 0, and modem status interrupt flag is cleared to 0 also.

• Line Status IRQ: Line status interrupt is enabled (Group18.7 uart0_isc[6]=1). If any condition of break condition (BC), frame error (FE), overrun (OE), parity error (PE) (Group18.1 uart0_lsr[5:2]) occurs in UART's controller, it will cause line status interrupt occur. The interrupt type can be confirmed by read the register (Group18.7 uart0_isc[2]). The interrupt caused by OE requires only read line status register, OE will be cleared to 0, and line status interrupt flag will be cleared to 0 too. The interrupt caused by PE, BC, and FE needs to read the uart0_data register, the next data PE, BC, and FE status reload to the current PE, BC, and FE status register. If there is no PE, BC, or FE error in the next data, PE, BC, and FE will be cleared, and the line status interrupt flag will be cleared also

• RXFIFO not empty IRQ: The size of the RXFIFO is 128 bytes. If the RX interrupt is enabled (Group18.7 uart0_isc[5]=1), the RXFIFO will immediately make UA_INT to 1 as long as there is data, so the CPU knows that a UART interrupt has occurred. The software determines the type of interrupt generated by querying Group18.7 uart0_isc[1], and the software reads the data in the FIFO through the uart0_data register. When RXFIFO is empty, the interrupt flag will be cleared to 0.

• TXFIFO empty IRQ: The size of the TXFIFO is 128 bytes. If the TX interrupt is enabled (Group18.7 uart0_isc[4]=1) and the TXFIFO is empty, the controller immediately sets UA_INT to 1, letting the CPU know that a UART interrupt has occurred. The software determines the type of interrupt generated by querying Group18.7 uart0_isc[0], and the software continues to write data to the FIFO through the uart0_data register. When TXFIFO is not empty, the interrupt flag will be cleared to 0.

13.2        UARTRX DMA (UADMA)

13.2.1        Introduction

UARTRX DMA (or named UADMA) which is used as a bridge for storing UART RX data in DRAM. The purpose is to improve CPU processing efficiency for slow peripherals. It can choose the UART0~UART4 by register setting.
There have two UADMA mechanisms that can serve each UART RX independently but can't serve the same UART at the same time.
The control registers memory map address locate at 0x9C008980-0x9C0089FF.

13.2.2       Function Diagram

UART RX circuit receives data from external device, than it issues an interrupt when the FIFO is almost full. Register bus provides the access interface for UART drive . A generalized function diagram of UADMA is shown in Figure 13-7.

Figure 13-7 UADMA Function Diagram

13.2.3        UADMA Interrupt Handler

An interrupt is issued when UART RX data out of timeout or DMA space less than threshold. Software needs to process interrupt and copy data from DMA space to UART buffer then clear status and set DMA_GO when FIFO almost Full happened.

Figure 13-8 UADMA Interrupt Tree

13.3        UARTTX DMA (HW_BUF_UA)

13.3.1        Introduction

UARTTX DMA (or named HW_BUF_UA) which is used as a bridge for transfer data from DRAM to UART TX port. The purpose is to improve CPU processing efficiency for slow peripherals. It can choose the UART0~UART4 by register setting.
HW_BUF_UA construct by GDMA(General DMA Function) and UART. It can transfer data automatically with no CPU control, instead by DMA_Controller. When data size larger than 64Byte or timeout happened, the data will be catch out automatically.
According to HW_BUF_UA status is empty or full, the controller will stop or start transfer data.
There have two UARTTX DMA mechanisms that can serve each UART TX independently but can't serve the same UART at the same time.
The HW_BUF_UA control registers memory map address locate at 0x9C008A00-0x9C008A7F.
The GDMA0 control registers memory map address locate at 0x9C008880-0x9C0088FF.
The GDMA1 control registers memory map address locate at 0x9C008900-0x9C00897F.

13.3.2       Function Diagram

The block diagram of UART TX circuit is shown in Figure 13-9.

Figure 13-9 UARTTX Block Diagram

DRAM is read by GDMA through NoC, while GDMA2UART is used for data transmission through the communication protocol between GDMA and UART.
UART to the outside is transmitted via UART protocol, through TXD/RXD.
When CPU write data to DRAM, it only need update WR_ADR, Control_GDMA will auto judge the data size larger than 64Byte or timeout happened and execute DMA action.

13.3.3      Data Control Flow

• When the CPU starts to throw the debug message to the DRAM, it will first read the RD_ADR (and FULL/EMPTY) of HW_BUF_UA to ensure that the current Buffer has enough space for writing.

• After step1 is completed, the CPU will update the WR_ADR of HW_BUF_UA and notify HW_BUF_UA where the current valid data is written to.

• Control GDMA will calculate whether the Buffer is greater than or equal to 64B, if so, start GDMA to read the DRAM; otherwise, continue to wait, if no new data is written before TIMEOUT, start GDMA directly.

• The register of HW_BUF_UA can set which UART to rd/wr, if GDMA0 is selected to UART3 for rd action, the data on DRAM will be transmitted to UART through GDMA.

• Interrupt part is GDMA internal Interrupt: THRESHOLD_INT, ERROR_INT, GDMA_DONE.

13.3.4        UARTTX DMA Interrupt Handler

DEBUG mode (DEBUG_ENABLE=1, GDMA_ENABLE=1)
Only TX path

1. When GDMA generates ERROR_INT, it will stop the action with the IP, and only complete the operation on the BUS (not let the BUS die).

2. After step1 is over, HW_BUF_UA will send ERROR_INT to UART. After UART receives it, in order to ensure that all the previous operation data is written out, it needs to wait until TXFIFO empty to send ERROR_INT to CPU.

3. CPU receives ERROR_INT and needs to perform SW_RESET action (TXFIFO_FLUSH) on UART, and then perform SW_RESET on GDMA through UART.

4. If ERROR_INT is caused by TIMEOUT, you need to adjust the TIMEROUT value or other actions through the CPU.

5. After all settings are completed, the CPU needs to check the cmd of REDO_CONTROLLER_DMA under HW_BUF_UA.

Normal mode (DEBUG_ENABLE=0, GDMA_ENABLE=1)
TX path

1. After the CPU sets UART_SELECT_RD and GDMA, etc., GDMA will start to read data from DRAM to UART.

2. The GDMA error interrupt that will be used has TIMEOUT_INT.

3. Error Interrupt flow is the same as debug mode, UART needs to ensure that all data has been transmitted.

4. But there is no need to download REDO_CONTROLLER_DMA, because the debug mode is no longer at this time, just reset the CPU.

RX path

1. After the CPU sets UART_SELECT_WR and GDMA, etc., GDMA will start to capture data and write into DRAM through UART.

2. The GDMA error interrupt that will be used has TIMEOUT_INT / WRITE_INT.

3. When an error interrupt occurs, GDMA will directly cut off the communication with the UART to ensure that the transmission on the BUS ends correctly, and then send an error interrupt to the UART.

4. At this time, the UART will immediately transmit the error interrupt to the CPU, and the CPU will perform SW_RESET on the UART, and then perform SW_RESET on the GDMA.

5. After GDMA SW_RESET_DONE, the CPU can start to set.

13.4 Registers Map

13.4.1  Register Memory Map

UART Register Memory Map

Table 13-2 UART Register Memory Map

All UARTs' registers have the same offset (address - base address) in corresponding UART register group. Only UART2 and UART DMA registers are described in following register description, for other UARTs (UART0, 1, 3, 4) please refer to UART2 description for more detail.

13.4

.2  Registers Description

UART Register Description
RGST Table Group 16 UART2

16.0 UART2 Data Port Register (uart2 data)

Address: 0x9C000800

Reset: 0x0000

16.1 UART2 Line Status Register (uart2 lsr)

Address:0x9C000804

Reset:0x0041

16.2 Modem Status Register (uart2 msr)
Address: 0x9C000808
Reset: 0x007f