11. Input Capture Module (ICM)
- edwin.chiu (Unlicensed)
- Michael Su (Unlicensed)
11.1 Introduction
The Input Capture Module (ICM) is used to capture a counter value from the ICM's internal counter based upon an event on an input pin. There are four ICM sub modules in the SP7021. The ICM's input source can come from external pins or internal test signal, the counter clock source can also come from external clocks or internal system clock. The ICM features are useful in applications that require frequency (time period) and pulse measurement. The ICM control registers locate at RGST table Group 81.0~31 which memory map in 0x9C002880~0x9C0028FF.
The detail ICM features of the sub module are as below.
- Input source selectable.
- The counter clock source selectable.
- One de-bounce filter
- Three EDGE detect modes and all of them can set event times that decide when to trigger interrupt.
- Report pulse width (high and low) for pulse measurement
- A FIFO buffer (depth is 16) which can record 16 times counter value. User can read from register and the FIFO counter will decrease one. If FIFO is full, the new counter value will be discarded..
Below description will focus on ICM0 , the ICM1/2/3 have the same structure and correspond registers.
11.2 Function Diagram
A generalized function diagram of ICM is shown in Figure 11-1.
Figure 11-1 ICM Function Blocks
- I_Mux_5T1: 4 external input signals and 1 internal test signal. Test signal generate from system clock and support to scale the period.
- I_DEBOUNCE_FILTER: Used to filter out noise.
- I_EDGE_EVENT: Three operating modes and all of them can be set event times that decide when to trigger interrupt.
- Rising Edge Detect Mode
- Falling Edge Detect Mode
- Edge Detect Mode
11.3 Input Source and Clock
There are 4 input pins and 1 test signal can be selected as input signal source by icm0_mux_sel in ICM0. The icm0_mux_sel is in bit[5:3] of RGST table Group 81.0 icm0_cfg0 register. The ICM0's count clock can be selected by icm0_clk_sel. 4 external clock come from input pins and others source are SYSCLK, 27MHz and 32KHz. The icm0_clk_sel is in bit[8:6] of RGST table Group 81.0 icm0_cfg0 register.
11.4 Input Capture Detect Mode
The input capture detect mode of ICM0 can be selected by icm0_ee_mode. The icm0_ee_mode is in bit[1:0] of RGST table Group 81.1 icm0_cfg1 register. Set icm0_ee_mode as 0 for Rising Edge Mode, set icm0_ee_mode as 1 for Falling Edge Mode and set icm0_ee_mode as 2 for Edge Detection Mode. The interrupt trigger timing is controlled by icm0_ee_times. If icm0_ee_times set 7, the interrupt will be triggered after 7 times edge event. The icm0_ee_ times is in bit[5:2] of RGST table Group 81.1 icm0_cfg1 register.
11.4.1 Rising Edge Mode
Figure 11-2 shows the icmx_ee_mode = 0 and icmx_ee_times = 0 or 1 case.
Figure 11-2 Rising Edge Mode Case1
Figure 11-3 shows the icmx_ee_mode = 0 and icmx_ee_times = 3 case.
Figure 11-3 Rising Edge Mode Case2
11.4.2 Falling Edge Mode
Figure 11-4 shows the icmx_ee_mode = 1 and icmx_ee_times = 0 or 1 case.
Figure 11-4 Falling Edge Mode Case1
Figure 11-5 shows the icmx_ee_mode = 1 and icmx_ee_times = 2 case.
Figure 11-5 Falling Edge Mode Case2
11.4.3 Edge Detection Mode
Figure 11-6 shows the icmx_ee_mode = 2 and icmx_ee_times = 0 or 1 case.
Figure 11-6 Edge Detection Mode Case1
Figure 11-7 shows the icmx_ee_mode = 2 and icmx_ee_times = 2 case.
Figure 11-7 Edge Detection Mode Case2
11.5 Interrupt Trigger Counter
The ICM0 interrupt trigger counter value control register is RGST table Group 81.4 icm0_cnt. This register will record the counter value when interrupt happened. This value is updated from FIFO, the FIFO depth is 16. Figure 11-8 shows the behavior of counter. When interrupt trigger at internal counter 9, the icm0_cnt will be updated to 9 immediately.
Figure 11-8 counter behavior
11.6 Debounce Filter
The ICM0 debounce filter is controled by icm0_df_times which is bit[8:6] of Group81.1 icm0_cfg1 register. Set the debounce times as 7, the input signals length under 7 clock will be filtered. Figure 11-9 shows the icm0_df_times=4 case. 
Figure 11-9 icm0_df_times=4 case
11.7 Count Pulse Width H and L
The ICM0 pulse width H and L count value will be recorded in Group 81.5 icm0_pulse_width_h and Group 81.6 icm0_pulse_width_l registers. Figure 11-10 shows the count pulse width H and L status.
Figure 11-10 Count Pulse Width H and L
11.8 Registers Map
11.8.1 Registers Memory Map
Address | Group No. | Register Name | Description |
|---|---|---|---|
0x9C002880 | G81.0 | icm0_cfg0 | ICM0 Config Register 0 |
0x9C002884 | G81.1 | icm0_cfg1 | ICM0 Config Register 1 |
0x9C002888 | G81.2 | icm0_cfg2 | ICM0 Internal Counter Scaler |
0x9C00288C | G81.3 | reserved | reserved |
0x9C002890 | G81.4 | icm0_cnt | ICM0 Interrupt Trigger Counter Value |
0x9C002894 | G81.5 | icm0_pulse_width_h | ICM0 Pulse Width H |
0x9C002898 | G81.6 | icm0_pulse_width_l | ICM0 Pulse Width L |
0x9C00289C | G81.7 | icm1_cfg0 | ICM1 Config Register 0 |
0x9C0028A0 | G81.8 | icm1_cfg1 | ICM1 Config Register 1 |
0x9C0028A4 | G81.9 | icm1_cfg2 | ICM1 Internal Counter Scaler |
0x9C0028A8 | G81.10 | reserved | reserved |
0x9C0028AC | G81.11 | icm1_cnt | ICM1 Interrupt Trigger Counter Value |
0x9C0028B0 | G81.12 | icm1_pulse_witdh_h | ICM1 Pulse Width H |
0x9C0028B4 | G81.13 | icm1_pulse_width_l | ICM1 Pulse Width L |
0x9C0028B8 | G81.14 | icm2_cfg0 | ICM2 Config Register 0 |
0x9C0028BC | G81.15 | icm2_cfg1 | ICM2 Config Register 1 |
0x9C0028C0 | G81.16 | icm2_cfg2 | ICM2 Internal Counter Scaler |
0x9C0028C4 | G81.17 | reserved | reserved |
0x9C0028C8 | G81.18 | icm2_cnt | ICM2 Interrupt Trigger Counter Value |
0x9C0028CC | G81.19 | icm2_pulse_witdh_h | ICM2 Pulse Width H |
0x9C0028D0 | G81.20 | icm2_pulse_width_l | ICM2 Pulse Width L |
0x9C0028D4 | G81.21 | icm3_cfg0 | ICM3 Config Register 0 |
0x9C0028D8 | G81.22 | icm3_cfg1 | ICM3 Config Register 1 |
0x9C0028DC | G81.23 | icm3_cfg2 | ICM3 Internal Counter Scaler |
0x9C0028E0 | G81.24 | reserved | reserved |
0x9C0028E4 | G81.25 | icm3_cnt | ICM3 Interrupt Trigger Counter Value |
0x9C0028E8 | G81.26 | icm3_pulse_witdh_h | ICM3 Pulse Width H |
0x9C0028EC | G81.27 | icm3_pulse_width_l | ICM3 Pulse Width L |
0x9C0028F0 | G81.28 | reserved | reserved |
0x9C0028F4 | G81.29 | reserved | reserved |
0x9C0028F8 | G81.30 | reserved | reserved |
0x9C0028FC | G81.31 | reserved | reserved |
11.8.2 Registers Description
RGST Table Group 81 ICM
81.0 ICM0 Config Register 0 (icm0 cfg0)
Address: 0x9C002880
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| Write Mask Bits | 31:16 | RW | Write Mask Bits Corresponding Mask Bits for Bit[15:0] Example: If user want to set bit0 = 1, than he should set bit16 to 1 (0x 0001) to enable bit0 functionality |
| Reserve | 15:9 | RO | RESERVED |
| icm0 clk sel | 8:6 | RW | ICM0 Clock Source Select |
| icm0 mux sel | 5:3 | RW | Select input signal source. |
| icm0 int clr | 2 | W1C | Clear the interrupt. Write 1 to clear interrupt, HW will recover this bit to 0 automatically. |
| Reserve | 1 | RW | RESERVED |
| icm0 en | 0 | RW | ICM0 enable When set this bit to 0, it mean disabled input capture module 0 and the interrupt also cleared. |
81.1 ICM0 Config Register 1 (icm0 cfg1)
Address: 0x9C002884
Reset: 0x0000 4000
| Field Name | Bit | Access | Description |
| Write Mask Bits | 31:16 | RW | Write Mask Bits Corresponding Mask Bits for Bit[15:0] Example: If user want to set bit0 = 1, than he should set bit16 to 1 (0x 0001) to enable bit0 functionality |
| icm0 fifo full | 15 | RO | Indicate the fifo is full (fifo depth is 7). 0: Non-full 1: Full |
| icm0 fifo empty | 14 | RO | Indicate the fifo is empty (fifo depth is 7). 0: Non-Empty 1: Empty |
| icm0 fifo clr | 13 | W1C | Input Capture Module 0 FIFO Clear 0: Writing 0 to this bit has no effect 1: Clear fifo and icm fifo data drop. Write 1 to clear fifo and icm fifo data drop flag, HW will recover this bit to 0 automatically. |
| icm0 fifo data drop | 12 | RO | Input Capture Module 0 Data Dropped 0: Non-dropped 1: Indicate the fifo data dropped. |
| Reserve | 11:9 | RO | RESERVED |
| icm0 df times | 8:6 | RW | Input Capture Module 0 Input Signal Debounce Filter Set the debounce times (0-7) of the input signal debounce filter. 0x0-6: icm0 df times+1 times, 0x7: 16 times |
| icm0 ee times | 5:2 | RW | Input capture module interrupt trigger threshold Set 0-15. If set 7, interrupt will be triggered after 8 times edge event. |
| icm0 ee mode | 1:0 | RW | Input capture detect mode Select Others don't care. |
81.2 ICM0 Internal Counter Scaler (icm0 cfg2)
Address: 0x9C002888
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| icm0 cnt scale | 31:0 | RW | ICM0 Internal Counter Scaler Clock prescaler 0-(2ˆ32-1). clk cnt = ext clk / (icmx cnt scale+1) |
81.3 Reserve
Address: 0x9C00288C
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| reserve | 31:0 | RW | reserve |
81.4 ICM0 Interrupt Trigger Counter Value (icm0 cnt)
Address: 0x9C002890
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| icm0 cnt | 31:0 | RO | ICM0 Interrupt Trigger Counter Value Record the internal counter value when interrupt happened. Interrupt trigger mode can be select by register G81.1 bit1~0. |
81.5 ICM0 Pulse Width H (icm0 pulse witdh h)
Address: 0x9C002894
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| icm0 pulse width h | 31:0 | RO | ICM0 Pulse Width H Square pulse high level width (unit : t, icm0_clk) |
81.6 ICM0 Pulse Width L (icm0 pulse width l)
Address: 0x9C002898
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| icm0 pulse width l | 31:0 | RO | ICM0 Pulse Width L Square pulse low level width (unit : t, icm0_clk) |
81.7 ICM1 Config Register 0 (icm1 cfg0)
Address: 0x9C00289C
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| Write Mask Bits | 31:16 | RW | Write Mask Bits Corresponding Mask Bits for Bit[15:0] Example: If user want to set bit0 = 1, than he should set bit16 to 1 (0x 0001) to enable bit0 functionality |
| Reserve | 15:9 | RO | RESERVED |
| icm1 clk sel | 8:6 | RW | Select clock source. (External CLK range 32K-210M Hz) 0: External CLK 0 (default) 1: External CLK 1 2: External CLK 2 3: External CLK 3 4: SYSCLK 5: 27 MHz 6: 32 KHz Others : 0 |
| icm1 mux sel | 5:3 | RW | Select input signal source. 0: Input 0 (default) 1: Input 1 2: Input 2 3: Input 3 Others: 0 |
| icm1 int clr | 2 | W1C | Clear the interrupt. Write 1 to clear interrupt, HW will recover this bit to 0 automatically. |
| Reserve | 1 | RW | RESERVED |
| icm1 en | 0 | RW | ICM1 enable When set this bit to 0, it mean disabled input capture module 1 and the interrupt also cleared. |
81.8 ICM1 Config Register 1 (icm1 cfg1)
Address: 0x9C0028A0
Reset: 0x0000 4000
| Field Name | Bit | Access | Description |
| Write Mask Bits | 31:16 | RW | Write Mask Bits Corresponding Mask Bits for Bit[15:0] Example: If user want to set bit0 = 1, than he should set bit16 to 1 (0x 0001) to enable bit0 functionality |
| icm1 fifo full | 15 | RO | Indicate the fifo is full (fifo depth is 7). 0: Non-full 1: Full |
| icm1 fifo empty | 14 | RO | Indicate the fifo is empty (fifo depth is 7). 0: Non-Empty 1: Empty |
| icm1 fifo clr | 13 | W1C | Input Capture Module 1 FIFO Clear 0: Writing 0 to this bit has no effect 1: Clear fifo and icm fifo data drop. Write 1 to clear fifo and icm fifo data drop flag, HW will recover this bit to 0 automatically. |
| icm1 fifo data drop | 12 | RO | Input Capture Module 1 Data Dropped 0: Non-dropped 1: Indicate the fifo data dropped. |
| Reserve | 11:9 | RO | Reserved |
| icm1 df times | 8:6 | RW | Input Capture Module 1 Input Signal Debounce Filter Set the debounce times (0-7) of the input signal debounce filter. 0x0-6: icm1 df times+1 times, 0x7: 16 times |
| icm10 ee times | 5:2 | RW | Input capture module interrupt trigger threshold Set 0-15. If set 7, interrupt will be triggered after 8 times edge event. |
| icm1 ee mode | 1:0 | RW | Input capture detect mode Select Others don't care. |
81.9 ICM1 Internal Counter Scaler (icm1 cfg2)
Address: 0x9C0028A4
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| icm1 cnt scale | 31:0 | RW | ICM1 Internal Counter Scaler Clock prescaler 0-(2ˆ32-1). clk cnt = ext clk / (icmx cnt scale+1) |
81.10 Reserve
Address: 0x9C0028A8
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| reserve | 31:0 | RW | reserve |
81.11 ICM1 Interrupt Trigger Counter Value (icm1 cnt)
Address: 0x9C0028AC
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| icm1 cnt | 31:0 | RO | ICM1 Interrupt Trigger Counter Value Record the internal counter value when interrupt happened. Interrupt trigger mode can be select by register G81.1 bit1~0. |
81.12 ICM1 Pulse Width H (icm1 pulse witdh h)
Address: 0x9C0028B0
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| icm1 pulse width h | 31:0 | RO | ICM1 Pulse Width H Square PWM pulse high level width (unit : t, icm1_clk) |
81.13 ICM1 Pulse Width L (icm1 pulse width l)
Address: 0x9C0028B4
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| icm1 pulse width l | 31:0 | RO | ICM1 Pulse Width L Square PWM pulse low level width (unit : t, icm1_clk) |
81.14 ICM2 Config Register 0 (icm2 cfg0)
Address: 0x9C0028B8
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| Write Mask Bits | 31:16 | RW | Write Mask Bits Corresponding Mask Bits for Bit[15:0] Example: If user want to set bit0 = 1, than he should set bit16 to 1 (0x 0001) to enable bit0 functionality |
| Reserve | 15:9 | RO | RESERVED |
| icm2 clk sel | 8:6 | RW | Select clock source. (External CLK range 32K-210M Hz) 0: External CLK 0 (default) 1: External CLK 1 2: External CLK 2 3: External CLK 3 4: SYSCLK 5: 27 MHz 6: 32 KHz Others : 0 |
| icm2 mux sel | 5:3 | RW | Selec input signal source. 0: Input 0 (default) 1: Input 1 2: Input 2 3: Input 3 Others: 0 |
| icm2 int clr | 2 | W1C | Clear the interrupt. Write 1 to clear interrupt, HW will recover this bit to 0 automatically. |
| Reserve | 1 | RW | RESERVED |
| icm2 en | 0 | RW | ICM2 enable When set this bit to 0, it mean disabled input capture module 2 and the interrupt also cleared. |
81.15 ICM2 Config Register 1 (icm2 cfg1)
Address: 0x9C0028BC
Reset: 0x0000 4000
| Field Name | Bit | Access | Description |
| Write Mask Bits | 31:16 | RW | Write Mask Bits Corresponding Mask Bits for Bit[15:0] Example: If user want to set bit0 = 1, than he should set bit16 to 1 (0x 0001) to enable bit0 functionality |
| icm2 fifo full | 15 | RO | Indicate the fifo is full (fifo depth is 7). 0: Non-full 1: Full |
| icm2 fifo empty | 14 | RO | Indicate the fifo is empty (fifo depth is 7). 0: Non-Empty 1: Empty |
| icm2 fifo clr | 13 | W1C | Input Capture Module 2 FIFO Clear 0: Writing 0 to this bit has no effect 1: Clear fifo and icm fifo data drop. Write 1 to clear fifo and icm fifo data drop flag, HW will recover this bit to 0 automatically. |
| icm2 fifo data drop | 12 | RO | Input Capture Module 2 Data Dropped 0: Non-dropped 1: Indicate the fifo data dropped. |
| Reserve | 11:9 | RO | Reserved |
| icm2 df times | 8:6 | RW | Input Capture Module 2 Input Signal Debounce Filter Set the debounce times (0-7) of the input signal debounce filter. 0x0-6: icm2 df times+1 times, 0x7: 16 times |
| icm2 ee times | 5:2 | RW | Input capture module interrupt trigger threshold Set 0-15. If set 7, interrupt will be triggered after 8 times edge event. |
| icm2 ee mode | 1:0 | RW | Input capture detect mode Select Others don't care. |
81.16 ICM2 Internal Counter Scaler (icm2 cfg2)
Address: 0x9C0028C0
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| icm2 cnt scale | 31:0 | RW | ICM2 Internal Counter Scaler Clock prescaler 0-(2ˆ32-1). clk cnt = ext clk / (icmx cnt scale+1) |
81.17 Reserve
Address: 0x9C0028C4
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| reserve | 31:0 | RW | reserve |
81.18 ICM2 Interrupt Trigger Counter Value (icm2 cnt)
Address: 0x9C0028C8
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| icm2 cnt | 31:0 | RO | ICM2 Interrupt Trigger Counter Value Record the internal counter value when interrupt happened. Interrupt trigger mode can be select by register G81.1 bit1~0. |
81.19 ICM2 Pulse Width H (icm2 pulse witdh h)
Address: 0x9C0028CC
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| icm2 pulse width h | 31:0 | RO | ICM2 Pulse Width H Square PWM pulse high level width (unit : t, icm2_clk) |
81.20 ICM2 Pulse Width L (icm2 pulse width l)
Address: 0x9C0028D0
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| icm2 pulse width l | 31:0 | RO | ICM2 Pulse Width L Square PWM pulse low level width (unit : t, icm2_clk) |
81.21 ICM3 Config Register 0 (icm3 cfg0)
Address: 0x9C0028D4
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| Write Mask Bits | 31:16 | RW | Write Mask Bits Corresponding Mask Bits for Bit[15:0] Example: If user want to set bit0 = 1, than he should set bit16 to 1 (0x 0001) to enable bit0 functionality |
| Reserve | 15:9 | RO | RESERVED |
| icm3 clk sel | 8:6 | RW | Select clock source. (External CLK range 32K-210M Hz) 0: External CLK 0 (default) 1: External CLK 1 2: External CLK 2 3: External CLK 3 4: SYSCLK 5: 27 MHz 6: 32 KHz Others : 0 |
| icm3 mux sel | 5:3 | RW | Select input signal source. 0: Input 0 (default) 1: Input 1 2: Input 2 3: Input 3 Others: 0 |
| icm3 int clr | 2 | W1C | Clear the interrupt. Write 1 to clear interrupt, HW will recover this bit to 0 automatically. |
| Reserve | 1 | RW | RESERVED |
| icm3 en | 0 | RW | ICM3 enable When set this bit to 0, it mean disabled input capture module 3 and the interrupt also cleared. |
81.22 ICM3 Config Register 1 (icm3 cfg1)
Address: 0x9C0028D8
Reset: 0x0000 4000
| Field Name | Bit | Access | Description |
| Write Mask Bits | 31:16 | RW | Write Mask Bits Corresponding Mask Bits for Bit[15:0] Example: If user want to set bit0 = 1, than he should set bit16 to 1 (0x 0001) to enable bit0 functionality |
| icm3 fifo full | 15 | RO | Indicate the fifo is full (fifo depth is 7). 0: Non-full 1: Full |
| icm3 fifo empty | 14 | RO | Indicate the fifo is empty (fifo depth is 7). 0: Non-Empty 1: Empty |
| icm3 fifo clr | 13 | W1C | Input Capture Module 3 FIFO Clear 0: Writing 0 to this bit has no effect 1: Clear fifo and icm fifo data drop. Write 1 to clear fifo and icm fifo data drop flag, HW will recover this bit to 0 automatically. |
| icm3 fifo data drop | 12 | RO | Input Capture Module 3 Data Dropped 0: Non-dropped 1: Indicate the fifo data dropped. |
| Reserve | 11:9 | RO | RESERVED |
| icm3 df times | 8:6 | RW | Input Capture Module 3 Input Signal Debounce Filter Set the debounce times (0-7) of the input signal debounce filter. 0x0-6: icm3 df times+1 times, 0x7: 16 times |
| icm3 ee times | 5:2 | RW | Input capture module interrupt trigger threshold Set 0-15. If set 7, interrupt will be triggered after 8 times edge event. |
| icm3 ee mode | 1:0 | RW | Input capture detect mode Select Others don't care. |
81.23 ICM3 Internal Counter Scaler (icm3 cfg2)
Address: 0x9C0028DC
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| icm3 cnt scale | 31:0 | RW | ICM3 Internal Counter Scaler Clock prescaler 0-(2ˆ32-1). clk cnt = ext clk / (icmx cnt scale+1) |
81.24 Reserve
Address: 0x9C0028E0
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| reserve | 31:0 | RW | reserve |
81.25 ICM3 Interrupt Trigger Counter Value (icm3 cnt)
Address: 0x9C0028E4
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| icm3 cnt | 31:0 | RO | ICM3 Interrupt Trigger Counter Value Record the internal counter value when interrupt happened. Interrupt trigger mode can be select by register G81.1 bit1~0. |
81.26 ICM3 Pulse Width H (icm3 pulse witdh h)
Address: 0x9C0028E8
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| icm3 pulse width h | 31:0 | RO | ICM3 Pulse Width H Square PWM pulse high level width (unit : t, icm3_clk) |
81.27 ICM3 Pulse Width L (icm3 pulse width l)
Address: 0x9C0028EC
Reset: 0x0000 0000
Field Name | Bit | Access | Description |
icm3 pulse width l | 31:0 | RO | ICM3 Pulse Width L Square PWM pulse low level width (unit : t, icm3_clk) |
81.28 (Reserved)
Address: 0x9C0028F0
Reset: 0x0000 0000
Field Name | Bit | Access | Description |
Reserved | 31:0 | RO | RESERVED |
81.29 (Reserved)
Address: 0x9C0028F4
Reset: 0x0000 0000
Field Name | Bit | Access | Description |
Reserved | 31:0 | RO | RESERVED |
81.30 (Reserved)
Address:0x9C0028F8
Reset: 0x0000 0000
Field Name | Bit | Access | Description |
Reserved | 31:0 | RO | RESERVED |
81.31 IP Version (ip version)
Address: 0x9C0028FC
Reset: 0x1811 1001
Field Name | Bit | Access | Description |
| ip version | 31:0 | RO | IP Version 0xaabbcdee, a : year (eg 0X018) b : month (BCD : 01-12) c |