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31. Inter-Integrated Circuit (I2C)

31. Inter-Integrated Circuit (I2C)

Sept 29, 2021

 

31.1 Introduction

I2C is invented by Philips Semiconductor and typically used for attaching lower-speed peripheral ICs communication. Two bus lines are required: a serial data line (SDA) and a serial clock line (SCL). There are four I2C master devices in SP7021, the registers space locate to address 0x9C004600~0x9C0049FF. They support the following functions:

  • Support Standard-mode (100KHz) and Fast-mode (400KHz)

  • Buffer depth reach FIFO 32

  • Support Read Mode, Write Mode and Restart Mode

  • Support DMA function

 

31.2 Function Diagram

A generalized function diagram of I2C Master Function Block is shown in Figure 31-1. I2C Master Controller will send Write or Read command after setting registers. The I2C Master will detect clock stretching when SCL low after receiving (or sending) a byte.

Figure 31-1 I2C MASTER Function Block

  • CLOCK GENERATION: The CLK generation circuit can generate SCL signal by setting register.

  • WAIT COUNTER: The wait counter circuit can detect clock stretching using SCL signal.

  • SHIFT CIRCUIT: The shift circuit can send data to SDA signal, or receive data from SDA signal.

  • NOISE FILTER: Noise Filter pass the signals only if the signal hold for require time. The require time can be set by register.

  • DATA FIFO: The write data can save in Data FIFO then transmit to I2C slave device.

  • DATA BUFFER: The DATA BUFFER module support I2C READ and I2C WRITE in normal mode.

  • GDMA: GDMA module is used for DMA function, support I2C READ and I2C WRITE.

  • CDC: Register CDC for clock domain crossing between 27MHz clock and SYS_CLK.

 

31.3 I2C Data Format

Figure 31-2 I2C Data Format

  • Every byte put on the SDA line must be eight bits long

  • The number of bytes that can be transmitted per transfer is unrestricted

  • The first byte include 7 bits slave address and 1 bit Read(HIGH)/Write(LOW)

  • START: SDA HIGH to LOW while SCL is HIGH

  • STOP: SDA LOW to HIGH while SCL is HIGH

  • ACK: SDA will pull LOW in the 9th clock period

  • NACK: SDA will remain HIGH in the 9th clock period

Figure 31-3 ACK and NACK condition

31.4 Clock Frequency Selection

When FREQ set to 1/2/3/4/5/6/7, it will map to divider as 1024/512/256/128/64/32/16 and the I2C clock will be 27MHz/divider. The FREQ is bit[26:24] of Group140.0 control0 register. When FREQ set to 0, then the I2C clock frequency can be set by FREQ_CUSTOM. The calculation formula is 27MHz/FREQ_CUSTOMThe FREQ_CUSTOM located in register Group140.2 (CONTROL2)[10:0].

31.5 Software Reset

A software reset can be performed by set SW_RST bit to 1. The SW_RST locate at bit15 of Group140.0 control0 register. In that case, I2C lines SCL and SDA are released. Internal states machines are reset and communication control bits, as well as status bits come back to their reset value. The configuration registers are not impacted.

31.6 NACK FLAG

When I2C master do the write transaction, the slave device is NACK. The bit0 of Group140.4 control4 register will become 1, it means I2C master write byte1 NACK. The bit1=1, means I2C master write byte2 NACK. Max can indicate 32 byte NACK. To clear the NACK flag, please set corresponding bit of Group140.3 control3 register.

31.7 I2C Operation Mode

31.7.1 Read mode & Burst Read mode

I2CM0 provides a read function. The read procedure as below:

  • Set clock div value, PREFETCH=1 and SLAVE ADDR. For detailed settings, please refer to register Group140.0 (CONTROL0)[26:24], register Group140.0 (CONTROL0)[18] and register Group140.0 (CONTROL0)[7:1].

  • Set the number of BYTEs that need to be read. You can set 1~65535. For detailed settings, please refer to register Group140.17 (CONTROL7)[31:16].

  • If the read data is larger than 32bytes, set I2CRDATA_EN=1 (Group140.13 register).

  • After receiving the interrupt, read the corresponding data.

  • Clear interrupt, set I2CWRDATA_CLR=1 (Group140.12 register)

 

31.7.2 Write mode & Burst Write mode

I2CM0 provides a write function. The write procedure as below:

  • Set clock div value, SLAVE ADDR. For detailed settings, please refer to register Group140.0 (CONTROL0)[26:24] and register Group140.0 (CONTROL0)[7:1].

  • Set the number of BYTEs that need to be written. You can set 1~65535. Setting 0byte will be wrong. For detailed settings, please refer to register Group140.17 (CONTROL7)[15:0]

  • Set the data to be written. Write up to 32 bytes for the first time. For detailed settings, please refer to register Group140.24-28 (DATA).

  • If the data is over 32 bytes, you can set CTL_EMPTY_THRESGOLD and EMPTY_THRESHOLD_EN. For detailed settings, please refer to register Group140.8 (I2CM INT_EN0)[11:9] and Group140.8 (I2CM INT_EN0)[6].

  • After triggering EMPTY_THRESHOLD_FLAG (refer to Group140.7 (INTERRUPT)[6]), read RING_VALUE (refer to Group140.5 (CONTROL5)[23:21]) to write a few 4 Bytes, or directly write the number of CTL_EMPTY_THRESGOLD*4 Bytes

  • Write Group140.24 (DATA) register, 4 Bytes data at a time

  • After writing, clear EMPTY_THRESHOLD_FLAG by write Group140.1 (CONTROL1)[6]=1 at first, then write Group140.1 (CONTROL1) [6]=0.

  • After writing the required data, set EMPTY_THRESHOLD_EN=0.

 

31.7.3 Restart Mode(selective read)

I2CM0 provides the restart function that directly read after writing, and does not need to issue STOP and then START, providing the function of first write the read address and then read the data.

  • You need to first set MANUAL_MODE=0 and set MANUAL_TRIG=0. For detailed settings, please refer to register Group140.9 (I2CM_MODE)[1] and Group140.9 (I2CM_MODE)[0].

  • Set the number of BYTEs that need to be written and read. For detailed settings, please refer to register Group140.17 (CONTROL7)[31:16]RDCOUNT, register Group140.17 (CONTROL7)[15:0]WRCOUNT.

  • Set the data to be written. For detailed settings, please refer to register Group140.24-28(DATA).

  • Set clock div, PREFETCH=1, RESTART_EN=1, SUBADDR_EN=1 and SLAVE ADDR. For detailed settings, please refer to register Group140.0 (CONTROL0)[26:24], register Group140.0 (CONTROL0)[18], register Group140.0 (CONTROL0)[17], register Group140.0 (CONTROL0)[16], register Group140.0 (CONTROL0)[7:1].

  • Set MANUAL_MODE =0 and set MANUAL_TRIG =1. For detailed settings, please refer to register Group140.9 (I2CM_MODE)[1] and Group140.9 (I2CM_MODE)[0].

 

31.7.4 I2C DMA Read Mode

The DMA read data transmission procedure is as following figure.

Figure 31-4 I2C DMA Read Mode


I2CM provides read from I2C slave to DRAM functionality.

  • Set DMA MODE=1, refer to Group140.9 (I2CM MODE)[2].

  • Set clock div value, PREFETCH and SLAVE ADDR. For detailed settings, please refer to register Group140.0 (CONTROL0)[26:24], register Group140.0 (CONTROL0)[18] and register Group140.0 (CONTROL0)[7:1].

  • Set DMA destination address, refer to Group141.3 (DMA_ADR)[31:0].

  • Set the number of BYTEs that the DMA needs to write. Refer to Group141.2 (DMA_LENGTH)[24:0].

  • Set DMA WRITE MODE=1, DMA_GO=1, refer to Group141.1 (DMA_CONFIG)[0] and Group141.1 (DMA_CONFIG)[8].

  • Set I2C_DONE_EN=0 and DMA_DONE_EN=1, refer to register Group140.8 (I2CM INT EN)[1] and Group141.6 (INT EN)[0], and wait GDMA_DONE interrupt in register Group141.5 (INT_FLAG)[0].

  • Clear GDMA_DONE interrupt in register Group141.5 (INT_FLAG)[0].

 

31.7.5 I2C DMA Write Mode

The DMA write data reception procedure is as follows:

Figure 31-5 I2C DMA Write Mode


I2CM provides write data to I2C Slave, which data from DRAM function.

  • Set DMA MODE=1, refer to Group140.9 (I2CM MODE)[2].

  • Set clock div, SLAVE ADDR. For detailed settings, please refer to register Group140.0 (CONTROL0)[26:24] and register Group140.0 (CONTROL0)[7:1].

  • Set DMA source address, refer to Group141.3 (DMA_ADR)[31:0].

  • Set the number of BYTEs that the DMA needs to write. Refer to Group141.2 (DMA_LENGTH)[24:0].

  • Set DMA WRITE MODE=0, DMA_GO=1, refer to Group141.1 (DMA_CONFIG)[0] and Group141.1 (DMA_CONFIG)[8].

  • Set I2C_DONE_EN=0 and wait I2C_DONE interrupt, refer to register Group140.8 (I2CM INT EN)[1] and Group140.7 (I2CM INTERRUPT)[1].

  • Clear I2C_DONE interrupt

 

31.7.6 I2C DMA Restart Mode

The DMA restart data reception procedure is as follows. Direction1 means write to I2C slave from register, Direction2 means read from I2C slave to DRAM.

Figure 31-6 I2C DMA Restart Mode


I2CM provides restart write to I2C slave from register, read I2C slave to DRAM function.

  • First set the I2C Registers

  • Set DMA MODE=1, MANUAL_MODE=0, MANUAL_TRIG=0, refer to Group140.9 (I2CM MODE)[2], register Group140.9 (I2CM_MODE)[1] and Group140.9 (I2CM_MODE)[0].

  • Set clock div, PREFETCH=1, RESTART_EN=1, SUBADDR_EN=1, SLAVE ADDR. For detailed settings, please refer to register Group140.0 (CONTROL0)[26:24], register Group140.0 (CONTROL0)[18], register Group140.0 (CONTROL0)[17], register Group140.0 (CONTROL0)[16], register Group140.0 (CONTROL0)[7:1]

  • Set the number of BYTEs to be written. For detailed settings, please refer to register Group57.CONTROL7[31:16], register Group57.CONTROL7[15:0]

  • Set the data to be written. For detailed settings, please refer to register Group140.24-28 (DATA).

  • Receiver set GDMA Register

  • Set DMA destination address, refer to Group141.3 (DMA_ADR)[31:0].

  • Set the number of BYTEs that the DMA needs to write. Refer to Group141.2 (DMA_LENGTH)[24:0].

  • Set DMA WRITE MODE=1, DMA_GO=1, refer to Group141.1 (DMA_CONFIG)[0] and Group141.1 (DMA_CONFIG)[8].

  • Reset I2C Register

  • Set to MANUAL_MODE=0 and set MANUAL_TRIG=1. For detailed settings, please refer to register Group140.9 (I2CM_MODE)[1] and Group140.9 (I2CM_MODE)[0].

  • If the data is over 32BYTES, you can set CTL_EMPTY_THRESHOLD and EMPTY_THRESHOLD_EN. For detailed settings, please refer to register Group140.8 (I2CM INT_EN0)[11:9] and Group140.8 (I2CM INT_EN0)[6].

  • After triggering EMPTY_THRESHOLD_FLAG Group140.7 (INTERRUPT)[6], read RING_VALUE Group140.5 (CONTROL5)[23:21] to write a few 4 Bytes, or directly write the number of CTL_ EMPTY_THRESHOLD *4 Bytes

  • Write Group140.24 (DATA), 4 Bytes data at a time

  • After writing, clear EMPTY_THRESHOLD_FLAG, write Group140.1 (CONTROL1)[6]=1, then write Group140.1 (CONTROL1) [6]=0.

  • After writing the required information, set EMPTY_THRESHOLD_EN to 0.

  • Set I2C_DONE_EN=0 and DMA_DONE_EN=1, refer to register Group140.8 (I2CM INT EN)[1] and Group141.6 (INT EN)[0], and wait GDMA_DONE interrupt in register Group141.5 (INT_FLAG)[0].

  • Clear GDMA_DONE interrupt in register Group141.5 (INT_FLAG)[0].

 

31.8 FIFO Operation

The RING_VALUE shows the redundant size of the FIFO (4*n bytes) in register Group140.5 (CONTROL5)[23:21], and can set CTL_EMPTY_THRESHOLD (register Group140.8 (INT_EN0)[11:9]) and EMPTY_THRESHOLD_EN (register Group140.8 (INT_EN0)[ 6]) to trigger interrupt, then write data.The number of writing and reading bytes of FIFO is displayed by FIFO_RCOUNTER (register Group140.6 (I2CM_STATUS0)[31:16]) and FIFO_WCOUNTER (register Group140.6 (I2CM_STATUS0)[15:0]). RINC_INDEX (register Group140.7 (I2CM INTERRUPT)[21:19]) and WINC_INDEX (register Group140.7 (I2CM INTERRUPT)[18:16]) show FIFO write and read indicators.Monitor WFIFO_ENABLE (register Group140.7 (I2CM INTERRUPT)[10]), FULL_FLAG (register Group140.7 (I2CM INTERRUPT)[9]), EMPTY_FLAG (register Group140.7 (I2CM INTERRUPT)[8]) to determine if writing can continue.

31.9 Clock stretching

Detect if the slave has pulled SCL signal. If the slave is found to hold SCL signal, the master will enter the wait state, pause the transmission and send a notification. Master will wait for the slave to release SCL, then stop the transmission and wait for the next transmission. Automatic continuous transfer is not supported currently.For detailed settings, please refer to SCL_WAIT_FLAG (register Group140.7 (I2CM INTERRUPT)[7]), SCL_WAIT_INT_EN (register Group140.8 (I2CM INT_EN0)[7]), SCL_WAIT_CLR (register Group140.1 (CONTROL1)[7]), SCL_WAIT_TIME (register Group140.11 (I2CM_STATUS2)[9:0]). If you pull the Clock stretching before returning the ACK, you need to see CLK_ERR_FLAG (register Group140.7 (I2CM INTERRUPT)[2]).

31.10 I2C Interrupt Handler

I2C interrupt handler handle the internal interrupt of I2C Master Module. Group140.8 (i2cm_int_en0) register can enable interrupt for each status. An interrupt is issued when i2c active done or an interrupt is issued when FIFO data can receive or transmit data. Read Group140.7 (i2cm_interrupt) register to see what interrupt happened. After read register, need to clear interrupt flag by write Group140.1 (control1) register. I2C Master0 in IRQ number is 174, I2C Master1 in IRQ number is 175, I2C Master2 in IRQ number is 176 and I2C Master3 in IRQ number is 177.Table 31-1 shows the interrupt events in the Group140.7 (i2cm_interrupt) register.

Fields

Event flag

Interrupt event

Bit 9

FULL_FLAG

Monitor I2C master ring FIFO full flag.

Bit 8

EMPTY_FLAG

Monitor I2C master ring FIFO empty flag.

Bit 7

SCL_WAIT_FLAG

I2C SCL bus waits (when I2C SCL waits by I2C slave device).

Bit 6

EMPTY_THRESHOLD_FLAG

When I2C master ring value (read index - write index) >= empty threshold

Bit 5

DATA_NACK_FLAG

Monitor i2c slave, data NACK (when I2C master transmit).

Bit 4

ADDRESS_NACK_FLAG

Monitor i2c slave, slave address NACK (when I2C master transmit).

Bit 3

BUSBUSY_FLAG

When I2C master engine is idle, monitor the I2C is idle or not.

Bit 2

CLKERR_FLAG

I2C master active, monitor SCL input active error flag.

Bit 1

DONE_FLAG

I2C master active done flag.

Bit 0

SIFBUSY_FLAG

When I2C master engine active flag.

Table 31-1 Interrupt Event

Figure 31-7 I2C Interrupt Tree

31.11 Registers Map

31.11.1  Register Memory Map

I2C Register Memory Map

Group Base Address

Data Width

Group No.

Module

0x9C004600

32

140

I2CM0

0x9C004680

32

141

I2CM0_GDMA

0x9C004700

32

142

I2CM1

0x9C004780

32

143

I2CM1_GDMA

0x9C004800

32

144

I2CM2

0x9C004880

32

145

I2CM2_GDMA

0x9C004900

32

146

I2CM3

0x9C004980

32

147

I2CM3_GDMA

Table 31-2 I2C Register Memory Map


All I2Cs' registers have the same offset (address - base address) in corresponding I2C register group. Only I2C0 and its corresponding DMA (I2C0 DMA) registers are described in following register description, for other I2Cs (I2C1, 2, 3) please refer to I2C0 description for more detail.

31.11.2  Registers Description


I2C Register Description


RGST Table Group 140 I2C Master0

140.0 I2C Master Control 0 (control0)
Address: 0x9C004600
Reset: 0x0211 0060

 

Field Name

Bit

Access

Description

RESERVED

31:27

RO

RESERVED

FREQ

26:24

R/W

Serial bus master speed selection.

0x0: custom— customized set for I2C clock
0x1: div 1024— 27MHz div 1024.
0x2: div 512— 27MHz div 512.(default)
0x3: div 256— 27MHz div 256.
0x4: div 128— 27MHz div 128.
0x5: div 64— 27MHz div 64.
0x6: div 32— 27MHz div 32.
0x7: div 16— 27MHz div 16.

RESERVED

23:19

RU

RESERVED

PREFETCH

18

R/W

Writing this bit will initiate master I2C read action, the address is set (eg. 0x10) and the corresponding data is stored in the register (eg. 0x18).
In restart mode this bit have to set 1'b1

RESTART EN

17

R/W

This bit determines whether the Synchronous serial in- terface's repeat start condition.(Only enable when Syn- chronous Serial interface read.)

0: disable— Do not repeat start.(default)
1: enable— Repeat start.

SUBADDR EN

16

R/W

The I2C master read transaction will include device sub- address, in restart mode this bit have to set 1'b1

0: disable— skip subaddress
1: enable— inlcude sub address(default)

SW RST

15

OTHER

Local reset I2C master

0: normal(default)
1: reset

RESERVED

14:8

RU

RESERVED

SLAVE ADDR

7:1

RW

Decide serial bus slave address for the function of serial bus master (In master mode), want to access the slave device address

RESERVED

0

RO

RESERVED

 

140.1 I2C Master Control 1 (control1)

Address: 0x9C004604
Reset:0x0

Field Name

Bit

Access

Description

RESERVED

31:10

RO

RESERVED