28. Audio

28.1 Introduction

The 【AUD module】is an abbreviation of Audio. This module manages all of the audio playback. It contains the standard I2S and S/PDIF interface (Encode/Decode), signals record from ADC, and multi-channel mix. It supports up to 192KHz sample rate. When the audio data has been decoded by DSP and saved in DRAM, AUD module will fetch the data from DRAM and encode it with I2S or SPDIF protocol. It also can decode the I2s or SPDIF signal and save the data in DRAM for further usage.

28.2 Function Diagram

The input path is shown as figure 28-1 and the output path is shown as figure 28-2. The hardware block diagram is shown as figure 28-3..

Figure 28-1 AUD Intput Functional Blocks

Figure 28-2 AUD Output Functional Blocks

Figure 28-3 AUD Hardware Functional Blocks

The I2S output up to 6 stereo channels and input up to 4 stereo channels.
The SPDIF interface support one output and one input.
The TDM/PDM interface support up to 8 channel microphone array.

28.3 Pin assignment

GPIO_P1_00 ~ GPIO_P1_06 pins will be set to I2S audio IN function while G1.1 register bit15 set to 1. (Please refer to table 28-1)
GPIO_P2_05 ~ GPIO_P3_05 pins will be set to I2S audio OUT function while G1.2 register bit0 set to 1. (Please refer to table 28-1)
GPIO_P2_04 pin will be set to SPDIF IN function while G1.2 register bit2 set to 1. (Please refer to table 28-2)
GPIO_P2_04 pin will be set to SPDIF OUT function while G1.2 register bit3 set to 1. (Please refer to table 28-2)
GPIO_P2_05 ~ GPIO_P3_02 pins will be set to TDM TX function while G1.2 register bit4 set to 1. (Please refer to table 28-3)
GPIO_P1_07 ~ GPIO_P2_02 pins will be set to TDM RX function while G1.2 register bit5 set to 1. (Please refer to table 28-3)
GPIO_P1_07 ~ GPIO_P2_03 pins will be set to PDM RX function while G1.2 register bit6 set to 1. (Please refer to table 28-4)
GPIO_P3_07 ~ GPIO_P4_04 pins will be set to PCM function while G1.2 register bit7 set to 1. (Please refer to table 28-5)
While use audio function, do not set GPIO function and Multiplex Peripheral Pin within GPIO_P1_00 ~ GPIO_P4_04 pins.
Please also careful that some pins have multiplex functions, don't enable them at the same time.

Pin Name	I2S audio IN signals	I2S audio OUT signals
GPIO_P1_00	CLKGENA_EXT_ADC_XCK_O
GPIO_P1_01	ADC_BCK
GPIO_P1_02	ADC_LRCK
GPIO_P1_03	ADC_DATA0
GPIO_P1_04	ADC_DATA1
GPIO_P1_05	ADC_DATA2
GPIO_P1_06	ADC_DATA3
GPIO_P2_05		CLKGENA_EXT_DAT_XCK
GPIO_P2_06		AU_BCK
GPIO_P2_07		AU_LRCK
GPIO_P3_00		AU_DATA0
GPIO_P3_01		AU_DATA1
GPIO_P3_02		AU_DATA2
GPIO_P3_03		AU_DATA3
GPIO_P3_04		AU_DATA4
GPIO_P3_05		AU_DATA5

Table 28-1 I2C audio pin define

Pin Name	SPDIF IN signals	SPDIF OUT signals
GPIO_P2_04	AUD_IEC0_RX
GPIO_P3_06		AUD_IEC0_TX

Table 28-2 SPDIF pin define

Pin Name	TDM TX signals	TDM RX signals
GPIO_P2_05	CLKGENA_TDMTX_XCK_O
GPIO_P2_06	TDMTX_BCK
GPIO_P2_07	TDMTX_SYNC
GPIO_P3_00	TDMTX_DATA4
GPIO_P3_01	TDMTX_DATA8
GPIO_P3_02	TDMTX_DATA16
GPIO_P1_07		TDMRX_BCK
GPIO_P2_00		TDMRX_SYNC
GPIO_P2_01		TDMRX_DATA4
GPIO_P2_02		TDMRX_DATA8

Table 28-3 TDM pin define

Pin Name	PDM RX signals
GPIO_P1_07	PDMRX_BCK
GPIO_P2_00	PDMRX_DATA0
GPIO_P2_01	PDMRX_DATA1
GPIO_P2_02	PDMRX_DATA2
GPIO_P2_03	PDMRX_DATA3

Table 28-4 PDM pin define

Pin Name	PCM signals
GPIO_P3_07	PCM_IEC_TX0
GPIO_P4_00	PCM_IEC_TX1
GPIO_P4_01	PCM_IEC_TX2
GPIO_P4_02	PCM_IEC_TX3
GPIO_P4_03	PCM_IEC_TX4
GPIO_P4_04	PCM_IEC_TX5

Table 28-5 PCM pin define

28.4 Registers Map

28.4.1 Registers Memory Map

Address	Group No.	Register Name	Description
0x9C001E00	G60.0	audif_ctrl	AUD Interface Control
0x9C001E04	G60.1	aud_enable	Audio FIFO Request Enable
0x9C001E08	G60.2	pcm_cfg	Audio PCM (I2S) Format Configuration
0x9C001E0C	G60.3	i2s_mute_flag_ctrl	Mute Flag of I2S TX Module
0x9C001E10	G60.4	ext_adc_cfg	External ADC (I2S) Format Configuration
0x9C001E14	G60.5	int_dac_ctrl0	Internal DAC Control 0 (ACODEC_CFG0)
0x9C001E18	G60.6	int_adc_ctrl	Internal ADC Config
0x9C001E1C	G60.7	adc_in_path_switch	ADC Input Path Switch
0x9C001E20	G60.8	int_adc_dac_cfg	Internal ADC and DAC (I2S) Format Configuration
0x9C001E24	G60.9	reserved	Reserved
0x9C001E28	G60.10	iec_cfg	S/PDIF Configuration
0x9C001E2C	G60.11	iec0_valid_out	Valid Bit for S/PDIF TX0
0x9C001E30	G60.12	iec0_par0_out	Channel Status of S/PDIF TX0
0x9C001E34	G60.13	iec0_par1_out	Channel Status of S/PDIF TX0
0x9C001E38	G60.14	iec1_valid_out	Valid Bit for S/PDIF TX1
0x9C001E3C	G60.15	iec1_par0_out	Channel Status of S/PDIF TX1
0x9C001E40	G60.16	iec1_par1_out	Channel Status of S/PDIF TX1
0x9C001E44	G60.17	iec0_rx_debug_info	Debug Information of S/PDIF RX0
0x9C001E48	G60.18	iec0_valid_in	Valid Bit of S/PDIF RX0
0x9C001E4C	G60.19	iec0_par0_in	Channel Status of S/PDIF RX0
0x9C001E50	G60.20	iec0_par1_in	Channel Status of S/PDIF RX0
0x9C001E54	G60.21	iec1_rx_debug_info	Debug Information of S/PDIF RX1
0x9C001E58	G60.22	iec1_valid_in	Valid Bit of S/PDIF RX1
0x9C001E5C	G60.23	iec1_par0_in	Channel Status of S/PDIF RX1
0x9C001E60	G60.24	iec1_par1_in	Channel Status of S/PDIF RX1
0x9C001E64	G60.25	iec2_rx_debug_info	Debug Information of S/PDIF RX2
0x9C001E68	G60.26	iec2_valid_in	Valid Bit of S/PDIF RX2
0x9C001E6C	G60.27	iec2_par0_in	Channel Status of S/PDIF RX2
0x9C001E70	G60.28	iec2_par1_in	Channel Status of S/PDIF RX2
0x9C001E74	G60.29	reserved	SACD Channel Number (Reserved)
0x9C001E78	G60.30	iec_tx_user_wdata	IEC Tx User FIFO Data
0x9C001E7C	G60.31	iec_tx_user_ctrl	IEC Tx User FIFO Control

Address	Group No.	Register Name	Description
0x9C001E80	G61.0	adcp_ch_enable	ADCPRC Configuration Group 1
0x9C001E84	G61.1	adcp_fubypass	ADCPRC Configuration Group 2
0x9C001E88	G61.2	adcp_mode_ctrl	ADCPRC Mode Control
0x9C001E8C	G61.3	adcp_init_ctrl	ADCP Initialization Control
0x9C001E90	G61.4	adcp_coeff_din	Coefficient Data Input
0x9C001E94	G61.5	adcp_agc_cfg	ADCPRC AGC Configuration of Ch0/1
0x9C001E98	G61.6	adcp_agc_cfg2	ADCPRC AGC Configuration of Ch2/3