18. SPI NAND

18.1 Introduction

This section describes the SPI_NAND Controller and its function. The SPI_NAND Controller is used to transmit or receive data with SPI_NAND device. The control registers locate at RGST Table Group 87&88 which memory map address are 0x9C002B80~0x9C002BFF. The SPI_NAND controller has below features.

Support BCH auto encode and decode
Support 32-bit AXI master bus for transferring data between controller and dram for DMA mode
Exchange to 32-bit AXI Slave bus from 32-bit OCP bus
Support auto multi page read
Support auto multi page program
Support enable BCH function for DMA mode
Support SPI_CLK is divided from CLK_SPI, and frequency division coefficient is 1/2, 1/4, 1/6, 1/8, 1/16, 1/24, 1/32

18.2 Function Diagram

A generalized function diagram of SPI_NAND is shown in Figure 18-1. SPI_PROTECT is reserved for SPI_NAND Controller. SPI_PROTECT function is useful for SPI_NOR controller.

Figure 18-1 SPINAND Functional Blocks

SPI_NAND_REG: This block is used for register configure.
SPI_NAND_DMA: Support 32-bit AXI master bus to read/write data between controller and dram for DMA mode.
SPI_NAND_CON: This block is used for controlling the operation flow
SPI_NAND_OUT: SPI interface with external SPI device.
SPI_NAND_ASYNC: For async information between SPI_NAND_CON and SPI_NAND_OUT
SPI_NAND_BCHIF: For auto bch function
SPI_NAND_AXI_S: Exchange to 32-bit AXI Slave bus from 32-bit OCP bus.

18.3 Data Control Timing

SPI_NAND Controller TX timing: The TX output start timing decides by spi_timing[0] which is bit0 of Group 87.1 spi_timing register. When spi_timing[0]=1 , TX will advance one system clock cycle to send data. Please refer to figure 18-2.

Figure 18-2 TX timing chart
SPI_NAND Controller RX timing: The RX timing can be fine tune by spi_timing[3:1] which is bit[3:1] of Group 87.1 spi_timing register.

Figure 18-3 RX timing chart

If the pad TX delay is t1，than from device to response data until SPI Controller receive data the delay is t2.
NEG_SAMPLE is spi_controller default sample point
As above figure，controller can't get correct data in the default sample point，user can fine tune spi_timing[3:1] to get correct read timing. For example, in figure 16-3 set spi_timing[3:1]=1 can get correct sample data.

18.4 SPI NAND Interrupts

The SPI_NAND interrupt events are connected to the same interrupt vector, please refer to figure 18-4. These events generate an interrupt if the corresponding "Mask Bit" isn't set. The mask control register is in Group 87.17. The interrupt status register is in Group 87.18. SPI_NAND controller interrupt is a level signal. It supports three kinds of interrupt status. If one interrupt mask enable, this interrupt will only update the status, the SPINAND_INT will not be set.

Figure 18-4 SPINAND Interrupt Tree
SPI interrupt status register (Group 87.18 spi_intr_sts) description.

PIO_DONE_INTR: When PIO mode transfer finished, spi_intr_sts[2] will be high. Software write 1 to clean this bit.
DMA_DONE_INTR: spi_intr_sts[1] indicate the current dma operation is done. Software can write 1 to clear this bit
BUF_DATA_ENOU_INTR: spi_intr_sts[0] indicate the number of data received from flash has reached the setting amount. Software can write 1 to clear this bit. The amount is set in spi_cfg0[21] which is bit 21 of Group 87.6 register. Set spi_cfg0[21]=1, the buffer size is 32byte. Set spi_cfg0[21]=0, the buffer size is 64byte.

18.5 Registers Map

18.5.1 Registers Memory Map

Address	Group No.	Register Name	Description
0x9C002B80	G87.0	spi ctrl	SPI Control Register
0x9C002B84	G87.1	spi timing	SPI Timing Register
0x9C002B88	G87.2	spi page addr	SPI Page Address Regsister
0x9C002B8C	G87.3	spi data	SPI Data Register
0x9C002B90	G87.4	spi status	SPI Status Register
0x9C002B94	G87.5	spi auto cfg	SPI Configuration1 Register
0x9C002B98	G87.6	spi cfg0	SPI Configuration0 Register
0x9C002B9C	G87.7	spi cfg1	SPI Configuration1 Register
0x9C002BA0	G87.8	spi cfg2	SPI Configuration2 Register
0x9C002BA4	G87.9	spi data 64	SPI Data Buffer Regsiter
0x9C002BA8	G87.10	spi buf addr	SPI Buffer Address Register
0x9C002BAC	G87.11	spi status 2	SPI Status2 Register
0x9C002BB0	G87.12	spi err status	SPI Controller Error Status Register
0x9C002BB4	G87.13	mem data addr	Memory Data Address
0x9C002BB8	G87.14	mem parity addr	Memory Data Address
0x9C002BBC	G87.15	spi col addr	SPI Column Page Address
0x9C002BC0	G87.16	spi bch	SPI BCH configuration Register
0x9C002BC4	G87.17	spi intr msk	SPI Interrupt Mask Register
0x9C002BC8	G87.18	spi intr sts	SPI Interrupt Status Register
0x9C002BCC	G87.19	spi page size	SPI device page size

18.5.2 Registers Description

RGST Table Group 87SPI NAND Controller Registers

87.0 SPI Control Register (spi ctrl)
Address: 0x9C002B80
Reset: 0x0117 0003

Field Name	Bit	Access	Description
SPI BUSY	31	RO	SPI controller busy 0: SPI DEVICE is in IDLE state 1: SPI DEVICE is in busy
Reserved	30	RO	Default to be zero
PAGE ACCESS	29	RW	Page access mode 0: SPI CS B raise when each read command end 1: SPI CS B keep in page mode when read command end and read command is identified (OCP bus read or auto identify customized read command)
AUTO MODE	28	RW	Auto to page program and page read 1'b1: Enable auto mode 1'b0: Disable auto mode Auto mode: CPU will enable controller once to finish a page program or a page read operation.
AUTO CMD EN	27	RW	Auto Command Enable When use Auto mode, user can define the PRGM EXE cmd or READ TO CACHE cmd in regis- ter(SPI CTRL.MULTI CMD). 1'b1: use define cmd MULTI CMD 1'b0: use default cmd(PRGM EXE: 10h, READ TO CACHE: 13h)
AUTO 4BYTE ADDR EN	26	RW	Auto do opearation with 4 bytes addr mode 1'b0: 4bytes addr mode is not auto enabled. 1'b1: 4bytes addr mode is auto enabled. default is 1'b0.
FLASH B SEL	25	RW	Select SPI FLASH Chip B 0: chip B unselected 1: chip B selected
FLASH A SEL	24	RW	Select SPI FLASH Chip A 0: chip A unselected 1: chip A selected
USEABLE DQ	23:20	RW	Useable Serial Interface data bits Bit 4: DQ0 data pin Bit 5: DQ1 data pin Bit 6: DQ2 data pin Bit 7: DQ3 data pin Auto-configure bit mode by this register.(referring to auto- configure table)
AUTO SPI WEL EN	19	RW	Auto write enable latch 0: SPI write enable is not auto enabled 1: SPI write enable is auto enabled This bit only affect OCP bus write command and auto identify customized write command
SCK MODE	18:16	RW	SPI clock frequency division selection 1: CLK SPI/2 2: CLK SPI/4 3: CLK SPI/6 4: CLK SPI/8 5: CLK SPI/16 6: CLK SPI/24 7: CLK SPI/32 Default is 7(32 division) Note: Don't Support SPI CLK = CLK SPI.
MULTI CMD	15:8	RW	Multi command for auto mode cmd or customer cmd to be send to SPI DEVICE Function 1:used for auto mode, user can define PRGM EXE or READ TO CACHE cmd. Function 2: used to define customer command.
SPI NAND EN	7	RW	SPI NAND enable signal 1'b1: Indicate it is SPI NAND controller. 1'b0: Indicate it is SPI NOR controller.
CUSTOMER DATA LEN SRC	6:4	RW	Byte length for SPI data 0: no need to transfer data 1: 1 byte 2: 2 bytes 3: 3 bytes 4: 4 bytes
Reserved	3	RO	Default to be zero
CUSTOMER WRITE SRC	2	RW	Read from or write to flash 0: to read from flash 1: to write to flash
CUST ADDR LEN	1:0	RW	Byte length for SPI address 0: no need to transfer address 1: 1 byte 2: 2 bytes 3: 3 bytes

87.1 SPI Timing Register (spi timing)
Address: 0x9C002B84
Reset: 0x012A 0000

Field Name	Bit	Access	Description
Reserved	31:27	RO	Default to be zero
CS SH CYC	26:22	RW	SPI CS B setup cycles and hold cycles Cycles for SPI CS B setup/hold, setting value = 10(ns)CLK SPI(?MHZ)/1000. For example, when CLK SPI=400MHZ, the setting value = 10400/1000 = 4. Note:10(ns) is SPI FLASH device's real max SPI CS B setup/hold timing.
CS DISACTIVE CYC	21:16	RW	SPI CS B disactive cycles Cycles to separate two SPI CS B, the unit is CLK SPI. setting value = 105(ns)CLK SPI(?MHZ)/1000. For example, when CLK SPI=400MHZ, the setting value = 105400/1000 = 42. Note:105(ns) is SPI FLASH device's real max disactive timing.
Reserved	5:4	RO	Default to be zero
READ TIMING SEL	3:1	RW	Sample read data timing option 0: normal timing (falling edge of SPI CLK) 1: delay 1 CLK SPI cycle from falling edge of SPI CLK to sample data. 2: delay 2 CLK SPI cycle from falling edge of SPI CLK to sample data. 3: delay 3 CLK SPI cycle from falling edge of SPI CLK to sample data. 4: delay 4 CLK SPI cycle from falling edge of SPI CLK to sample data. 5: delay 5 CLK SPI cycle from falling edge of SPI CLK to sample data. 6: delay 6 CLK SPI cycle from falling edge of SPI CLK to sample data. 7: delay 7 CLK SPI cycle from falling edge of SPI CLK to sample data.
WRITE TIMING SEL	0	RW	SPI CLK output timing option 0: normal timing 1: advance one system clock cycle to send data

87.2 SPI Page Address Regsister (spi page addr)
Address: 0x9C002B88
Reset: 0x0

Field Name	Bit	Access	Description
PAGE ADDR BYTE3	31:24	RW	Page Address[31:24] to be send to SPI DEVICE
PAGE ADDR BYTE2	23:16	RW	Page Address[23:16] to be send to SPI DEVICE
PAGE ADDR BYTE1	15:8	RW	Page Address[15:8] to be send to SPI DEVICE
PAGE ADDR BYTE0	7:0	RW	Page Address[7:0] to be send to SPI DEVICE

87.3 SPI Data Register (spi data)
Address: 0x9C002B8C
Reset: 0x0

Field Name	Bit	Access	Description
DATA BYTE3	31:24	RW	DATA[31:24] to be write to or read from SPI DEVICE
DATA BYTE2	23:16	RW	DATA[23:16] to be write to or read from SPI DEVICE
DATA BYTE1	15:8	RW	DATA[15:8] to be write to or read from SPI DEVICE
DATA BYTE0	7:0	RW	DATA[7:0] to be write to or read from SPI DEVICE

87.4 SPI Status Register (spi status)
Address: 0x9C002B90
Reset: 0x0000

Field Name	Bit	Access	Description
Reserved	31:21	RO
PRE FETCH BUSY	20	RO	Indicate pre-fetch operation ongoing
SP2 FLAG CHIP B	19	RO	Indicate SP2 mode of chip B
SP2 FLAG CHIP A	18	RO	Indicate SP2 mode of chip A
ADDR 4BYTE FLAG CHIP B	17	RO	Indicate 4bytes address mode status of chip B 1: current ADDR mode is 4 bytes; 0: ADDR mode is normal mode. This bit will be set to 1'b1 after EN4B command received, 1'b0 after EX4B command received.
ADDR 4BYTE FLAG CHIP A	16	RO	Indicate 4bytes address mode status of chip A 1: current ADDR mode is 4 bytes; 0: ADDR mode is normal mode. This bit will be set to 1'b1 after EN4B command received, 1'b0 after EX4B command received.
Reserved	15:8	RO	Default to be zero
FLASH STATUS	7:0	RO	Status feed back from SPI DEVICE

87.5 SPI Configuration1 Register (spi auto cfg)
Address: 0x9C002B94
Reset: 0x3B00

Field Name	Bit	Access	Description
READ FROM CACHE	31:24	RW	Read from cache command When use the auto mode or DMA function, user can set READ FROM CACHE command.
CONTINUE MODE	23	RW	Winbond Read continue Mode Enable 1'b0: Disable read continue mode. 1'b1: Enable read continue mode.
PRE FETCH EN	22	RW	Pre-fetch enable 0: disable pre-fetch function 1: enable pre-fetch fucntion This bit afffect OCP/CUST read command
REG SPI EN	21	Other	customer command enable/disable 0: customer command has been finished or customer com- mand is not enabled 1: customer command is enabled and triggered Note: User can not set this bit to disable if it is ever setted to enable. It will go to disable after the current executing command is finished.
AUTO RD CMD EN	20	RW	User defined READ FROM CACHE command enable 0: use default READ FROM CACHE read command 1: use user defined command.
CHECK DEVICE OIP	19	RW	Check whether device is busy or not The configureation of GET FEATURE command will be set automatically. Note: It's convenient to check device's OIP-bit using this configuration. Hardware will check the OIP-bit by sending one command and keep reading the OIP-bit. The entire transmission will be finished after the OIP-bit is low.
AUTO RDSR EN	18	RW	Auto read status register enable 0: SPI read status is not auto enabled 1: SPI read status is auto enabled
DMA OWNER	17	RW	DMA Owner bit Indicate whether the register is latched by HW. 1'b0: SW can modify the registers. 1'b1: HW has not latch the registers. Note: the bit only can be set 1 by SW and set 0 by HW.
DUMMY OUT	16	RW	Data in/out selection in dummy cycles 0: SPI DQ will change to input mode in the dummy cycles 1: SPI DQ will change to output mode in the dummy cy- cles
PRGM LOAD	15:8	RW	Page Program Load data command When use the auto mode or DMA function, user can set PRGM LOAD command.
Reserved	7:3	RO	Default to be zero
AUTO WREN 2	2	RW	Auto WREN before program execute When enable this bit, the WREN command will issue before Program Execute command automatically during auto write or dma write operation.
AUTO WREN 1	1	RW	Auto WREN before program load When enable this bit, the WREN command will issue be- fore Program Load command automatically during auto write or dma write operation.
AUTO WR CMD EN	0	RW	User defined PRGM LOAD command enable 0: use default PRGM LOAD commnad 1: use user defined command.

87.6 SPI Configuration0 Register (spi cfg0)
Address: 0x9C002B98
Reset: 0x8 0004

Field Name	Bit	Access	Description
ENHANCE DATA	31:24	RW	Enhance data to be send
ENDIAN MODE	23	RW	Endian mode select for OCP 0: Big endian 1:Little endian
DQ BIT SWITCH	22	RW	Switch serial data pin DQ0 and DQ1 0: DQ1 is high bit and DQ0 is low bit when transferred mode equal to 2 1: DQ0 is high bit and DQ1 is low bit when transferred mode equal to 2
BUF DATA NUM SEL	21	RW	Buffer Data Number Select 1'b1: When receive 32Bytes data into buffer 1'b0: When receive 64Bytes data into buffer There will issue a interrupt after reading the amount of data. But SPI NAND won't stop after interrupt.
DATA64 EN	20	RW	64-byte customized read/write operation enable 1'b0: use SPI DATA. 1'b1: use SPI DATA64.
SPI TRS MODE	19	RW	Transferring mode for auto WREN and RDSR 0: using SPI CFG4,5,6,7 setting 1: SPI mode transferred
ENHANCE 8BITS SEL	18	RW	Enhance Bits to be transferred 0: 4 bits to be transferred(SPI CFG3[15:12]) 1: 8 bits to be transferred
SCK IDLE	17	RW	SPI CLK mode 0: SPI CLK high active at idle state 1: SPI CLK low active at idle state
Reserved	16	RO	Default to be zero
DATA LEN	15:0	Other	Byte length for SPI data Indicate the number of data will be programmed to flash or read from flash no matter under normal/auto mode or DMA mode.

87.7 SPI Configuration1 Register (spi cfg1)
Address: 0x9C002B9C

Reset: 0x00150095

Field Name	Bit	Access	Description
Reserved	31:30	RO	Default to be zero
CUST DUMMY CYC	29:24	RW	Serial interface dummy cycle. The range is from 0 to 63. e
CUST ENHANCE BIT	23:22	RW	Serial interface enhance data mode 0: no need transferred 1: 1 bit mode 2: 2 bit mode 3: 4 bit mode
CUST DATA BIT	21:20	RW	Serial interface data mode 0: no need transferred 1: 1 bit mode 2: 2 bit mode 3: 4 bit mode
CUST ADDR BIT	19:18	RW	Serial interface address mode 0: no need transferred 1: 1 bit mode 2: 2 bit mode 3: 4 bit mode
CUST CMD BIT	17:16	RW	Serial interface command mode 0: no need transferred 1: 1 bit mode 2: 2 bit mode 3: 4 bit mode
Reserved	15:8	RO	Default to be zero
CUST DATA DQ IEN	7:6	RW	Customized DATA bit input enable, mode only affect 1bit 0: input disable 1: DQ0 input enable 2: DQ1 input enable
CUST DATA DQ OEN	5:4	RW	Customized DATA bit output enable, mode only affect 1bit 0: output disable 1: DQ0 output enable 2: DQ0, DQ1 output enable
			3: DQ0, DQ1, DQ2 and DQ3 output enable
CUST ADDR DQ OEN	3:2	RW	Customized ADDR bit output enable, only affect 1bit mode 0: output disable 1: DQ0 output enable 2: DQ0, DQ1 output enable 3: DQ0, DQ1, DQ2 and DQ3 output enable
CUST CMD DQ OEN	1:0	RW	Customized CMD bit output enable, only affect 1bit mode 0: output disable 1: DQ0 output enable 2: DQ0, DQ1 output enable 3: DQ0, DQ1, DQ2 and DQ3 output enable

87.8 SPI Configuration2 Register (spi cfg2)
Address: 0x9C002BA0
Reset: 0x0015 0095

Field Name	Bit	Access	Description
Reserved	31:30	RO	Default to be zero
DMA DUMMY CYC	29:24	RW	Serial interface dummy cycle The range is from 0 to 63. e
DMA ENHANCE BIT	23:22	RW	Serial interface enhance data mode 0: no need transferred 1: 1 bit mode 2: 2 bit mode 3: 4 bit mode
DMA DATA BIT	21:20	RW	Serial interface data mode 0: no need transferred 1: 1 bit mode 2: 2 bit mode 3: 4 bit mode
DMA ADDR BIT	19:18	RW	Serial interface address mode 0: no need transferred 1: 1 bit mode 2: 2 bit mode 3: 4 bit mode
DMA CMD BIT	17:16	RW	Serial interface command mode 0: no need transferred 1: 1 bit mode 2: 2 bit mode 3: 4 bit mode
Reserved	15:8	RO	Default to be zero
DMA DATA DQ IEN	7:6	RW	Customized DATA bit input enable, only affect 1bit mode 0: input disable 1: DQ0 input enable 2: DQ1 input enable
DMA DATA DQ OEN	5:4	RW	Customized DATA bit output enable, only affect 1bit mode 0: output disable 1: DQ0 output enable 2: DQ0, DQ1 output enable 3: DQ0, DQ1, DQ2 and DQ3 output enable
DMA ADDR DQ OEN	3:2	RW	Customized ADDR bit output enable, only affect 1bit mode 0: output disable 1: DQ0 output enable 2: DQ0, DQ1 output enable 3: DQ0, DQ1, DQ2 and DQ3 output enable
DMA CMD DQ OEN	1:0	RW	Customized CMD bit output enable, only affect 1bit mode 0: output disable 1: DQ0 output enable 2: DQ0, DQ1 output enable 3: DQ0, DQ1, DQ2 and DQ3 output enable

87.9 SPI Data Buffer Regsiter (spi data 64)
Address: 0x9C002BA4
Reset: 0x0000

Field Name	Bit	Access	Description
DATA64 BYTE3	31:24	RW	data[31:24] to be write to or read from SPI DEVICE Repeated read this register achieve read data from data buffer when reading from SPI DEVICE, repeated write this register achieve write data to data buffer when any time
DATA64 BYTE2	23:16	RW	data[23:16] to be write to or read from SPI DEVICE Repeated read this register achieve read data from data buffer when reading from SPI DEVICE, repeated write this register achieve write data to data buffer when any time
DATA64 BYTE1	15:8	RW	data[15:8] to be write to or read from SPI DEVICE Repeated read this register achieve read data from data buffer when reading from SPI DEVICE, repeated write this register achieve write data to data buffer when any time
DATA64 BYTE0	7:0	RW	data[7:0] to be write to or read from SPI DEVICE Repeated read this register achieve read data from data buffer when reading from SPI DEVICE, repeated write this register achieve write data to data buffer when any time

87.10 SPI Buffer Address Register (spi buf addr)
Address: 0x9C002BA8
Reset: 0x0000

Field Name	Bit	Access	Description
Reserved	31:22	RO	Default to be zero
BUF RADDR	21:16	RW	SPI DATA64 read address BUF RADDR will decrease by 2 when a read of SPI DATA64 and reading from SPI DEVICE is on going. User can define the start read address of data buffer by setting BUF RADDR.
Reserved	15:6	RO	Default to be zero
BUF WADDR	5:0	RW	SPI DATA64 write address BUF WADDR will increase by 2 when every writing of SPI DATA64. User can define the start write address of data buffer by setting BUF WADDR.

87.11 SPI Status2 Register (spi status 2)
Address: 0x9C002BAC
Reset: 0x0000

Field Name	Bit	Access	Description
Reserved	31:23	RO	Default to be zero
DMA SUB ST	22:20	RO	DMA sub state 0x0: AXI IDLE 0x1: AXI WR INFO 0x2: AXI WR DATA 0x3: AXI RD INFO 0x4: AXI RD DATA
DMA MAIN ST	19:18	RO	DMA main state 0x0: DMA IDLE 0x1: DMA DATA 0x2: DMA PARITY
BCH ST	17:16	RO	DMA main state 0x0: IDLE 0x1: ENCODE 0x2: DECODE
SPI SRAM ST	15:13	RO	Status of SRAM [0]: SRAM conflict, both OCP and customzied read/write at the same time [1]: SRAM empty [2]: SRAM full
SPI CON ST	12:8	RO	Status of block SPI CON 0: Reset flash, Write Disable (04h) 1: Reset flash, reset winbond Quad mode (FFh) 2: Reset flash, reset winbond Dual mode (FFFFh) 3: Command IDLE 4: Read command executing 5: Page access mode reading 6: Write command executing 7: Write enable(WREN) executing 8: Erase executing 9: Read status register(RDSR) executing 10: Enter 4byte address mode executing 11: Exit 4byte address mode executing 12: exit EON SP2 mode executing 13: Temp state for SP2 mode and 4byte address mode change
SPI OUT ST	7:4	RO	Status of block SPI OUT 0: IDLE state 1: SPI CS B go to low and SPI SCK is not active (Setup time) 2: Transmit command to SPI interface 3: Transmit address to SPI interface 4: Transmit enhance data to SPI interface 5: Count dummy cycle 6: Transmit data to SPI interface 7: SPI CS B keep at low and SPI SCK is not active 8: SPI CS B is going to high and SPI SCK is not acitve 9: SPI CS B go to high and begin counting SPI CS B disac- tive cycles
SPI AXIS ST	3:0	RO	Status of block SPI AXIS 0: IDLE state 1: Send command to SPI CON 2: Request data from SPI CON 3: Send data left in inner 32x8 buffers to OCP BUS

87.12 SPI Controller Error Status Register (spi err status)

Address: 0x9C002BB0
Reset: 0x0000

Field Name	Bit	Access	Description
Reserved	15:3	RO
TWO CHIP SEL ERR	2	W1C	Error flag about two chip selected
NO CHIP SEL ERR	1	W1C	Error flag about no chip selected
CUS DATA64 OVERFLOW ERR	0	W1C	Error flag about DATA64 write data overflow to inner SRAM(64X8). For data64 access with the order about write data first, then send write command, the SRAM may hanpen over- flow. At this time, the error flag will be triggered to indicate overflow status.

87.13 Memory Data Address (mem data addr)
Address: 0x9C002BB4
Reset: 0x0000

Field Name	Bit	Access	Description
MEM DATA ADDR	31:0	RW	Memory Data Address DMA data start address

87.14 Memory Data Address (mem parity addr)
Address: 0x9C002BB8
Reset: 0x0000

Field Name	Bit	Access	Description
MEM PARITY ADDR	31:0	RW	Memory Parity Address DMA parity data start address

87.15 SPI Column Page Address (spi col addr)
Address: 0x9C002BBC
Reset: 0x0000

Field Name	Bit	Access	Description
Reserved	31:16	RO	Default to be zero
COL ADDR BYTE1	15:8	RW	SPI Column Addr Column Address[15:8] to be send to SPI device
COL ADDR BYTE0	7:0	RW	SPI Column Addr Column Address[7:0] to be send to SPI device

87.16 SPI BCH configuration Register (spi bch)
Address: 0x9C002BC0
Reset: 0x0000

Field Name	Bit	Access	Description
Reserved	31:16	RO	Default to be zero
BCH DATA LEN	15:8	RW	BCH data length per sector For bch data: 0x0: 0Byte parity data per BCH sector 0x1: 1Byte parity data per BCH sector ... 0xff: 255Byte parity data per BCH sector
Reserved	7	RO	Default to be zero
BCH DATA MODE	6	RW	BCH data mdoe select 0: 512Byte per BCH. 1: 1k Byte per BCH.
BCH ACC	5	RW	32Byte or 16Byte align 0: 32Byte align. 1: 16Byte align.
AUTO BCH EN	4	RW	Auto BCH function enable Write 1 enable. It will encode data before the page program or decode data during page read.
SECTOR NUM	3:0	RW	Set the number N of block for BCH N= 0˜15(1˜16 blocks)

87.17 SPI Interrupt Mask Register (spi intr msk)

Address: 0x9C002BC4
Reset: 0x0000

Field Name	Bit	Access	Description
Reserved	31:3	RO	Default to be zero
PIO DONE MASK	2	RW	PIO done mask High active. it is used to mask the pio done interrupt.
DMA DONE MASK	1	RW	DMA done mask High active. it is used to mask the dma done interrupt.
BUF DATA ENOU MASK	0	RW	Buffer data enough mask High active. it is used to mask the buffer data enough in- terrupt.

87.18 SPI Interrupt Status Register (spi intr sts)

Address: 0x9C002BC8
Reset: 0x0000

Field Name	Bit	Access	Description
Reserved	31:3	RO	Default to be zero
PIO DONE INTR	2	RW	PIO done interrupt When PIO mode transfer finished, it will be high. SW write 1 to clean this bit.
DMA DONE INTR	1	RW	DMA done interrput The current dma operation is done. SW write 1 to clear this bit.
BUF DATA ENOU INTR	0	RW	Buffer data enough interrupt The number of data received from flash has reached the setting amount. The amount is set in spi cfg0[21]. SW write 1 to clear this bit.

87.19 SPI device page size (spi page size)
Address: 0x9C002BCC
Reset: 0x0000

Field Name	Bit	Access	Description
Reserved	31:16	RO	Default to be zero
ECC EN	15	RW	Device ECC enable 0x1: Device enable ECC, the data can not be stored in spare space. 0x0: Device disable ECC, the data can be stored in spare space.
SPARE SIZE LEN	14:4	RW	Device Spare Space length 0x0: 0Byte 0x1: 1Byte ... 0x7ff: 2047Byte Note: When SPI NAND, it is spare space in device; when SPI NOR, it is per page size in device
Reserved	3	RO	Default to be zero
PAGE SIZE LEN	2:0	RW	Page number select Used for auto mode and DMA mode to count the page number. For 0˜7, indicate 1˜8k Byte data per page. Example: 1.ECC enable:the page size only decide by Byte per page PAGE SIZE LEN, if PAGE SIZE LEN = 0x1, it indicates 2k 2. ECC disable:if PAGE SIZE LEN=0x1, and SPARE SIZE LEN = 64Byte, it indicate (2K + 64)Byte per page.