6. Memory Map

6.1 General Description

The SP7021 ARM CPU uses a 32-bit memory map for all accesses. The memory map shows in Table 6-1. At reset, the memory is configured by the internal BootROM mirrored at address 0xFFFF0000 where the ARM will start execution.

Name

CPU view

memory range size

Description

DRAM

0x0000_0000 - 0x1FFF_FFFF

512MB

DRAM memory area

Reserved

0x2000_0000 - 0x6FFF_FFFF

1280MB


FPGA Device

0x7000_0000 - 0x77FF_FFFF

128MB

For FPGA application

Exchange data with external device (FPGA) via FBIO slave port

Reserved

0x7800_0000 - 0x97FF_FFFF

512MB


SPI-NOR Flash (External ROM)

0x9800_0000 - 0x9BFF_FFFF

64MB

External boot ROM area

Device Register

0x9C00_0000 - 0x9DFE_FFFF

32MB

Device Register Space, refer to Section 6.2 Device Register Map for more detail

Reserved

0x9DFF_0000 - 0x9DFF_FFFF

64KB


Internal BootROM0x9E00_0000 - 0x9E0F_FFFF1MBInternal boot ROM area

Reserved

0x9E10_0000 - 0x9E7F_FFFF

7MB


Internal SRAM (CB_DMA0)

0x9E80_0000 - 0x9E81_FFFF

128KB

Access exceeds the CBDMA range, the Write data will be discarded, Read will get the error data, and trigger interrupt

Internal SRAM (CB_DMA1)

0x9E82_0000 - 0x9E82_0FFF

4KB

Access exceeds the CBDMA range, the Write data will be discarded, Read will get the error data, and trigger interrupt

Reserved

0x9EA0_0000 - 0x9EAF_FFFF

1MB


Reserved

0x9EC0_0000 - 0x9EFF_FFFF

4MB


Hivec_ROM

0xFFFF_0000 - 0xFFFF_FFFF

64KB

In the Internal BootROM mode, CPU address will remap from 0xFFFF_xxxx to 0x9E00_xxxx (64KB range) after reset.

In the External Boot from SPI_NOR mode, CPU address will transfer from 0xFFFF_xxxx to 0x9800_xxxx (64KB range)

Table 6-1 Memory Map

6.2 Device Register Map

The device register space, located in the memory map address range of 0x9C000000~0x9DFEFFFF, control most SP7021 functions. The device registers is separated into 2 segments, one is called RGST table (Register table) which base address is 0x9C000000, another one is called AMBA table (Advanced Microcontroller Bus Architecture table) which base address is 0x9C100000. Table 6-2 /6-3 show the group number with memory map start address of each module.

Memory Map Start Address

Data Width

Group No.

Module

Chapter link

0x9C000000

32

0

MOON0

7. System Control

0x9C000080

32

1

MOON1

7. System Control

0x9C000100

32

2

MOON2

7. System Control

0x9C000180

32

3

MOON3

7. System Control

0x9C000200

32

4

MOON4

7. System Control

0x9C000280

32

5

MOON5

7. System Control

0x9C000300

32

6

GPIOXT

7. System Control

0x9C000380

32

7

GPIOXT

7. System Control
0x9C000400168IOP26. IOP8051

0x9C000600

32

12

STC/Timer/Watchdog

10. General Purpose Timers

0x9C000780

32

15

INTERRUPT2

9. Interrupt Controller

0x9C000800

16

16

UA2

/wiki/spaces/doc/pages/461537282

0x9C000880

16

17

UA3

/wiki/spaces/doc/pages/461537282

0x9C000900

16

18

UA0

/wiki/spaces/doc/pages/461537282

0x9C000980

16

19

UA1

/wiki/spaces/doc/pages/461537282

0x9C000A80

32

21

INTERRUPT3

9. Interrupt Controller

0x9C000B00

32

22

SPINOR

17. SPI NOR

0x9C000B80

32

23

SPINOR Protection

17. SPI NOR

0x9C000D00

32

26

CBDMA0

25. CBDMA

0x9C001900

32

50

DPHY0

16. SDRAM

0x9C001980

32

51

DPHY0

16. SDRAM

0x9C001A00

32

52

DPHY0

16. SDRAM

0x9C001A80

32

53

DPHY0

16. SDRAM

0x9C001B80

32

55

DDC0

20. HDMI TX

0x9C002880

32

81

ICM

11. Input Capture Module (ICM)
0x9C0029803283SECGRP1/wiki/spaces/doc/pages/465535013
0x9C002A003284SEC24. SECURITY
0x9C002A803285SEC24. SECURITY

0x9C002B80

32

87

SPINAND

18. SPI NAND

0x9C002C00

32

88

SPINAND Protection

18. SPI NAND

0x9C002D80

32

91

SPI_MASTER_0

/wiki/spaces/doc/pages/461537282

0x9C002E00

32

92

SPI_SLAVE_0

/wiki/spaces/doc/pages/461537282

0x9C003A00

32

116

RTC

8. Real Time Clock (RTC)

0x9C003B00

32

118

CARD0

22. CARD_CTL (eMMC, SD, SDIO)

0x9C003B80

32

119

CARD0

22. CARD_CTL (eMMC, SD, SDIO)

0x9C003C00

32

120

CARD0

22. CARD_CTL (eMMC, SD, SDIO)

0x9C003E80

32

125

CARD1

22. CARD_CTL (eMMC, SD, SDIO)

0x9C003F00

32

126

CARD1

22. CARD_CTL (eMMC, SD, SDIO)

0x9C003F80

32

127

CARD1

22. CARD_CTL (eMMC, SD, SDIO)

0x9C004000

32

128

CARD1

22. CARD_CTL (eMMC, SD, SDIO)

0x9C004080

32

129

CARD1

22. CARD_CTL (eMMC, SD, SDIO)

0x9C004600

32

140

I2CM0

/wiki/spaces/doc/pages/461537282

0x9C004680

32

141

I2CM0_GDMA

/wiki/spaces/doc/pages/461537282

0x9C004700

32

142

I2CM1

/wiki/spaces/doc/pages/461537282

0x9C004780

32

143

I2CM1_GDMA

/wiki/spaces/doc/pages/461537282

0x9C004800

32

144

I2CM2

/wiki/spaces/doc/pages/461537282

0x9C004880

32

145

I2CM2_GDMA

/wiki/spaces/doc/pages/461537282

0x9C004900

32

146

I2CM3

/wiki/spaces/doc/pages/461537282

0x9C004980

32

147

I2CM3_GDMA

/wiki/spaces/doc/pages/461537282

0x9C004A80

32

149

UPHY0

14. Universal Serial Bus (USB)

0x9C004B00

32

150

UPHY1

14. Universal Serial Bus (USB)

0x9C005280

32

165

MIPICSI0

19. MIPI CSI

0x9C005300

32

166

CSIIW0

19. MIPI CSI

0x9C005380

32

167

MIPICSI1

19. MIPI CSI

0x9C005400

32

168

CSIIW1

19. MIPI CSI

0x9C005C80

32

185

DDFCH

21. DISPLAY

0x9C006200

32

196

OSD

21. DISPLAY

0x9C006380

16

199

VPOST

21. DISPLAY

0x9C006700

16

206

GPOST

21. DISPLAY

0x9C006A80

32

213

TGEN

21. DISPLAY

0x9C006D00

16

217

DMIX

21. DISPLAY

0x9C007500

16

234

DVE

21. DISPLAY

0x9C007580

16235DVE21. DISPLAY

0x9C007A00

16

244

PWM

12. Pulse Width Modulation (PWM)

0x9C008400

32

264

CARD4

22. CARD_CTL (eMMC, SD, SDIO)

0x9C008480

32

265

CARD4

22. CARD_CTL (eMMC, SD, SDIO)

0x9C008500

32

266

CARD4

22. CARD_CTL (eMMC, SD, SDIO)

0x9C008580

32

267

CARD4

22. CARD_CTL (eMMC, SD, SDIO)

0x9C008600

32

268

CARD4

22. CARD_CTL (eMMC, SD, SDIO)

0x9C008780

16

271

UA4

/wiki/spaces/doc/pages/461537282

0x9C00BE00

16

380

HDMITX

20. HDMI TX

0x9C00BE80

16

381

HDMITX

20. HDMI TX

0x9C00BF00

16

382

HDMITX

20. HDMI TX

0x9C00BF80

16

383

HDMITX

20. HDMI TX

0x9C00C000

16

384

HDMITX

20. HDMI TX

0x9C00C080

16

385

HDMITX

20. HDMI TX

0x9C00C100

16

386

HDMITX

20. HDMI TX

0x9C00C180

16

387

HDMITX

20. HDMI TX

0x9C00F480

32

489

SPI_MASTER_1

/wiki/spaces/doc/pages/461537282

0x9C00F500

32

490

SPI_SLAVE_1

/wiki/spaces/doc/pages/461537282

0x9C00F600

32

492

SPI_MASTER_2

/wiki/spaces/doc/pages/461537282

0x9C00F680

32

493

SPI_SLAVE_2

/wiki/spaces/doc/pages/461537282

0x9C00F780

32

495

SPI_MASTER_3

/wiki/spaces/doc/pages/461537282

0x9C00F800

32

496

SPI_SLAVE_3

/wiki/spaces/doc/pages/461537282

Table 6-2 Chip control registers group list of RGST table

Memory Map Start Address

Data Width

Module

Chapter Link

0x9C101000

32

BCH

23. BCH

0x9C102000

32

USB0 HOST

14. Universal Serial Bus (USB)

0x9C103000

32

USB1 HOST

14. Universal Serial Bus (USB)

0x9C108000

32

Ethernet Switch

15. Ethernet Switch
0x9C10820032Ethernet Switch15. Ethernet Switch

Table 6-3 Chip control registers group list of AMBA table

6.3 DRAM area

The DRAM area located in memory map address range 0x00000000~0x1FFFFFFF.

6.4 FPGA Device area

The FPGA device area located in memory map address range 0x70000000~0x77FFFFFF, it used for FPGA application.

6.5 External ROM area

The External ROM area located in memory map address range 0x98000000~0x9BFFFFFF. In the External Boot ROM mode, CPU address will transfer from 0xFFFF_xxxx to 0x9800_xxxx and progress boot procedure.

6.6 Internal Boot ROM area

The Internal Boot ROM area located in memory map address range 0x9E000000~0x9E0FFFFF. In the Internal Boot ROM mode, CPU address will transfer from 0xFFFF_xxxx to 0x9E00_xxxx and progress boot procedure.

6.7 Internal SRAM area

The Internal SRAM area include CB_DMA0 and CB_DMA1 which located in memory map address range 0x9E800000~0x9E81FFFF and 0x9E820000~0x9E820FFF. Internal SRAM in addition to the temporary storage data in operation, another function is to let the data have some place before the system has initialized DRAM. In addition, this hardware also provides DMA function, which is quite flexible.

6.8 Hivec_ROM area

The Hivec_ROM area located in memory map address range 0xFFFF0000~0xFFFFFFFF, it used for remap Boot ROM address.