5. Pin Multiplex Function

5.1. Description

There are totally 72 GPIO pins which are separated into 9 I/O ports, and each port contains 8 GPIO signals. The I/O driving capability for signals in GPIO0 is 16mA and 8mA for those in other GPIO ports. All 72 GPIO signals are Tri-state Output with Schmitt Trigger Input.

There are 8 interrupt sources in GPIO1 port and need to be configured as wake-up source.

Internal signals are Multiplex into these 72 GPIO signals in 5 categories: General Purpose Input/Out, Specific Peripheral Signals, FPGA interfaces to connect to external FPGA according to user setting, LCD interface and HDMIDDC interface.

5.2. GPIO Support Function Category Mapping

There are totally 72 pins can be set as general purpose I/O function.

There are totally 64 pins can be set as Multiplex Peripheral Pins. Multiplex Peripheral Pins include ETH_SW, SDIO, PWM, Input Capture, SPI MASTER, SPI SLAVE, I2C MASTER, UART(1~4), TIMER, GPIO INT functions.

There are totally 41 pins can be set as FPGA Bus I/O Interface (FBIO). SP7021 enables FPGA platform expansion through the FBIO interface. But the priority is GPIO function > Peripheral Function > FBIO Function. While use FBIO function , do not set GPIO function and Peripheral function at the same pins.

There are totally 28 pins can be set as LCD Interface.

There are totally 8 pins can be set as HDMI Display Data Channel.

Table 3. shows the full function category mapping for GPIO signals .

Symbol explanation:

• GPIO: General purpose I/O

• MPP: Multiplex Peripheral Pins

• FBIO: FPGA Bus I/O Interface

• LCDIF: LCD Interface

• HDMIDDC: HDMI Display Data Channel

• O: Mean support

• X: Mean no support

• GPIO_Px_xx: The “x” means port number, so P0 means port0. The “xx” means bit number, so 00 means bit0, and so on.1

Table 3. GPIO Support Function Category Mapping

The GPIO function selected method describe in chapter 5.3.

The MPP function selected method describe in chapter 5.4.

The FBIO function selected method describe in chapter 5.5.

The LCDIF function selected method describe in chapter 5.6.

The HDMIDDC function selected method describe in chapter 5.7.

5.3. How to Program General Purpose I/O Ports

There are totally 72 pins can be set as general purpose I/O function. They can be set as Input, Output, Open Drain and Invert state by internal registers. Figure 4 shows GPIO hardware block.

Associated Registers : Group6 / Group7 / Group101. Refer to 6.8 Register Map for details.

Group6.0~7 (abbreviation as G6.0~7) registers are used for set GPIO_MASTER (for source selection, “1” means GPIO, “0” means IOP8051) state. Each bit map to one pin. For example, G6.0[0] control GPIO_P0_00 pin’s GPIO_MASTER state.

Group6.8~15 (abbreviation as G6.8~15) registers are used for set GPIO_OE (means output enable) state. Each bit map to one pin. For example, G6.8[0] control GPIO_P0_00 pin’s GPIO_OE state.

Group6.16~23 (abbreviation as G6.16~23) registers are used for set GPIO_OUT (means output data) state. Each bit map to one pin. For example, G6.16[0] control GPIO_P0_00 pin’s GPIO_OUT state.

Group6.24~27 (abbreviation as G6.24~27) registers are used for set GPIO_IN (means input data) state. Each bit map to one pin. For example, G6.24[0] control GPIO_P0_00 pin’s GPIO_IN state.

Group7.0~7 (abbreviation as G7.0~7) registers are used for set GPIO_I_INV (means input invert) state. Each bit map to one pin. For example, G7.0[0] control GPIO_P0_00 pin’s GPIO_I_INV state.

Group7.8~15(abbreviation as G7.8~15) registers are used for set GPIO_O_INV (means output invert) state. Each bit map to one pin. For example, G7.8[0] control GPIO_P0_00 pin’s GPIO_O_INV state.

Group7.16~23 (abbreviation as G7.16~23) registers are used for set GPIO_OD (means open drain) state. Each bit map to one pin. For example, G7.16[0] control GPIO_P0_00 pin’s GPIO_OD state.

Group101.25~31 (abbreviation as G101.25~31) registers are used for set GPIO_FIRST (for pad control, “1” means GPIO, “0” means Multiplex function ) state. Each bit map to one pin. For example, G101.25[0] control GPIO_P0_00 pin’s GPIO_FIRST state.

Figure 5-1 GPIO Block Diagram

5.3.1. Set General Purpose I/O Pin Method

First step is setting GPIO_MASTER bit to “1”, it means source select as GPIO or IOP(8051).

The GPIO_MASTER bit of GPIO_P0_07~00 map to register G6.0[7:0]. The GPIO_MASTER bit of GPIO_P1_07~00 map to register G6.0[15:8]. The GPIO_MASTER bit of GPIO_P2_07~00 map to register G6.1[7:0]. The GPIO_MASTER bit of GPIO_P3_07~00 map to register G6.1[15:8]. The GPIO_MASTER bit of GPIO_P4_07~00 map to register G6.2[7:0]. The GPIO_MASTER bit of GPIO_P5_07~00 map to register G6.2[15:8]. The GPIO_MASTER bit of GPIO_P6_07~00 map to register G6.3[7:0]. The GPIO_MASTER bit of GPIO_P7_07~00 map to register G6.4[15:8]. The GPIO_MASTER bit of GPIO_P8_07~00 map to register G6.4[7:0].

Second step is setting GPIO_FIRST bit to “1”, it means pad_control select as GPIO.

The GPIO_ FIRST bit of GPIO_P0_07~00 map to register G101.25[7:0]. The GPIO_ FIRST bit of GPIO_P1_07~00 map to register G101.25[15:8]. The GPIO_ FIRST bit of GPIO_P2_07~00 map to register G101.26[7:0]. The GPIO_ FIRST bit of GPIO_P3_07~00 map to register G101.26[15:8]. The GPIO_ FIRST bit of GPIO_P4_07~00 map to register G101.27[7:0]. The GPIO_ FIRST bit of GPIO_P5_07~00 map to register G101.27[15:8]. The GPIO_ FIRST bit of GPIO_P6_07~00 map to register G101.28[7:0]. The GPIO_ FIRST bit of GPIO_P7_07~00 map to register G101.28[15:8]. The GPIO_ FIRST bit of GPIO_P8_07~00 map to register G101.29[7:0].

For example, set GPIO_P0_00 pin to general purpose I/O function, please set registers value as below:

GPIO_P0 port default set as GPIO function.

5.3.2. GPIO control method

For example, set GPIO_P0_00 as output without open drain, please set as below:

For example, set GPIO_P1_00 as output with open drain, please set as below:

5.4. How to program Multiplex Peripheral Pins

All Multiplex Peripheral Pins support means that you can set all Multiplex Peripheral Pin output through GPIO1 ~ GPIO8 ports. Multiplex Peripheral Pins include: ETH_SW, SDIO, PWM, Input Capture, SPI MASTER, SPI SLAVE, I2C MASTER, UART(1~4), TIMER, GPIO INT. Multiplex Peripheral Pin hardware block show as below figure.

Associated Registers : Group2 / Group3 / Group6 / Group101. Refer to 6.8 Register Map for details.

Group2.0~31(abbreviation as G2.0~31) and Group3.0~27(abbreviation as G3.0~27) registers are used for set Multiplex Peripheral signals to Multiplex Peripheral pins. Each byte will map to one signal. For example, G2.0[7:0] control L2SW_CLK_OUT signal. The register value map GPIO formula is (portnumber-1)*8+bitnumber+1. For example, set GPIO_P6_02 as L2SW_CLK_OUT output pin, the register G2.0[7~0] values should be set as 5*8+2+1=43.

Please notice that user should prevent set several signals in the same pin, one signal only can be assign to one pin.

Figure 5-2 Multiplex Peripheral Pin Block Diagram

5.4.1. Set Multiplex Peripheral Pin Method

Just need to set GPIO_FIRST bit to “0” , GPIO_MASTER bit set “X” means don’t care in this case. Regarding registers map, please check 6.3.1 .

For example, set GPIO_P1_00 pin to general purpose I/O function, please set registers values as below:

GPIO_P1~8 ports default set as Multiplex Peripheral Pin.

5.4.2. Set Multiplex Peripheral Pin - ETHERNET_SWITCH pins

There have 2 ETH_SW ports supported in this chip , Each ETH_SW module have 11pins, user can select any signals output in any pins of GPIO_P1~8. The registers G2.0~G2.10 can be used for select ETH_SW signals and pins.

For example, set ETH_SW port0 to GPIO_P5_03~07 and GPIO_P6_00~06 pins.

5.4.3. Set Multiplex Peripheral Pin - SDIO pins

Method same as 5.4.2.

For example, set SDIO port to GPIO_P8_01~06 pins.

5.4.4. Set Multiplex Peripheral Pin - PWM pins

Method same as 5.4.2.

For example, set PWM0~3 to GPIO_P3_04~07 pins.

5.4.5. Set Multiplex Peripheral Pin - Input Capture pins

Method same as 5.4.2.

For example, set ICM0~1 to GPIO_P4_00~03 pins.

5.4.6. Set Multiplex Peripheral Pin - SPI MASTER pins

Method same as 5.4.2.

For example, set SPIM0 to GPIO_P1_06~07 and GPIO_P2_00~02 pins.

5.4.7. Set Multiplex Peripheral Pin - I2C MASTER pins

Method same as 5.4.2.

For example, set I2CM0 to GPIO_P3_00~01 pins.

5.4.8. Set Multiplex Peripheral Pin - UART pins

Method same as 5.4.2.

For example, set UART1 to GPIO_P1_00~01 pins.

5.4.9. Set Multiplex Peripheral Pin - TIMER_INT pins

Method same as 5.4.2.

For example, set TIMER0~1_INT to GPIO_P4_04~05 pins.

5.4.10. Set Multiplex Peripheral Pin - GPIO_INT pins

Method same as 5.4.2.

For example, set GPIO_INT0~1 to GPIO_P5_00~01 pins.

5.5. How to program FBIO function

FBIO function mode can be enabled while G1.1 register bit12 set to 1, GPIO_P0_02 ~ GPIO_P5_02 pins will be set to FBIO function for FPGA usage. But the priority is GPIO function > Multiplex Peripheral Pin > FBIO Function. While use FBIO function, do not set GPIO function and Multiplex Peripheral Pin within GPIO_P0_02 ~ GPIO_P5_02 pins.

5.6. How to program LCDIF function

LCDIF function mode can be enabled while G1.4 register bit6 set to 1, GPIO_P1_04 ~ GPIO_P4_07 pins will be set to LCDIF function for LCD display usage.

Table 4 shows the LCDIF signals description.

Table 4. LCDIF signals description

5.7. How to program HDMIDDC function

HDMIDDC function mode can be enabled while G1.1 register bit14 set 1 and bit13 set 0, GPIO_P8_03 ~ GPIO_P8_06 pins will be set to HDMIDDC function for HDMI display data channel communication usage.

HDMIDDC function mode can be enabled while G1.1 register bit14 set 1 and bit13 set 1, GPIO_P7_04 ~ GPIO_P7_07 pins will be set to HDMIDDC function for HDMI display data channel communication usage.

Table 5 shows the HDMIDDC signals description.

Table 5. HDMIDDC signals description

5.8. Register Map for Multiplex Pins

Table 6. Group2 registers address map

Table 7. Group3 registers address map

Table 8. Group6 registers address map

Table 9. Group7 registers address map

Table 10. Group101 registers address map

For more detail register description please refer to Register-File document.