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5. Pin Multiplex Function

5. Pin Multiplex Function

Owned by Longson Huang
Last updated: Jan 08, 2020 by edwin.chiu (Unlicensed)

5.1. Description

There are totally 72 GPIO pins which are separated into 9 I/O ports, and each port contains 8 GPIO signals. The I/O driving capability for signals in GPIO0 is 16mA and 8mA for those in other GPIO ports. All 72 GPIO signals are Tri-state Output with Schmitt Trigger Input.

There are 8 interrupt sources in GPIO1 port and need to be configured as wake-up source.

Internal signals are Multiplex into these 72 GPIO signals in 5 categories: General Purpose Input/Out, Specific Peripheral Signals, FPGA interfaces to connect to external FPGA according to user setting, LCD interface and HDMIDDC interface.

 

5.2. GPIO Support Function Category Mapping

There are totally 72 pins can be set as general purpose I/O function.

There are totally 64 pins can be set as Multiplex Peripheral Pins. Multiplex Peripheral Pins include ETH_SW, SDIO, PWM, Input Capture, SPI MASTER, SPI SLAVE, I2C MASTER, UART(1~4), TIMER, GPIO INT functions.

There are totally 41 pins can be set as FPGA Bus I/O Interface (FBIO). SP7021 enables FPGA platform expansion through the FBIO interface. But the priority is GPIO function > Peripheral Function > FBIO Function. While use FBIO function , do not set GPIO function and Peripheral function at the same pins.

There are totally 28 pins can be set as LCD Interface.

There are totally 8 pins can be set as HDMI Display Data Channel.

Table 3. shows the full function category mapping for GPIO signals .

 

Symbol explanation:

  • GPIO: General purpose I/O

  • MPP: Multiplex Peripheral Pins

  • FBIO: FPGA Bus I/O Interface

  • LCDIF: LCD Interface

  • HDMIDDC: HDMI Display Data Channel

  • O: Mean support

  • X: Mean no support

  • GPIO_Px_xx: The “x” means port number, so P0 means port0. The “xx” means bit number, so 00 means bit0, and so on.1

 

Pin Name

Pin No
(LQFP176)

GPIO

MPP

FBIO

LCDIF

HDMIDDC

GPIO_P0_00

174

O

X

X

X

X

GPIO_P0_01

175

O

X

X

X

X

GPIO_P0_02

176

O

X

O

X

X

GPIO_P0_03

1

O

X

O

X

X

GPIO_P0_04

2

O

X

O

X

X

GPIO_P0_05

3

O

X

O

X

X

GPIO_P0_06

5

O

X

O

X

X

GPIO_P0_07

6

O

X

O

X

X

GPIO_P1_00

7

O

O

O

X

X

GPIO_P1_01

8

O

O

O

X

X

GPIO_P1_02

9

O

O

O

X

X

GPIO_P1_03

10

O

O

O

X

X

GPIO_P1_04

11

O

O

O

O

X

GPIO_P1_05

12

O

O

O

O

X

GPIO_P1_06

13

O

O

O

O

X

GPIO_P1_07

14

O

O

O

O

X

GPIO_P2_00

15

O

O

O

O

X

GPIO_P2_01

16

O

O

O

O

X

GPIO_P2_02

17

O

O

O

O

X

GPIO_P2_03

18

O

O

O

O

X

GPIO_P2_04

19

O

O

O

O

X

GPIO_P2_05

20

O

O

O

O

X

GPIO_P2_06

21

O

O

O

O

X

GPIO_P2_07

22

O

O

O

O

X

GPIO_P3_00

25

O

O

O

O

X

GPIO_P3_01

26

O

O

O

O

X

GPIO_P3_02

27

O

O

O

O

X

GPIO_P3_03

28

O

O

O

O

X

GPIO_P3_04

29

O

O

O

O

X

GPIO_P3_05

30

O

O

O

O

X

GPIO_P3_06

31

O

O

O

O

X

GPIO_P3_07

32

O

O

O

O

X

GPIO_P4_00

37

O

O

O

O

X

GPIO_P4_01

38

O

O

O

O

X

GPIO_P4_02

39

O

O

O

O

X

GPIO_P4_03

40

O

O

O

O

X

GPIO_P4_04

41

O

O

O

O

X

GPIO_P4_05

42

O

O

O

O

X

GPIO_P4_06

43

O

O

O

O

X

GPIO_P4_07

44

O

O

O

O

X

GPIO_P5_00

47

O

O

O

X

X

GPIO_P5_01

48

O

O

O

X

X

GPIO_P5_02

49

O

O

O

X

X

GPIO_P5_03

50

O

O

X

X

X

GPIO_P5_04

51

O

O

X

X

X

GPIO_P5_05

52

O

O

X

X

X

GPIO_P5_06

53

O

O

X

X

X

GPIO_P5_07

54

O

O

X

X

X

GPIO_P6_00

62

O

O

X

X

X

GPIO_P6_01

63

O

O

X

X

X

GPIO_P6_02

64

O

O

X

X

X

GPIO_P6_03

65

O

O

X

X

X

GPIO_P6_04

66

O

O

X

X

X

GPIO_P6_05

67

O

O

X

X

X

GPIO_P6_06

68

O

O

X

X

X

GPIO_P6_07

69

O

O

X

X

X

GPIO_P7_00

70

O

O

X

X

X

GPIO_P7_01

71

O

O

X

X

X

GPIO_P7_02

72

O

O

X

X

X

GPIO_P7_03

73

O

O

X

X

X

GPIO_P7_04

74

O

O

X

X

O

GPIO_P7_05

75

O

O

X

X

O

GPIO_P7_06

76

O

O

X

X

O

GPIO_P7_07

77