7. SP7021 Reference Circuit
0.9V Power Tree
There is a feedback loop in DC to DC 0.9 circuit, and the 0.9V output is the power source of the C chip.
Pin Name | Pin Number | Type | Description |
---|---|---|---|
VDD09_A | 33, 36, 57 | Power | Power for C chip |
DCDC09_FB | 58 | Analog Input | Feedback Voltage |
DCDC09_VI_VDD33 | 59 | Analog Input | 3.3V Power Input |
DCDC09_VO | 60 | Analog Output | 0.9V Power Output |
Notice:
(1) In typical cases, the internal DC-DC 0.9V efficiency is 73.45~88.16%
Recommended Bead Electrical characteristics:
Part Number: ACMS160808A600
Impedance@100MHz, ohm+/-25%: 60
DC Resistance, ohm(max): 0.04
Rated Current mA(max): 3000
1.2V Power Tree
1.2V is the power source for the CPU chip and Peripheral chip.
Pin Name | Pin Number | Type | Description |
---|---|---|---|
VDD12_A | 35, 56 | Power | Power for C chip |
CVDD12 | 23, 46, 79, 108, 154 | Power | Power for P chip |
VDD12_STH | 34 | Power | Power for CPIO South side |
VDD12_EST | 55 | Power | Power for CPIO east side |
HDMITX_PLL_AVDD12 | 136 | Power | Power for HDMI |
PLL_CVDD12 | 156 | Power | Power for PLL |
DDR3-PHY-1.2CORE | 159, 161 | Power | DDR3-PHY core power |
DCDC12_VO | 171 | Analog Output | 1.2V Power Output |
DCDC12_VI_VDD33 | 172 | Analog Input | 3.3V Power Input |
Notice:
(1) 1.2V external power is needed if 1.2V consumes current more than 1200mA
(2) In typical cases, the internal DC-DC 1.2V efficiency is 76.68~84.87%
1.5V Power Tree
1.5V is the power of built-in DDR and DDR-PHY
Pin Name | Pin Number | Type | Description |
---|---|---|---|
DDR3-K-VDDQ | 157, 166 | Power | DDR3 KGD IO power |
DDR3-PHY-VDDQ | 158, 160, 162 | Power | DDR3-PHY IO power |
DDR3-PHY-3.3PLL | 163 | Power | DDR3-PHY PLL power |
DDR3-PHY-VREF | 164 | Analog Input | DDR3-PHY reference voltage |
DDR3-PHY-PZQ | 165 | Analog Output | DDR3-PHY external reference resistor |
DCDC15_VI_VDD33 | 167 | Analog Input | 3.3V Power Input |
DCDC15_VO | 168 | Analog Output | 1.5V Power Output |
MIPI-CSI
There is one MIPI-CSI Rx interface in SP7021. Two used application circuits are shown as below. One is 4 lane OV9282 camera module, and the other is 1 lane GC0310 camera module.
https://www.ovt.com/sensors/OV9282
http://www.gcoreinc.com/product/showproduct.php?lang=cn&id=32
Note : MIPI layout impedance 100 ohm
Pin Name | Pin Number | Type | Description | Remark |
---|---|---|---|---|
MIPI_D3N | 143 | Analog Input | MIPI Lane3, Data- |
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MIPI_D3P | 144 | Analog Input | MIPI Lane3, Data+ |
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MIPI_D1N | 145 | Analog Input | MIPI Lane1 Data- |
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MIPI_D1P | 146 | Analog Input | MIPI Lane1, Data+ |
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MIPI_SN | 147 | Analog Input | MIPI Clock- |
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MIPI_SP | 148 | Analog Input | MIPI Clock+ |
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MIPI_D0N | 149 | Analog Input | MIPI Lane0, Data- |
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MIPI_D0P | 150 | Analog Input | MIPI Lane0, Data+ |
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MIPI_D2N | 151 | Analog Input | MIPI Lane2, Data- |
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MIPI_D2P | 152 | Analog Input | MIPI Lane2, Data+ |
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MIPIAVDD | 153 | Power | MIPI 1.2V power |
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GPIO_P0_0 | 174 | Digital Output | MIPI power down control siganl | any GPIO |
GPIO_P8_5 | 85 | Digital I/O | MIPI I2C control data (MPI_SDA) | I2C in PinMux |
GPIO_P8_6 | 86 | Digital I/O | MPI I2C control clock (MIPI_SCL) | I2C in PinMux |
HDMI TX
Pin 134 ~ 142 are the HDMI signal output, and there are three control pins need to be assigned for
Note : Differential signals (TXCP/N, TXD0P/N, TXD1P/N and TXD2P/N): 50ohm single_ended, and 100ohm differential
Pin Name | Pin Number | Type | Description | Remark |
---|---|---|---|---|
HDMITX_CN | 134 | Analog Output |
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HDMITX_CP | 135 | Analog Output |
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HDMI_AVDD12 | 136 | Power | HDMI TX PLL Power |
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HDMITX_DN0 | 137 | Analog Output |
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HDMITX_DP0 | 138 | Analog Output |
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HDMITX_DN1 | 139 | Analog Output |
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HDMITX_DP1 | 140 | Analog Output |
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HDMITX_DN2 | 141 | Analog Output |
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HDMITX_DP2 | 142 | Analog Output |
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DDC_SDA | 112, 76, 85 | Digital Output | Display Data Chanel Serial Data | dedicated pin |
DDC_SCL | 113, 77, 86 | Digital Output | Display Data Chanel Serial Clock | dedicated pin |
HDMI_HPD | 114, (any) | Digital Input | Hot Plug Detection | GPIO |
USB
There have two USB ports in SP7021. They all support OTG mode. Please check below table with signals list.
Pin Name | Pin Number | Type | Description |
---|---|---|---|
USB0_VBUS | 125 | Power | USB0 bus power |
USB0_ID | 126 | Digital Input | USB0_ID signal |
USB0_DM | 127 | Analog I/O | USB0_DM signal |
USB0_DP | 128 | Analog I/O | USB0_DP signal |
USB1_DP | 130 | Analog I/O | USB1_DP signal |
USB1_DM | 131 | Analog I/O | USB1_DM signal |
USB1_ID | 132 | Digital Input | USB1_ID signal |
USB1_VBUS | 133 | Power | USB1 bus power |
X'tal
There have two X’tal source in SP7021. One is 27MHz at pin 110 and 111, the other one is 32KHz at pin123 and 124. Please check below table with signals list.
Pin Name | Pin Number | Type | Description |
---|---|---|---|
XTAL_IN | 110 | Analog Input | XTAL_IN signal |
XTAL_OUT | 111 | Analog Output | XTAL_OUT signal |
XTAL32K_IN | 123 | Analog Input | XTAL32K_IN signal |
XTAL32K_OUT | 124 | Analog Output | XTAL32K_OUT signal |
JTAG/SWD
JTAG function pins locate at pin104, 105, 106, 107, 112 and 113. SWD function pins locate at pin102 and 103. Please check below table with signals list.
Pin Name | Pin Number | Type | Description |
---|---|---|---|
SWD_CLK | 102 | Digital Output | SWD clock signal |
SWD_DATA | 103 | Digital I/O | SWD data signal |
JTAG_TDO | 104 | Digital Output | JTAG_TDO signal |
JTAG_RTCK | 105 | Digital Output | JTAG_RTCK signal |
JTAG_TCLK | 106 | Digital Output | JTAG_TCLK signal |
JTAG_TMS | 107 | Digital Output | JTAG_TMS signal |
JTAG_TDI | 112 | Digital Input | JTAG_TDI signal |
JTAG_TRST | 113 | Digital Output | JTAG_TRST signal |
UART
UART0 function pins locate at pin98 and 99. Please check below table with signals list.
Pin Name | Pin Number | Type | Description |
---|---|---|---|
UA0_TX | 98 | Digital Output | UART0 transmitter signal |
UA0_RX | 99 | Digital Input | UART0 receiver signal |
UART1~4 function pins can be output from any GPIOMUX pins by set correct register value. Below figure shows the example of UART2 reference circuit.
Pin Name | Pin Number | Type | Description |
---|---|---|---|
UA2_TX | 15 | Digital Output | UART2 transmitter signal |
UA2_RX | 16 | Digital Input | UART2 receiver signal |
UA2_RTS | 17 | Digital Output | UART2 RTS signal |
UA2_CTS | 18 | Digital Output | UART2 CTS signal |
eMMC
EMMC function pins locate at pin88~97. Please check below table with signals list. The application circuit eMMC component use Micron MTFC4GACAJCN-4M IT.
Pin Name | Pin Number | Type | Description |
---|---|---|---|
EMMC_CMD | 88 | Digital Output | EMMC command signal |
EMMC_D5 | 89 | Digital I/O | EMMC data signal |
EMMC_D3 | 90 | Digital I/O | EMMC data signal |
EMMC_D4 | 91 | Digital I/O | EMMC data signal |
EMMC_D0 | 92 | Digital I/O | EMMC data signal |
EMMC_D1 | 93 | Digital I/O | EMMC data signal |
EMMC_CLK | 94 | Digital Output | EMMC clock signal |
EMMC_D2 | 95 | Digital I/O | EMMC data signal |
EMMC_D7 | 96 | Digital I/O | EMMC data signal |
EMMC_D6 | 97 | Digital I/O | EMMC data signal |
SD card
SD card function pins can be output from multiplex pins by set register Group1.1(sft cfg 1) bit6 to 1. Please check below table with signals list.
Pin Name | Pin Number | Type | Description |
---|---|---|---|
SD_D1 | 81 | Digital I/O | SDIO data signal |
SD_D0 | 82 | Digital I/O | SDIO data signal |
SD_CLK | 83 | Digital Output | SDIO clock signal |
SD_CMD | 84 | Digital Output | SDIO command signal |
SD_D3 | 85 | Digital I/O | SDIO data signal |
SD_D2 | 86 | Digital I/O | SDIO data signal |
SD_SEN | 87 | Digital Output | SDIO enable signal |
Ethernet
Ethernet function pins can be output from any GPIOMUX pin by set correct register value. For example , assign Pin50(GPIO_P5_3) to MAC_SMI_MDIO , Pin51(GPIO_P5_4) to MAC_SMI_MDC , Pin52(GPIO_P5_5) to LED_ON , Pin53(GPIO_P5_6) to RMII_RXER , Pin54(GPIO_P5_7) to RMII_CRSDV , Pin62(GPIO_P6_0) to RMII_RXD0 , Pin63(GPIO_P6_1) to RMII_RXD1 , Pin64(GPIO_P6_2) to RMII_CLKOUT , Pin65(GPIO_P6_3) to RMII_TXD0 , Pin66(GPIO_P6_4) to RMII_TXD1 , Pin67(GPIO_P6_5) to RMII_TXEN , Pin68(GPIO_P6_6) to LED_FLASH.
Pin Name | Pin Number | Type | Description |
---|---|---|---|
MAC_SMI_MDIO | 50 | Digital I/O | MAC_SMI_MDIO signal |
MAC_SMI_MDC | 51 | Digital Output | MAC_SMI_MDC signal |
LED_ON | 52 | Digital Output | LED_ON signal |
RMII_RXER | 53 | Digital Input | RMII_RXER signal |
RMII_CRSDV | 54 | Digital Output | RMII_CRSDV signal |
RMII_RXD0 | 62 | Digital Input | RMII_RXD0 signal |
RMII_RXD1 | 63 | Digital Input | RMII_RXD1 signal |
RMII_CLKOUT | 64 | Digital Output | RMII_CLKOUT signal |
RMII_TXD0 | 65 | Digital Output | RMII_TXD0 signal |
RMII_TXD1 | 66 | Digital Output | RMII_TXD1 signal |
RMII_TXEN | 67 | Digital Output | RMII_TXEN signal |
LED_FLASH | 68 | Digital Output | LED_FLASH signal |
I2C
I2CM function pins can be output from any GPIOMUX pin by set correct register value. For example , assign Pin25(GPIO_P3_0) to I2CM0_CK , Pin26(GPIO_P3_1) to I2CM0_DAT.
Pin Name | Pin Number | Type | Description |
---|---|---|---|
I2CM0_CK | 25 | Digital Output | I2CM clock signal |
I2CM0_DAT | 26 | Digital I/O | I2CM data signal |
SPI
SPI-COMBO function pins can be output from any GPIOMUX pin by set correct register value. For example , assign Pin13(GPIO_P1_6) to SPIM0_INT , Pin14(GPIO_P1_7) to SPIM0_CLK , Pin15(GPIO_P2_0) to SPIM0_EN , Pin16(GPIO_P2_1) to SPIM0_DO , Pin17(GPIO_P2_2) to SPIM0_DI.
Pin Name | Pin Number | Type | Description |
---|---|---|---|
SPIM0_INT | 13 | Digital Output | SPI interrupt signal |
SPIM0_CLK | 14 | Digital Output | SPI clock signal |
SPIM0_EN | 15 | Digital Output | SPI enable signal |
SPIM0_DO | 16 | Digital Output | SPI master data output |
SPIM0_DI | 17 | Digital Input | SPI master receive data from slave |
FPGA
FPGA function pins can be output from GPIOMUX pin by set correct register value. Please check below table with signals list.
Pin Name | Pin Number | Type | Description |
---|---|---|---|
FBIO_PAD_0 | 176 | Digital I/O | FBIO_PAD signal |
FBIO_PAD_1 | 1 | Digital I/O | FBIO_PAD signal |
FBIO_PAD_2 | 2 | Digital I/O | FBIO_PAD signal |
FBIO_PAD_3 | 3 | Digital I/O | FBIO_PAD signal |
FBIO_PAD_4 | 5 | Digital I/O | FBIO_PAD signal |
FBIO_PAD_5 | 6 | Digital I/O | FBIO_PAD signal |
FBIO_PAD_6 | 7 | Digital I/O | FBIO_PAD signal |
FBIO_PAD_7 | 8 | Digital I/O | FBIO_PAD signal |
FBIO_PAD_8 | 9 | Digital I/O | FBIO_PAD signal |
FBIO_PAD_9 | 10 | Digital I/O | FBIO_PAD signal |
FBIO_PAD_10 | 11 | Digital I/O | FBIO_PAD signal |
FBIO_PAD_11 | 12 | Digital I/O | FBIO_PAD signal |
FBIO_PAD_12 | 13 | Digital I/O | FBIO_PAD signal |
FBIO_PAD_13 | 14 | Digital I/O | FBIO_PAD signal |
FBIO_PAD_14 | 15 | Digital I/O | FBIO_PAD signal |
FBIO_PAD_15 | 16 | Digital I/O | FBIO_PAD signal |
FBIO_PAD_16 | 17 | Digital I/O | FBIO_PAD signal |
FBIO_TCLK | 18 | Digital Output | FBIO_PAD signal |
FBIO_RCLK | 19 | Digital Output | FBIO_PAD signal |
FBIO_PAD_17 | 20 | Digital I/O | FBIO_PAD signal |
FBIO_PAD_18 | 21 | Digital I/O | FBIO_PAD signal |
FBIO_PAD_19 | 22 | Digital I/O | FBIO_PAD signal |
FBIO_PAD_20 | 25 | Digital I/O | FBIO_PAD signal |
FBIO_PAD_21 | 26 | Digital I/O | FBIO_PAD signal |
FBIO_PAD_22 | 27 | Digital I/O | FBIO_PAD signal |
FBIO_PAD_23 | 28 | Digital I/O | FBIO_PAD signal |
FBIO_PAD_24 | 29 | Digital I/O | FBIO_PAD signal |
FBIO_PAD_25 | 30 | Digital I/O | FBIO_PAD signal |
FBIO_PAD_26 | 31 | Digital I/O | FBIO_PAD signal |
FBIO_PAD_27 | 32 | Digital I/O | FBIO_PAD signal |
FBIO_PAD_28 | 37 | Digital I/O | FBIO_PAD signal |
FBIO_PAD_29 | 38 | Digital I/O | FBIO_PAD signal |
FBIO_PAD_30 | 39 | Digital I/O | FBIO_PAD signal |
FBIO_PAD_31 | 40 | Digital I/O | FBIO_PAD signal |
FBIO_PAD_32 | 41 | Digital I/O | FBIO_PAD signal |
FBIO_PAD_33 | 42 | Digital I/O | FBIO_PAD signal |
FBIO_PAD_34 | 43 | Digital I/O | FBIO_PAD signal |
FBIO_PAD_35 | 44 | Digital I/O | FBIO_PAD signal |
FBIO_PAD_RSTB | 47 | Digital Output | FBIO_PAD signal |
EXT0_INT | 48 | Digital Output | FBIO_PAD signal |
EXT1_INT | 49 | Digital Output | FBIO_PAD signal |
SPI NAND
SPI NAND function pins can be output from multiplex pins by set register Group1.1(sft cfg 1) bit4 to 1. Please check below table with signals list.
Pin Name | Pin Number | Type | Description |
---|---|---|---|
SPI_NAND_D0 | 92 | Digital I/O | SPI NAND data0 |
SPI_NAND_D2 | 93 | Digital I/O | SPI NAND data2 |
SPI_NAND_CLK | 94 | Digital Output | SPI NAND clock |
SPI_NAND_D1 | 95 | Digital I/O | SPI NAND data1 |
SPI_NAND_D3 | 96 | Digital I/O | SPI NAND data3 |
SPI_NAND_CEN | 97 | Digital Output | SPI NAND chip enable |
SPI NOR
SPI NOR function pins can be output from multiplex pins by set register Group1.1(sft cfg 1) bit1 to 0 and bit0 to 1. Please check below table with signals list.
Pin Name | Pin Number | Type | Description |
---|---|---|---|
SPI_NOR_D2 | 102 | Digital I/O | SPI NOR data2 |
SPI_NOR_CLK | 103 | Digital Output | SPI NOR clock |
SPI_NOR_D1 | 104 | Digital I/O | SPI NOR data1 |
SPI_NOR_D3 | 105 | Digital I/O | SPI NOR data3 |
SPI_NOR_CEN | 106 | Digital Output | SPI NOR chip enable |
SPI_NOR_D0 | 107 | Digital I/O | SPI NOR data0 |